the following patch was just integrated into master:
commit ef639b2dd3ec7d322c59d53e4e614b31e209d8d3
Author: Julius Werner <jwerner(a)chromium.org>
Date: Thu Nov 6 14:33:12 2014 -0800
veyron: Change VCC10_LCD_PWREN_H to allowed maximum of 2.5V
LDO7 (VCC10_LCD_PWREN_H) is essentially just a glorified GPIO that turns
the real VCC10 regulator on or off. We tried setting it to 3.3V since it
matches the VCC33_SYS voltage on the input of that regulator. However,
we didn't notice that the LDO only supports going up to 2.5V.
This patch changes the voltage to the allowed maximum, which should
still work fine as an enable line (and is the same value used by the
kernel). This removes an assertion error in the ramstage.
Also change the PMIC driver to assert maximum VSEL values based on the
LDO, because the lower-voltage ones support one more setting. (LDO3 is
actually listed to only go up to 0b1111 in the manual, and has a weird
jump from 0b1101 -> 2.2V (skipping over 0b1110) to 0b1111 -> 2.5V. I
don't know if that's a documentation error or what they were smoking
when they designed that, but we don't need to care for now.)
BRANCH=None
BUG=None
TEST=Booted on Pinky, no more ASSERTION FAILED.
Change-Id: I38bf99e38822fd0883fd4d0bd9a1b01143545a95
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 70f3149efbc3aa9a03ab3fd5be99d17d9c5e1c87
Original-Change-Id: I68a3bb882cf25d98aca8922ede2a17e1ef6524de
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228292
Original-Commit-Queue: Lin Huang <hl(a)rock-chips.com>
Original-Tested-by: Lin Huang <hl(a)rock-chips.com>
Original-Reviewed-by: Jerry Parson <jwp(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9547
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9547 for details.
-gerrit
the following patch was just integrated into master:
commit 0353c9f640086d543762a12797ba51987bfd6fc5
Author: Julius Werner <jwerner(a)chromium.org>
Date: Thu Nov 6 12:51:24 2014 -0800
veyron_jerry: Remove board ID based assumptions
The veyron_jerry board code was just copied over from veyron_pinky
1-to-1. The Jerry board IDs start at 1, but there has never been a Jerry
rev0 so we can remove the code for board ID 0 from it.
BRANCH=none
BUG=None
TEST=Booted Jerry image on a Pinky rev2, worked fine.
Change-Id: I0f2ffdc577934c1695e8d2dcf71512696ac1d5a5
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: aa36da69ac584b845e15282dae100eec27fc7f12
Original-Change-Id: I45a18b288c8d8b1399ceedf582addcce1c7e857d
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/228254
Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9546
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9546 for details.
-gerrit
the following patch was just integrated into master:
commit f3d5736c8f079321af3cc8dc7210dc0b1a05a327
Author: Doug Anderson <dianders(a)chromium.org>
Date: Tue Oct 28 14:09:47 2014 -0700
veyron: Change eMMC enable pin to be pulled (not driven) high
The eMMC enable pin is in a 3.3V IO domain. Unfortunately the eMMC
expects this pin to be 1.8V. The way we were driving this pin would
cause the eMMC to pull power through this pin and that was causing
current leaks.
In future revisions of hardware we should move this pin somewhere more
legit. However, in the current hardware we can get things working
pretty well by using a pullup to "drive" this pin. This will work in
conjunction with the external 100K pullup to give a somewhat
reasonable voltage. The eMMC will also not be able to pull much
current through this pin, so it can't leak too badly.
BRANCH=none
BUG=chrome-os-partner:33319
TEST=Boot a kernel that doesn't touch the mux/pulls and see no leak:
dut-control --port=${SERVO} vcc_flash_ma -t 5
Change-Id: Ibc25cd090d826c8215be24a0b5c11d97b5281700
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 26e7a9d7e067ed4dd859387ee63bf654ab9dc529
Original-Change-Id: Iadfc1477cd478773cc9d159e3fbc22b66b8f0f78
Original-Signed-off-by: Doug Anderson <dianders(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/226039
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9545
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9545 for details.
-gerrit
the following patch was just integrated into master:
commit b262c726252dc870b373c1e2736699ce172788b1
Author: Katie Roberts-Hoffman <katierh(a)google.com>
Date: Thu Oct 23 19:14:30 2014 -0700
Add google/veyron_jerry board
This is essentially a copy of veyron_pinky for now.
BUG=chrome-os-partner:33269
TEST=build and boot
Change-Id: I151c82f54ece4620953d0db5aedf027a3293926f
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 267611f2354be4384de3f05d2459a4e421ee6b4f
Original-Change-Id: I0d473361e0850ee3b11da5a809f8396826ccdad6
Original-Signed-off-by: Katie Roberts-Hoffman <katierh(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/225301
Reviewed-on: http://review.coreboot.org/9544
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9544 for details.
-gerrit
the following patch was just integrated into master:
commit 103a07fbeb78bf6fc199400da197b86d248093dd
Author: Vadim Bendebury <vbendeb(a)chromium.org>
Date: Thu Oct 23 16:03:29 2014 -0700
storm: copy WiFi calibration data in the CBMEM
Invoke the function which copies WiFi calibration data in a CBMEM
table.
BRANCH=storm
BUG=chrome-os-partner:32611
TEST=verified that the WIFI entry is added to CBMEM when the
calibration data is present in the VPD.
Change-Id: Icab0a2343e88e1d44575eeb608fdf6588aff255b
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 68b96f158633cb3a1f157b5a19da39fa7e78f975
Original-Change-Id: I5fa77da98e37b88da01fb7884e713535fc178006
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/225272
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9543
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9543 for details.
-gerrit
the following patch was just integrated into master:
commit e28fd3626fb740a6b7679bef8a56d109bfa90014
Author: Joseph Lo <josephl(a)nvidia.com>
Date: Fri Nov 21 08:54:15 2014 +0800
tegra132: psci: add cpu_on/off support
The CPU on/off functions are the method for the Kernel to support CPU
hot-plug function in PSCI. To support this, we still need flow controller
support to capture the WFI from the CPU and inform PMC to power gate the
CPU core. On the other path, we turn on the CPU by toggling the PMC and
use flow controller to let go when the power is steady.
BUG=chrome-os-partner:32136
BRANCH=None
TEST=built the kernel with PSCI enabled,
check both of the CPUs are coming up,
test the CPU hot-plug is working on Ryu
Change-Id: If2c529b6719c5747d5aea95fb5049b2d7353ff17
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 0f078e89daad1c4d8b342a395f36b3e922af66f5
Original-Change-Id: Ie49940adb2966dcc9967d2fcc9b1e0dcd6d98743
Original-Signed-off-by: Joseph Lo <josephl(a)nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/231267
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9542
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9542 for details.
-gerrit
the following patch was just integrated into master:
commit 14b444b83be0fe3c3a7fc524265e64d535018049
Author: Furquan Shaikh <furquan(a)google.com>
Date: Fri Nov 21 15:54:39 2014 -0800
arm64: No need of invalidating cache line for secondary CPU stack
With support for initializing registers based on values saved by primary CPU, we
no longer need to invalidate secondary CPU stack cache lines. Before jumping to
C environment, we enable caching and update the required registers.
BUG=chrome-os-partner:33962
BRANCH=None
TEST=Compiles and boots both CPU0 and CPU1 on ryu.
Change-Id: Ifee36302b5de25b909b4570a30ada8ecd742ab82
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 0a0403d06b89dae30b7520747501b0521d16a6db
Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Original-Change-Id: I738250f948e912725264cba3e389602af7510e3e
Original-Reviewed-on: https://chromium-review.googlesource.com/231563
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9541
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9541 for details.
-gerrit
the following patch was just integrated into master:
commit 9482498003d500db6aced4c94bf4ab3485cab18e
Author: Furquan Shaikh <furquan(a)google.com>
Date: Fri Nov 21 15:42:40 2014 -0800
arm64: Add support for save/restore registers for CPU startup.
startup.c provides function to enable CPU in any stage to save register data
that can be used by secondary CPU (for normal boot) or any CPU (for resume
boot). stage_entry.S defines space for saving arm64_startup_data. This can be
filled by:
1) Primary CPU before bringing up secondary CPUs so that the secondary can use
register values to initialize MMU-related and other required registers to
appropriate values.
2) CPU suspend path to ensure that on resume the values which were saved are
restored appropriately.
stage_entry.S provides a common path for both normal and resume boot to
initialize saved registers. For resume path, it is important to set the
secondary entry point for startup since x26 needs to be 1 for enabling MMU and
cache.
This also ensures that we do not fall into false memory cache errors which
caused CPU to fail during normal / resume boot. Thus, we can get rid of the
stack cache invalidate for secondary CPUs.
BUG=chrome-os-partner:33962
BRANCH=None
TEST=Compiles and boots both CPU0 and CPU1 on ryu without mmu_enable and stack
cache invalidate for CPU1.
Change-Id: Ia4ca0e7d35c0738dbbaa926cce4268143c6f9de3
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 9f5e78469313ddd144ad7cf5abc3e07cb712183a
Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Original-Change-Id: I527a95779cf3fed37392b6605b096f54f8286d64
Original-Reviewed-on: https://chromium-review.googlesource.com/231561
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9540
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9540 for details.
-gerrit
the following patch was just integrated into master:
commit ff6d4facbb956175ef6ef9742545924b7fff4fad
Author: Furquan Shaikh <furquan(a)google.com>
Date: Fri Nov 21 15:35:17 2014 -0800
arm64: Add conditional read/write from/to EL3 assembly macros.
Some registers are available only at EL3. Add conditional read/write functions
that perform operations only if currently we are in EL3.
BUG=chrome-os-partner:33962
BRANCH=None
TEST=Compiles and boots to kernel prompt.
Change-Id: Ic95838d10e18f58867b6b77aee937bdacae50597
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 62a0e324a00248dba92cb3e2ac2f4072d0e4e2a7
Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Original-Change-Id: Ia170d94adb9ecc141ff86e4a3041ddbf9045bc89
Original-Reviewed-on: https://chromium-review.googlesource.com/231549
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: http://review.coreboot.org/9538
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/9538 for details.
-gerrit