the following patch was just integrated into master:
commit 28a269abbdb0a47e36529a3d111c06cdcd315d1d
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Fri Feb 6 16:39:30 2015 -0600
hp/pavilion_m6_1035dx/cmos.layout: Remove unused options
Some of the options in cmos.layout date back to the K8 days, and have
not been used anywhere else, but K8. This makes nvramtool expose a
very confusing set of options, most of which have no effect. Clean up
the layout before it gets forked again.
TEST: Booted linux, and checked 'nvramtool -a' output.
Change-Id: I1c5f83790ec89ced4dcf954e4949f8554aef6087
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Reviewed-on: http://review.coreboot.org/8378
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com>
See http://review.coreboot.org/8378 for details.
-gerrit
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9594
-gerrit
commit f5b4fd44b9db42b044454f91ae8dcfebf392e5bd
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Fri Apr 10 22:42:22 2015 +0200
tpm: Only expose base address Kconfig option when enabled
Change-Id: Ia8ddd689a3bf09ed68f94907ea19d4d2ee874542
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
---
src/drivers/pc80/tpm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/drivers/pc80/tpm/Kconfig b/src/drivers/pc80/tpm/Kconfig
index 9630de2..279da39 100644
--- a/src/drivers/pc80/tpm/Kconfig
+++ b/src/drivers/pc80/tpm/Kconfig
@@ -9,6 +9,7 @@ config LPC_TPM
config TPM_TIS_BASE_ADDRESS
hex "TPM Base Address"
default 0xfed40000
+ depends on LPC_TPM
help
This can be used to adjust the TPM memory base address.
The default is specified by the TCG PC Client Specific TPM
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9590
-gerrit
commit 0c7dc654853781fbc196cf29b4b5db0417238eab
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Jan 5 10:47:00 2015 -0800
broadwell: Enable double self refresh by default
Rather than enable this in every mainboard just enable
it by default for all broadwell devices and let a
specific mainboard disable it if needed.
BUG=chrome-os-partner:34420
BRANCH=samus,auron
TEST=build and boot on samus
Change-Id: I6e47c20abf29abfbd1f4b7905914b4c9fadb0ae7
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 25d3a685893e1c85f7b78e302da3187947a1f84f
Original-Change-Id: I26d9f2e2a12d3f2f888ecb5af0d949eec5928f57
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/238400
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/broadwell/pei_data.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c
index b87202f..180f0ca 100644
--- a/src/soc/intel/broadwell/pei_data.c
+++ b/src/soc/intel/broadwell/pei_data.c
@@ -45,4 +45,5 @@ void broadwell_fill_pei_data(struct pei_data *pei_data)
pei_data->tseg_size = smm_region_size();
pei_data->temp_mmio_base = EARLY_TEMP_MMIO;
pei_data->tx_byte = &send_to_console;
+ pei_data->ddr_refresh_2x = 1;
}
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9589
-gerrit
commit 3a94033d9adb32c6a9ff4c475286cfa6cc987298
Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com>
Date: Mon Dec 8 12:51:09 2014 +0000
pistachio: increase the size of romstage to 36K
This is necessary for the subsequent changes that will add to the size
of romstage.
BUG=chrome-os-partner:31438
TEST=coreboot builds successfully;tested on Pistachio FPGA
BRANCH=none
Change-Id: I132215bd44708913d878bbd8b6147bef535b52df
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: 00f73f9d80a36fc43735f093365564b9d74ed7f7
Original-Change-Id: Ie858416a1c9ab63cfe85eea40a76a093cbd2c79c
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/233871
Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org>
---
src/soc/imgtec/pistachio/include/soc/memlayout.ld | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 554ebfc..1c7ea9a 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -29,7 +29,7 @@ SECTIONS
/* GRAM becomes the SRAM. */
SRAM_START(0x9a000000)
BOOTBLOCK(0x9a000000, 16K)
- ROMSTAGE(0x9a004000, 32K)
+ ROMSTAGE(0x9a004000, 36K)
STACK(0x9a01c000, 8K)
PRERAM_CBMEM_CONSOLE(0x9a01e000, 8K)
SRAM_END(0x9a020000)
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9587
-gerrit
commit ac6d64c1f3e81679505239df1cbc2ab8db954c75
Author: Deepa Dinamani <deepad(a)codeaurora.org>
Date: Wed Dec 17 13:40:43 2014 -0800
arch: armv7: Fix cache sync instructions.
When the i-cache is on and the d-cache is off, the L1 i-cache is still
fetching information through L2 cache.
Since L2 cache is never invalidated, it has stale information.
BRANCH=storm
BUG=none
TEST=Resolves the invalidate data fetch from i-cache while jumping from
bootblock to romstage.
Change-Id: Ibaca1219be2e40ce5bbbd1c124863d0ea71d0466
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Original-Commit-Id: a13e20f9b242d8193dcb314a2bdc708c6bdfea51
Original-Change-Id: I252682d372bd505f525f075461b327e4bcf70a1a
Original-Signed-off-by: Deepa Dinamani <deepad(a)codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/236422
Original-Reviewed-by: Trevor Bourget <tbourget(a)codeaurora.org>
Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb(a)chromium.org>
---
src/arch/arm/armv7/cache.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/armv7/cache.c b/src/arch/arm/armv7/cache.c
index 31819f7..1f762b8 100644
--- a/src/arch/arm/armv7/cache.c
+++ b/src/arch/arm/armv7/cache.c
@@ -142,7 +142,15 @@ void dcache_mmu_enable(void)
void cache_sync_instructions(void)
{
- dcache_clean_all(); /* includes trailing DSB (in assembly) */
+ uint32_t sctlr;
+
+ sctlr = read_sctlr();
+
+ if (sctlr & SCTLR_C)
+ dcache_clean_all();
+ else if (sctlr & SCTLR_I)
+ dcache_clean_invalidate_all();
+
iciallu(); /* includes BPIALLU (architecturally) */
dsb();
isb();