coreboot-gerrit March 2015

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Patch set updated for coreboot: 31ba1eb AMD K8: Move SB_HT_CHAIN_ON_BUS0 default 0
by Kyösti Mälkki 27 Mar '15

27 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8353 -gerrit commit 31ba1ebbdaf41759f849a61f0f2b50c8c1b123dc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 5 14:05:51 2015 +0200 AMD K8: Move SB_HT_CHAIN_ON_BUS0 default 0 Define the default value under northbridge. The list of boards this patchset touches will change to use SB_HT_CHAIN_ON_BUS0 with follow-up patch. Based on code analysis, these boards already scan system bus as the first (active) HT chain, so it is placed as bus 0 even when this option was not explicitly selected. Change-Id: I5a00d6372cb89151940aeee517ea613398825c78 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/ibm/e325/Kconfig | 4 ---- src/mainboard/ibm/e326/Kconfig | 4 ---- src/mainboard/iwill/dk8s2/Kconfig | 4 ---- src/mainboard/iwill/dk8x/Kconfig | 4 ---- src/mainboard/newisys/khepri/Kconfig | 4 ---- src/mainboard/tyan/s2850/Kconfig | 4 ---- src/mainboard/tyan/s2875/Kconfig | 4 ---- src/mainboard/tyan/s2880/Kconfig | 4 ---- src/mainboard/tyan/s2882/Kconfig | 4 ---- src/mainboard/tyan/s4880/Kconfig | 4 ---- src/mainboard/tyan/s4882/Kconfig | 4 ---- src/northbridge/amd/amdk8/Kconfig | 4 ++++ 12 files changed, 4 insertions(+), 44 deletions(-) diff --git a/src/mainboard/ibm/e325/Kconfig b/src/mainboard/ibm/e325/Kconfig index 10b6fde..0400677 100644 --- a/src/mainboard/ibm/e325/Kconfig +++ b/src/mainboard/ibm/e325/Kconfig @@ -43,10 +43,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/ibm/e326/Kconfig b/src/mainboard/ibm/e326/Kconfig index 005012a..bd2bb26 100644 --- a/src/mainboard/ibm/e326/Kconfig +++ b/src/mainboard/ibm/e326/Kconfig @@ -43,10 +43,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/iwill/dk8s2/Kconfig b/src/mainboard/iwill/dk8s2/Kconfig index c4de3a1..6b54645 100644 --- a/src/mainboard/iwill/dk8s2/Kconfig +++ b/src/mainboard/iwill/dk8s2/Kconfig @@ -37,10 +37,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/iwill/dk8x/Kconfig b/src/mainboard/iwill/dk8x/Kconfig index af35bb6..f2660c6 100644 --- a/src/mainboard/iwill/dk8x/Kconfig +++ b/src/mainboard/iwill/dk8x/Kconfig @@ -36,10 +36,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/newisys/khepri/Kconfig b/src/mainboard/newisys/khepri/Kconfig index 7f618af..f1c2687 100644 --- a/src/mainboard/newisys/khepri/Kconfig +++ b/src/mainboard/newisys/khepri/Kconfig @@ -30,10 +30,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "Khepri" diff --git a/src/mainboard/tyan/s2850/Kconfig b/src/mainboard/tyan/s2850/Kconfig index e6e3df2..2866b0c 100644 --- a/src/mainboard/tyan/s2850/Kconfig +++ b/src/mainboard/tyan/s2850/Kconfig @@ -40,10 +40,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config APIC_ID_OFFSET hex default 0x0 diff --git a/src/mainboard/tyan/s2875/Kconfig b/src/mainboard/tyan/s2875/Kconfig index 30aa01e..85c3ab4 100644 --- a/src/mainboard/tyan/s2875/Kconfig +++ b/src/mainboard/tyan/s2875/Kconfig @@ -42,10 +42,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config APIC_ID_OFFSET hex default 0x0 diff --git a/src/mainboard/tyan/s2880/Kconfig b/src/mainboard/tyan/s2880/Kconfig index 5186337..62b4e70 100644 --- a/src/mainboard/tyan/s2880/Kconfig +++ b/src/mainboard/tyan/s2880/Kconfig @@ -22,10 +22,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S2880" diff --git a/src/mainboard/tyan/s2882/Kconfig b/src/mainboard/tyan/s2882/Kconfig index 646b5a8..bf980d7 100644 --- a/src/mainboard/tyan/s2882/Kconfig +++ b/src/mainboard/tyan/s2882/Kconfig @@ -23,10 +23,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S2882" diff --git a/src/mainboard/tyan/s4880/Kconfig b/src/mainboard/tyan/s4880/Kconfig index d4feacb..6c85c6c 100644 --- a/src/mainboard/tyan/s4880/Kconfig +++ b/src/mainboard/tyan/s4880/Kconfig @@ -30,10 +30,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S4880" diff --git a/src/mainboard/tyan/s4882/Kconfig b/src/mainboard/tyan/s4882/Kconfig index 2bd3854..7723acf 100644 --- a/src/mainboard/tyan/s4882/Kconfig +++ b/src/mainboard/tyan/s4882/Kconfig @@ -30,10 +30,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S4882" diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 65dc173..8dd8cea 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -65,6 +65,10 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n +config SB_HT_CHAIN_ON_BUS0 + int + default 0 + config QRANK_DIMM_SUPPORT bool default n

1 0

Patch set updated for coreboot: e03aae7 AMD K8 fam10: Refactor Kconfig SB_HT_CHAIN_ON_BUS0
by Kyösti Mälkki 27 Mar '15

27 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8366 -gerrit commit e03aae727a355feacd699511fdaa20a93443d596 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 5 15:48:38 2015 +0200 AMD K8 fam10: Refactor Kconfig SB_HT_CHAIN_ON_BUS0 If SB_HT_CHAIN_ON_BUS0 is selected, HyperTransport chain for System Bus is the first to scan and it will be assigned with bus number 0. If HT_CHAIN_DISTRIBUTE is selected, each link will reserve a fixed range of bus numbers instead of assigning consecutive numbers across all the links. All fam10 have SB_HT_CHAIN_ON_BUS0 selected under northbridge. Follow-up can easily drop this if we find this is dictated by architecture. Change-Id: I8deddcb4c3fd679b6b27e2879d9dba3895c4dd6f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/advansus/a785e-i/Kconfig | 4 ---- src/mainboard/amd/bimini_fam10/Kconfig | 4 ---- src/mainboard/amd/dbm690t/Kconfig | 4 ---- src/mainboard/amd/mahogany/Kconfig | 4 ---- src/mainboard/amd/mahogany_fam10/Kconfig | 4 ---- src/mainboard/amd/pistachio/Kconfig | 4 ---- src/mainboard/amd/serengeti_cheetah/Kconfig | 5 +---- src/mainboard/amd/serengeti_cheetah_fam10/Kconfig | 5 +---- src/mainboard/amd/tilapia_fam10/Kconfig | 4 ---- src/mainboard/arima/hdama/Kconfig | 4 ---- src/mainboard/asrock/939a785gmh/Kconfig | 4 ---- src/mainboard/asus/a8n_e/Kconfig | 5 +---- src/mainboard/asus/a8v-e_deluxe/Kconfig | 4 ---- src/mainboard/asus/a8v-e_se/Kconfig | 4 ---- src/mainboard/asus/k8v-x/Kconfig | 4 ---- src/mainboard/asus/kfsn4-dre/Kconfig | 4 ---- src/mainboard/asus/m2n-e/Kconfig | 5 +---- src/mainboard/asus/m2v-mx_se/Kconfig | 4 ---- src/mainboard/asus/m2v/Kconfig | 4 ---- src/mainboard/asus/m4a78-em/Kconfig | 4 ---- src/mainboard/asus/m4a785-m/Kconfig | 4 ---- src/mainboard/asus/m4a785t-m/Kconfig | 4 ---- src/mainboard/asus/m5a88-v/Kconfig | 4 ---- src/mainboard/avalue/eax-785e/Kconfig | 4 ---- src/mainboard/broadcom/blast/Kconfig | 4 ---- src/mainboard/gigabyte/ga_2761gxdk/Kconfig | 5 +---- src/mainboard/gigabyte/m57sli/Kconfig | 5 +---- src/mainboard/gigabyte/ma785gm/Kconfig | 4 ---- src/mainboard/gigabyte/ma785gmt/Kconfig | 4 ---- src/mainboard/gigabyte/ma78gm/Kconfig | 4 ---- src/mainboard/hp/dl145_g1/Kconfig | 5 +---- src/mainboard/hp/dl145_g3/Kconfig | 5 +---- src/mainboard/hp/dl165_g6_fam10/Kconfig | 5 +---- src/mainboard/iei/kino-780am2-fam10/Kconfig | 4 ---- src/mainboard/iwill/dk8_htx/Kconfig | 5 +---- src/mainboard/jetway/pa78vm5/Kconfig | 4 ---- src/mainboard/kontron/kt690/Kconfig | 4 ---- src/mainboard/msi/ms7135/Kconfig | 5 +---- src/mainboard/msi/ms7260/Kconfig | 5 +---- src/mainboard/msi/ms9185/Kconfig | 5 +---- src/mainboard/msi/ms9282/Kconfig | 4 ---- src/mainboard/msi/ms9652_fam10/Kconfig | 4 ---- src/mainboard/nvidia/l1_2pvv/Kconfig | 5 +---- src/mainboard/siemens/sitemp_g1p1/Kconfig | 4 ---- src/mainboard/sunw/ultra40/Kconfig | 5 +---- src/mainboard/supermicro/h8dme/Kconfig | 5 +---- src/mainboard/supermicro/h8dmr/Kconfig | 5 +---- src/mainboard/supermicro/h8dmr_fam10/Kconfig | 5 +---- src/mainboard/supermicro/h8qme_fam10/Kconfig | 5 +---- src/mainboard/supermicro/h8scm_fam10/Kconfig | 4 ---- src/mainboard/technexion/tim5690/Kconfig | 4 ---- src/mainboard/technexion/tim8690/Kconfig | 4 ---- src/mainboard/tyan/s2881/Kconfig | 5 +---- src/mainboard/tyan/s2885/Kconfig | 5 +---- src/mainboard/tyan/s2891/Kconfig | 5 +---- src/mainboard/tyan/s2892/Kconfig | 5 +---- src/mainboard/tyan/s2895/Kconfig | 5 +---- src/mainboard/tyan/s2912/Kconfig | 5 +---- src/mainboard/tyan/s2912_fam10/Kconfig | 5 +---- src/mainboard/winent/mb6047/Kconfig | 5 +---- src/northbridge/amd/amdfam10/Kconfig | 6 ++++++ src/northbridge/amd/amdfam10/northbridge.c | 4 ++-- src/northbridge/amd/amdk8/Kconfig | 6 ++++-- src/northbridge/amd/amdk8/northbridge.c | 4 ++-- 64 files changed, 41 insertions(+), 246 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig index e76a312..c84bf4d 100644 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ b/src/mainboard/advansus/a785e-i/Kconfig @@ -52,10 +52,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/bimini_fam10/Kconfig b/src/mainboard/amd/bimini_fam10/Kconfig index 369cb7e..261c60a 100644 --- a/src/mainboard/amd/bimini_fam10/Kconfig +++ b/src/mainboard/amd/bimini_fam10/Kconfig @@ -52,10 +52,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/dbm690t/Kconfig b/src/mainboard/amd/dbm690t/Kconfig index 70d63ad..77bafc5 100644 --- a/src/mainboard/amd/dbm690t/Kconfig +++ b/src/mainboard/amd/dbm690t/Kconfig @@ -36,10 +36,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/mahogany/Kconfig b/src/mainboard/amd/mahogany/Kconfig index 394ad77..8861b4a 100644 --- a/src/mainboard/amd/mahogany/Kconfig +++ b/src/mainboard/amd/mahogany/Kconfig @@ -47,10 +47,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/mahogany_fam10/Kconfig b/src/mainboard/amd/mahogany_fam10/Kconfig index ec5ca0b..393882c 100644 --- a/src/mainboard/amd/mahogany_fam10/Kconfig +++ b/src/mainboard/amd/mahogany_fam10/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/pistachio/Kconfig b/src/mainboard/amd/pistachio/Kconfig index 9a91eec..2296e82 100644 --- a/src/mainboard/amd/pistachio/Kconfig +++ b/src/mainboard/amd/pistachio/Kconfig @@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig index e1363eb..2d2d4d1 100644 --- a/src/mainboard/amd/serengeti_cheetah/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah/Kconfig @@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select PARALLEL_CPU_INIT select HAVE_OPTION_TABLE @@ -55,10 +56,6 @@ config MEM_TRAIN_SEQ int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config HT_CHAIN_END_UNITID_BASE hex default 0x6 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig index 2a3e6a7..3e6e025 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8132 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -41,10 +42,6 @@ config MAX_PHYSICAL_CPUS int default 8 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config HT_CHAIN_END_UNITID_BASE hex default 0x6 diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig b/src/mainboard/amd/tilapia_fam10/Kconfig index dd46f6a..491a886 100644 --- a/src/mainboard/amd/tilapia_fam10/Kconfig +++ b/src/mainboard/amd/tilapia_fam10/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/arima/hdama/Kconfig b/src/mainboard/arima/hdama/Kconfig index 49860b3..66177f5 100644 --- a/src/mainboard/arima/hdama/Kconfig +++ b/src/mainboard/arima/hdama/Kconfig @@ -38,10 +38,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/asrock/939a785gmh/Kconfig b/src/mainboard/asrock/939a785gmh/Kconfig index cfaa599..2148385 100644 --- a/src/mainboard/asrock/939a785gmh/Kconfig +++ b/src/mainboard/asrock/939a785gmh/Kconfig @@ -49,10 +49,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/asus/a8n_e/Kconfig b/src/mainboard/asus/a8n_e/Kconfig index 5b7c1e6..1852ae4 100644 --- a/src/mainboard/asus/a8n_e/Kconfig +++ b/src/mainboard/asus/a8n_e/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_939 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select HT_CHAIN_DISTRIBUTE select SUPERIO_ITE_IT8712F select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT @@ -54,10 +55,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 13 diff --git a/src/mainboard/asus/a8v-e_deluxe/Kconfig b/src/mainboard/asus/a8v-e_deluxe/Kconfig index 8ebff31..a1c2fd9 100644 --- a/src/mainboard/asus/a8v-e_deluxe/Kconfig +++ b/src/mainboard/asus/a8v-e_deluxe/Kconfig @@ -33,10 +33,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "A8V-E Deluxe" diff --git a/src/mainboard/asus/a8v-e_se/Kconfig b/src/mainboard/asus/a8v-e_se/Kconfig index d819b0d..dffe9eb 100644 --- a/src/mainboard/asus/a8v-e_se/Kconfig +++ b/src/mainboard/asus/a8v-e_se/Kconfig @@ -33,10 +33,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "A8V-E SE" diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 1deb5b6..52bf661 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -32,10 +32,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "K8V-X" diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index a7ac369..d3477dc 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -40,10 +40,6 @@ config APIC_ID_OFFSET hex default 0 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "KFSN4-DRE" diff --git a/src/mainboard/asus/m2n-e/Kconfig b/src/mainboard/asus/m2n-e/Kconfig index 7292bf3..448cd9f 100644 --- a/src/mainboard/asus/m2n-e/Kconfig +++ b/src/mainboard/asus/m2n-e/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_ITE_IT8716F @@ -57,10 +58,6 @@ config MEM_TRAIN_SEQ int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "M2N-E" diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index 27b8253..3b66235 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -67,10 +67,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/asus/m2v/Kconfig b/src/mainboard/asus/m2v/Kconfig index 35ad38d..72527be 100644 --- a/src/mainboard/asus/m2v/Kconfig +++ b/src/mainboard/asus/m2v/Kconfig @@ -36,10 +36,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "M2V" diff --git a/src/mainboard/asus/m4a78-em/Kconfig b/src/mainboard/asus/m4a78-em/Kconfig index b00a0b6..0382daf 100644 --- a/src/mainboard/asus/m4a78-em/Kconfig +++ b/src/mainboard/asus/m4a78-em/Kconfig @@ -39,10 +39,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/asus/m4a785-m/Kconfig b/src/mainboard/asus/m4a785-m/Kconfig index f93c484..a945d2a 100644 --- a/src/mainboard/asus/m4a785-m/Kconfig +++ b/src/mainboard/asus/m4a785-m/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig index d98ad95..a347f02 100644 --- a/src/mainboard/asus/m4a785t-m/Kconfig +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -42,10 +42,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig index bded839..8a8fcab 100644 --- a/src/mainboard/asus/m5a88-v/Kconfig +++ b/src/mainboard/asus/m5a88-v/Kconfig @@ -50,10 +50,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig index 84f3523..24a5b07 100644 --- a/src/mainboard/avalue/eax-785e/Kconfig +++ b/src/mainboard/avalue/eax-785e/Kconfig @@ -52,10 +52,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/broadcom/blast/Kconfig b/src/mainboard/broadcom/blast/Kconfig index b821f7a..ddd2aca 100644 --- a/src/mainboard/broadcom/blast/Kconfig +++ b/src/mainboard/broadcom/blast/Kconfig @@ -31,10 +31,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "Blast" diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig index a79c28f..e182c99 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig +++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_SIS_SIS966 + select HT_CHAIN_DISTRIBUTE select SUPERIO_ITE_IT8716F select PARALLEL_CPU_INIT select HAVE_OPTION_TABLE @@ -37,10 +38,6 @@ config MEM_TRAIN_SEQ int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "GA-2761GXDK" diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig index 6ef94ce..cc8be43 100644 --- a/src/mainboard/gigabyte/m57sli/Kconfig +++ b/src/mainboard/gigabyte/m57sli/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_ITE_IT8716F @@ -41,10 +42,6 @@ config MEM_TRAIN_SEQ int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "GA-M57SLI-S4" diff --git a/src/mainboard/gigabyte/ma785gm/Kconfig b/src/mainboard/gigabyte/ma785gm/Kconfig index 8f44e76..bf441e9 100644 --- a/src/mainboard/gigabyte/ma785gm/Kconfig +++ b/src/mainboard/gigabyte/ma785gm/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/gigabyte/ma785gmt/Kconfig b/src/mainboard/gigabyte/ma785gmt/Kconfig index 03b9237..827c8da 100644 --- a/src/mainboard/gigabyte/ma785gmt/Kconfig +++ b/src/mainboard/gigabyte/ma785gmt/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/gigabyte/ma78gm/Kconfig b/src/mainboard/gigabyte/ma78gm/Kconfig index 32421e8..3d85708 100644 --- a/src/mainboard/gigabyte/ma78gm/Kconfig +++ b/src/mainboard/gigabyte/ma78gm/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig index 0c6d642..74ce0e7 100644 --- a/src/mainboard/hp/dl145_g1/Kconfig +++ b/src/mainboard/hp/dl145_g1/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8111 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_HARD_RESET select HAVE_OPTION_TABLE @@ -28,10 +29,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "ProLiant DL145 G1" diff --git a/src/mainboard/hp/dl145_g3/Kconfig b/src/mainboard/hp/dl145_g3/Kconfig index 439188a..da20fb3 100644 --- a/src/mainboard/hp/dl145_g3/Kconfig +++ b/src/mainboard/hp/dl145_g3/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 + select HT_CHAIN_DISTRIBUTE select SUPERIO_SERVERENGINES_PILOT select SUPERIO_NSC_PC87417 select HAVE_OPTION_TABLE @@ -56,10 +57,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x6 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 15 diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index bbf5e07..408fe66 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 + select HT_CHAIN_DISTRIBUTE select SUPERIO_SERVERENGINES_PILOT select SUPERIO_NSC_PC87417 select DIMM_DDR2 @@ -55,10 +56,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x6 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 15 diff --git a/src/mainboard/iei/kino-780am2-fam10/Kconfig b/src/mainboard/iei/kino-780am2-fam10/Kconfig index deea898..4b3bce6 100644 --- a/src/mainboard/iei/kino-780am2-fam10/Kconfig +++ b/src/mainboard/iei/kino-780am2-fam10/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/iwill/dk8_htx/Kconfig b/src/mainboard/iwill/dk8_htx/Kconfig index cdfd99a..929f47f 100644 --- a/src/mainboard/iwill/dk8_htx/Kconfig +++ b/src/mainboard/iwill/dk8_htx/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select PARALLEL_CPU_INIT select HAVE_OPTION_TABLE @@ -38,10 +39,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config HT_CHAIN_END_UNITID_BASE hex default 0x6 diff --git a/src/mainboard/jetway/pa78vm5/Kconfig b/src/mainboard/jetway/pa78vm5/Kconfig index b13bead..30478d2 100644 --- a/src/mainboard/jetway/pa78vm5/Kconfig +++ b/src/mainboard/jetway/pa78vm5/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/kontron/kt690/Kconfig b/src/mainboard/kontron/kt690/Kconfig index 8d1f039..e679e66 100644 --- a/src/mainboard/kontron/kt690/Kconfig +++ b/src/mainboard/kontron/kt690/Kconfig @@ -37,10 +37,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/msi/ms7135/Kconfig b/src/mainboard/msi/ms7135/Kconfig index f2cfd9a..50f989e 100644 --- a/src/mainboard/msi/ms7135/Kconfig +++ b/src/mainboard/msi/ms7135/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627THG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -43,10 +44,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 13 diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig index 0e7e592..e3863a0 100644 --- a/src/mainboard/msi/ms7260/Kconfig +++ b/src/mainboard/msi/ms7260/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627EHG @@ -39,10 +40,6 @@ config MEM_TRAIN_SEQ int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "MS-7260" diff --git a/src/mainboard/msi/ms9185/Kconfig b/src/mainboard/msi/ms9185/Kconfig index 0b0ff1c..355fdcf 100644 --- a/src/mainboard/msi/ms9185/Kconfig +++ b/src/mainboard/msi/ms9185/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_BROADCOM_BCM5780 select SOUTHBRIDGE_BROADCOM_BCM5785 + select HT_CHAIN_DISTRIBUTE select SUPERIO_NSC_PC87417 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -34,10 +35,6 @@ config APIC_ID_OFFSET hex default 0x8 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "MS-9185" diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig index f109375..dd96992 100644 --- a/src/mainboard/msi/ms9282/Kconfig +++ b/src/mainboard/msi/ms9282/Kconfig @@ -33,10 +33,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "MS-9282" diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig index c1c095b..c64fdda 100644 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ b/src/mainboard/msi/ms9652_fam10/Kconfig @@ -76,10 +76,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x00 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config VAR_MTRR_HOLE bool default n diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig index 57911f7..e9664ac 100644 --- a/src/mainboard/nvidia/l1_2pvv/Kconfig +++ b/src/mainboard/nvidia/l1_2pvv/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627EHG @@ -43,10 +44,6 @@ config MCP55_NUM int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "l1_2pvv" diff --git a/src/mainboard/siemens/sitemp_g1p1/Kconfig b/src/mainboard/siemens/sitemp_g1p1/Kconfig index dff329f..d9ad74b 100644 --- a/src/mainboard/siemens/sitemp_g1p1/Kconfig +++ b/src/mainboard/siemens/sitemp_g1p1/Kconfig @@ -43,10 +43,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/sunw/ultra40/Kconfig b/src/mainboard/sunw/ultra40/Kconfig index 8f3ff2a..a29cf16 100644 --- a/src/mainboard/sunw/ultra40/Kconfig +++ b/src/mainboard/sunw/ultra40/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select HT_CHAIN_DISTRIBUTE select SUPERIO_SMSC_LPC47B397 select SUPERIO_SMSC_LPC47M10X select HAVE_OPTION_TABLE @@ -56,10 +57,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8dme/Kconfig b/src/mainboard/supermicro/h8dme/Kconfig index 52d5581..35f9bf0 100644 --- a/src/mainboard/supermicro/h8dme/Kconfig +++ b/src/mainboard/supermicro/h8dme/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF @@ -60,10 +61,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8dmr/Kconfig b/src/mainboard/supermicro/h8dmr/Kconfig index f85460b..9efc5d2 100644 --- a/src/mainboard/supermicro/h8dmr/Kconfig +++ b/src/mainboard/supermicro/h8dmr/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF @@ -59,10 +60,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8dmr_fam10/Kconfig b/src/mainboard/supermicro/h8dmr_fam10/Kconfig index 0f94620..0d20204 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/Kconfig +++ b/src/mainboard/supermicro/h8dmr_fam10/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF @@ -55,10 +56,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x1 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8qme_fam10/Kconfig b/src/mainboard/supermicro/h8qme_fam10/Kconfig index 5b195bb..27a74bb 100644 --- a/src/mainboard/supermicro/h8qme_fam10/Kconfig +++ b/src/mainboard/supermicro/h8qme_fam10/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_AMD8132 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -53,10 +54,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x1 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig b/src/mainboard/supermicro/h8scm_fam10/Kconfig index 3105493..0673390 100644 --- a/src/mainboard/supermicro/h8scm_fam10/Kconfig +++ b/src/mainboard/supermicro/h8scm_fam10/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig index 98dce39..0220d77 100644 --- a/src/mainboard/technexion/tim5690/Kconfig +++ b/src/mainboard/technexion/tim5690/Kconfig @@ -37,10 +37,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/technexion/tim8690/Kconfig b/src/mainboard/technexion/tim8690/Kconfig index 4e0b25a..ad80e85 100644 --- a/src/mainboard/technexion/tim8690/Kconfig +++ b/src/mainboard/technexion/tim8690/Kconfig @@ -36,10 +36,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/tyan/s2881/Kconfig b/src/mainboard/tyan/s2881/Kconfig index 6c759e1..de641cd 100644 --- a/src/mainboard/tyan/s2881/Kconfig +++ b/src/mainboard/tyan/s2881/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8111 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -24,10 +25,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2881" diff --git a/src/mainboard/tyan/s2885/Kconfig b/src/mainboard/tyan/s2885/Kconfig index 86e43f8..b218ab7 100644 --- a/src/mainboard/tyan/s2885/Kconfig +++ b/src/mainboard/tyan/s2885/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8151 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -23,10 +24,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2885" diff --git a/src/mainboard/tyan/s2891/Kconfig b/src/mainboard/tyan/s2891/Kconfig index 3d1c1fb..238f5bc 100644 --- a/src/mainboard/tyan/s2891/Kconfig +++ b/src/mainboard/tyan/s2891/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 select SOUTHBRIDGE_AMD_AMD8131 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -23,10 +24,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2891" diff --git a/src/mainboard/tyan/s2892/Kconfig b/src/mainboard/tyan/s2892/Kconfig index b9c4105..cbe076c 100644 --- a/src/mainboard/tyan/s2892/Kconfig +++ b/src/mainboard/tyan/s2892/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 select SOUTHBRIDGE_AMD_AMD8131 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -43,10 +44,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/tyan/s2895/Kconfig b/src/mainboard/tyan/s2895/Kconfig index 544b0c5..21db63c 100644 --- a/src/mainboard/tyan/s2895/Kconfig +++ b/src/mainboard/tyan/s2895/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 select SOUTHBRIDGE_AMD_AMD8131 + select HT_CHAIN_DISTRIBUTE select SUPERIO_SMSC_LPC47B397 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -47,10 +48,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig index 26d9a53..7ad1a1c 100644 --- a/src/mainboard/tyan/s2912/Kconfig +++ b/src/mainboard/tyan/s2912/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select SUPERIO_WINBOND_W83627HF select PARALLEL_CPU_INIT @@ -38,10 +39,6 @@ config MEM_TRAIN_SEQ int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2912" diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index 1dd74ca..b5e31fa 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select SUPERIO_WINBOND_W83627HF select PARALLEL_CPU_INIT @@ -35,10 +36,6 @@ config APIC_ID_OFFSET hex default 0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2912 (Fam10)" diff --git a/src/mainboard/winent/mb6047/Kconfig b/src/mainboard/winent/mb6047/Kconfig index 86b0ae0..622441e 100644 --- a/src/mainboard/winent/mb6047/Kconfig +++ b/src/mainboard/winent/mb6047/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627THG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -25,10 +26,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "MB6047" diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 37993aa..5f6fdec 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -65,6 +65,12 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n +config SB_HT_CHAIN_ON_BUS0 + def_bool y + +config HT_CHAIN_DISTRIBUTE + def_bool n + config DIMM_FBDIMM bool default n diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 8c60e96..5990949 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -197,11 +197,11 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool * so we set the subordinate bus number to 0xff for the moment. */ - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) || !is_sblink) + if (!CONFIG_SB_HT_CHAIN_ON_BUS0 || !is_sblink) max++; /* One node can have 8 link and segn is the same. */ - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) && !is_sblink) + if (CONFIG_HT_CHAIN_DISTRIBUTE && !is_sblink) max = ALIGN_UP(max, 8); link->secondary = max; diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 8dd8cea..fd11105 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -66,8 +66,10 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY default n config SB_HT_CHAIN_ON_BUS0 - int - default 0 + def_bool y + +config HT_CHAIN_DISTRIBUTE + def_bool n config QRANK_DIMM_SUPPORT bool diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 17c5a13..b1c62cd 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -163,11 +163,11 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ * so we set the subordinate bus number to 0xff for the moment. */ - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) || !is_sblink) + if (!CONFIG_SB_HT_CHAIN_ON_BUS0 || !is_sblink) max++; /* Second chain will be on 0x40, third 0x80, forth 0xc0. */ - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) && !is_sblink) + if (CONFIG_HT_CHAIN_DISTRIBUTE && !is_sblink) max = ALIGN_UP(max, 0x40); link->secondary = max;

1 0

Patch set updated for coreboot: 6c75cd6 AMD K8 fam10: Relocate SB_HT_CHAIN in devicetree
by Kyösti Mälkki 27 Mar '15

27 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8560 -gerrit commit 6c75cd6b9ac49e03e55f598af61d7ef79ab306b9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 21 14:31:01 2015 +0200 AMD K8 fam10: Relocate SB_HT_CHAIN in devicetree When we want to scan the HT chain to southbridge first, we relocate it as the first item of dev->link_list of node 0. Change-Id: Ic73ba43aadb3c5e0c8d4b82ed7d41094692ea37f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 45 +++++++++++++++++++++++------ src/northbridge/amd/amdk8/northbridge.c | 46 +++++++++++++++++++++++------- 2 files changed, 72 insertions(+), 19 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 1b91da7..8c60e96 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -250,6 +250,36 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool return link->subordinate; } +/* Do sb ht chain at first, in case s2885 put sb chain + * (8131/8111) on link2, but put 8151 on link0. + */ +static void relocate_sb_ht_chain(void) +{ + struct device *dev; + struct bus *link, *prev = NULL; + u8 sblink; + + if (!CONFIG_SB_HT_CHAIN_ON_BUS0) + return; + + dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + sblink = (pci_read_config32(dev, 0x64)>>8) & 7; + link = dev->link_list; + + while (link) { + if (link->link_num == sblink) { + if (!prev) + return; + prev->next = link->next; + link->next = dev->link_list; + dev->link_list = link; + return; + } + prev = link; + link = link->next; + } +} + static void amdfam10_scan_chains(device_t dev) { unsigned nodeid; @@ -262,15 +292,6 @@ static void amdfam10_scan_chains(device_t dev) /* Do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 */ for (link = dev->link_list; link; link = link->next) { bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); - } - - for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - continue; - max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); } @@ -561,9 +582,15 @@ static const struct pci_driver mcf0_driver __pci_driver = { .device = 0x1200, }; +static void amdfam10_nb_init(void *chip_info) +{ + relocate_sb_ht_chain(); +} + struct chip_operations northbridge_amd_amdfam10_ops = { CHIP_NAME("AMD FAM10 Northbridge") .enable_dev = 0, + .init = amdfam10_nb_init, }; static void amdfam10_domain_read_resources(device_t dev) diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 12d153a..17c5a13 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -223,6 +223,36 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ return link->subordinate; } +/* Do sb ht chain at first, in case s2885 put sb chain + * (8131/8111) on link2, but put 8151 on link0. + */ +static void relocate_sb_ht_chain(void) +{ + struct device *dev; + struct bus *link, *prev = NULL; + u8 sblink; + + if (!CONFIG_SB_HT_CHAIN_ON_BUS0) + return; + + dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + sblink = (pci_read_config32(dev, 0x64)>>8) & 3; + link = dev->link_list; + + while (link) { + if (link->link_num == sblink) { + if (!prev) + return; + prev->next = link->next; + link->next = dev->link_list; + dev->link_list = link; + return; + } + prev = link; + link = link->next; + } +} + static void amdk8_scan_chains(device_t dev) { unsigned nodeid; @@ -234,18 +264,8 @@ static void amdk8_scan_chains(device_t dev) if (nodeid == 0) sblink = (pci_read_config32(dev, 0x64)>>8) & 3; - // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 for (link = dev->link_list; link; link = link->next) { bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); - } - - for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - continue; - max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); } @@ -618,9 +638,15 @@ static const struct pci_driver mcf0_driver __pci_driver = { .device = 0x1100, }; +static void amdk8_nb_init(void *chip_info) +{ + relocate_sb_ht_chain(); +} + struct chip_operations northbridge_amd_amdk8_ops = { CHIP_NAME("AMD K8 Northbridge") .enable_dev = 0, + .init = amdk8_nb_init, }; static void amdk8_domain_read_resources(device_t dev)

1 0

Patch set updated for coreboot: 45a2182 AMD K8 fam10: Always have SB_HT_CHAIN_ON_BUS0
by Kyösti Mälkki 27 Mar '15

27 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8561 -gerrit commit 45a2182e5ed43ad2ae69927827450e28667644d5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 5 15:43:23 2015 +0200 AMD K8 fam10: Always have SB_HT_CHAIN_ON_BUS0 Change-Id: I65fad1cfba95f0ee1ed3f7f7a57d874144da1e40 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/Kconfig | 3 --- src/northbridge/amd/amdfam10/northbridge.c | 5 +---- src/northbridge/amd/amdk8/Kconfig | 3 --- src/northbridge/amd/amdk8/northbridge.c | 5 +---- 4 files changed, 2 insertions(+), 14 deletions(-) diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 5f6fdec..900d81b 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -65,9 +65,6 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n -config SB_HT_CHAIN_ON_BUS0 - def_bool y - config HT_CHAIN_DISTRIBUTE def_bool n diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 5990949..dddc048 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -197,7 +197,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool * so we set the subordinate bus number to 0xff for the moment. */ - if (!CONFIG_SB_HT_CHAIN_ON_BUS0 || !is_sblink) + if (!is_sblink) max++; /* One node can have 8 link and segn is the same. */ @@ -259,9 +259,6 @@ static void relocate_sb_ht_chain(void) struct bus *link, *prev = NULL; u8 sblink; - if (!CONFIG_SB_HT_CHAIN_ON_BUS0) - return; - dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); sblink = (pci_read_config32(dev, 0x64)>>8) & 7; link = dev->link_list; diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index fd11105..6096ab5 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -65,9 +65,6 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n -config SB_HT_CHAIN_ON_BUS0 - def_bool y - config HT_CHAIN_DISTRIBUTE def_bool n diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index b1c62cd..282993e 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -163,7 +163,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ * so we set the subordinate bus number to 0xff for the moment. */ - if (!CONFIG_SB_HT_CHAIN_ON_BUS0 || !is_sblink) + if (!is_sblink) max++; /* Second chain will be on 0x40, third 0x80, forth 0xc0. */ @@ -232,9 +232,6 @@ static void relocate_sb_ht_chain(void) struct bus *link, *prev = NULL; u8 sblink; - if (!CONFIG_SB_HT_CHAIN_ON_BUS0) - return; - dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); sblink = (pci_read_config32(dev, 0x64)>>8) & 3; link = dev->link_list;

1 0

Patch set updated for coreboot: 10ed3a0 AMD K8 fam10: Refactor HT link connection test FIXME
by Kyösti Mälkki 27 Mar '15

27 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8562 -gerrit commit 10ed3a0b95b098ad769cf97e3e8891dcd7cd099d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 23 00:34:26 2015 +0200 AMD K8 fam10: Refactor HT link connection test FIXME Change-Id: I1e935a6b848a59f7f2e58779bceea599032de9e3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/hypertransport.c | 17 +++++++++++++ src/include/device/device.h | 1 + src/include/device/hypertransport.h | 7 ++++++ src/northbridge/amd/amdfam10/northbridge.c | 38 ++++++++++++------------------ src/northbridge/amd/amdk8/northbridge.c | 37 ++++++++++++----------------- 5 files changed, 55 insertions(+), 45 deletions(-) diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index f1d1f08..fa64629 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -507,6 +507,23 @@ void ht_scan_bridge(struct device *dev) do_pci_scan_bridge(dev, hypertransport_scan_chain_x); } +bool ht_is_non_coherent_link(struct bus *link) +{ + u32 link_type; + do { + link_type = pci_read_config32(link->dev, link->cap + 0x18); + } while (link_type & ConnectionPending); + + if (!(link_type & LinkConnected)) + return false; + + do { + link_type = pci_read_config32(link->dev, link->cap + 0x18); + } while (!(link_type & InitComplete)); + + return !!(link_type & NonCoherent); +} + /** Default device operations for hypertransport bridges */ static struct pci_operations ht_bus_ops_pci = { .set_subsystem = 0, diff --git a/src/include/device/device.h b/src/include/device/device.h index da59024..a09413f 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -90,6 +90,7 @@ struct bus { unsigned reset_needed : 1; unsigned disable_relaxed_ordering : 1; + unsigned ht_link_up : 1; }; /* diff --git a/src/include/device/hypertransport.h b/src/include/device/hypertransport.h index 22e0ac4..9885fdf 100644 --- a/src/include/device/hypertransport.h +++ b/src/include/device/hypertransport.h @@ -3,6 +3,13 @@ #include <device/hypertransport_def.h> +/* FIXME */ +#define LinkConnected (1 << 0) +#define InitComplete (1 << 1) +#define NonCoherent (1 << 2) +#define ConnectionPending (1 << 4) +bool ht_is_non_coherent_link(struct bus *link); + unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned *ht_unit_base, unsigned offset_unitid); void ht_scan_bridge(struct device *dev); diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index dddc048..e6a1dc7 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -139,23 +139,6 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn) } -static bool is_non_coherent_link(struct device *dev, struct bus *link) -{ - u32 link_type; - do { - link_type = pci_read_config32(dev, link->cap + 0x18); - } while (link_type & ConnectionPending); - - if (!(link_type & LinkConnected)) - return false; - - do { - link_type = pci_read_config32(dev, link->cap + 0x18); - } while (!(link_type & InitComplete)); - - return !!(link_type & NonCoherent); -} - static void ht_route_link(struct bus *link) { u32 busses; @@ -181,11 +164,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_devfn; - /* Check for connected link. */ - link->cap = 0x80 + (link->link_num * 0x20); - if (!is_non_coherent_link(dev, link)) - return max; - /* See if there is an available configuration space mapping * register in function 1. */ @@ -277,6 +255,17 @@ static void relocate_sb_ht_chain(void) } } +static void trim_ht_chain(struct device *dev) +{ + struct bus *link; + + /* Check for connected link. */ + for (link = dev->link_list; link; link = link->next) { + link->cap = 0x80 + (link->link_num * 0x20); + link->ht_link_up = ht_is_non_coherent_link(link); + } +} + static void amdfam10_scan_chains(device_t dev) { unsigned nodeid; @@ -287,9 +276,12 @@ static void amdfam10_scan_chains(device_t dev) nodeid = amdfam10_nodeid(dev); /* Do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 */ + trim_ht_chain(dev); + for (link = dev->link_list; link; link = link->next) { bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); + if (link->ht_link_up) + max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); } dev->bus->subordinate = max; diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 282993e..7afdbb7 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -79,23 +79,6 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static bool is_non_coherent_link(struct device *dev, struct bus *link) -{ - u32 link_type; - do { - link_type = pci_read_config32(dev, link->cap + 0x18); - } while (link_type & ConnectionPending); - - if (!(link_type & LinkConnected)) - return false; - - do { - link_type = pci_read_config32(dev, link->cap + 0x18); - } while (!(link_type & InitComplete)); - - return !!(link_type & NonCoherent); -} - static void ht_route_link(struct bus *link) { u32 busses; @@ -127,10 +110,6 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_devfn; - link->cap = 0x80 + (link->link_num * 0x20); - if (!is_non_coherent_link(dev, link)) - return max; - /* See if there is an available configuration space mapping * register in function 1. */ @@ -250,6 +229,17 @@ static void relocate_sb_ht_chain(void) } } +static void trim_ht_chain(struct device *dev) +{ + struct bus *link; + + /* Check for connected links. */ + for (link = dev->link_list; link; link = link->next) { + link->cap = 0x80 + (link->link_num * 0x20); + link->ht_link_up = ht_is_non_coherent_link(link); + } +} + static void amdk8_scan_chains(device_t dev) { unsigned nodeid; @@ -261,9 +251,12 @@ static void amdk8_scan_chains(device_t dev) if (nodeid == 0) sblink = (pci_read_config32(dev, 0x64)>>8) & 3; + trim_ht_chain(dev); + for (link = dev->link_list; link; link = link->next) { bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); + if (link->ht_link_up) + max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); } dev->bus->subordinate = max;

1 0

Patch set updated for coreboot: 9445086 AMD K8 fam10: Eliminate local variable min_bus
by Kyösti Mälkki 27 Mar '15

27 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8364 -gerrit commit 9445086e627a8cffdf3423e4d125b48e1cf9dd77 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 5 08:12:20 2015 +0200 AMD K8 fam10: Eliminate local variable min_bus Some cases of max==0xff wrapping around the 8-bit link->secondary register remain to be solved. Change-Id: I01e2ab6b2f23a03dbac49207ab584eccd1ca9b1f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 19 +++++++------------ src/northbridge/amd/amdk8/northbridge.c | 16 +++++++--------- 2 files changed, 14 insertions(+), 21 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 1a77594..d9b4648 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -180,7 +180,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool unsigned int next_unitid; u32 ht_c_index; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain - u32 min_bus; u32 max_devfn; /* Check for connected link. */ @@ -201,25 +200,21 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool */ if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) { - min_bus = ++max; + max++; } else if (is_sblink) { - // first chain will on bus 0 - min_bus = max; /* actually max is 0 here */ + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) { - min_bus = ++max; + max++; } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) { - // second chain will be on 0x40, third 0x80, forth 0xc0 - // i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0 - // >4 will use more segments, // We can have 16 segmment and every segment have 256 bus, // For that case need the kernel support mmio pci config. /* One node can have 8 link and segn is the same. */ - min_bus = (((max & 0xff) >> 3) + 1) << 3; - max = min_bus; + max++; + max = ALIGN_UP(max, 8); } - link->secondary = min_bus; + link->secondary = max; link->subordinate = 0xfc; ht_route_link(link); @@ -236,7 +231,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool } //if ext conf is enabled, only need use 0x1f - if (min_bus == 0) + if (link->secondary == 0) max_devfn = (0x17<<3) | 7; else max_devfn = (0x1f<<3) | 7; diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index be9cb95..f16111b 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -125,7 +125,6 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ u32 config_busses; u32 free_reg, config_reg; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain - u32 min_bus; u32 max_devfn; link->cap = 0x80 + (link->link_num * 0x20); @@ -164,19 +163,18 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ * so we set the subordinate bus number to 0xff for the moment. */ if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) { - min_bus = ++max; + max++; } else if (is_sblink) { - // first chain will on bus 0 - min_bus = max; /* actually max is 0 here */ + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) { - min_bus = ++max; + max++; } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) { /* Second chain will be on 0x40, third 0x80, forth 0xc0. */ - min_bus = (max & ~0x3f) + 0x40; - max = min_bus; + max++; + max = ALIGN_UP(max, 0x40); } - link->secondary = min_bus; + link->secondary = max; link->subordinate = 0xff; ht_route_link(link); @@ -198,7 +196,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ ht_unitid_base[i] = 0x20; } - if (min_bus == 0) + if (link->secondary == 0) max_devfn = (0x17<<3) | 7; else max_devfn = (0x1f<<3) | 7;

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Patch set updated for coreboot: 3288ebd AMD K8 fam10: Refactor logic around SB_HT_CHAIN_ON_BUS0
by Kyösti Mälkki 27 Mar '15

27 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8365 -gerrit commit 3288ebd3c3b16bcb6402f2637b60b7b513a73d3d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 5 13:36:54 2015 +0200 AMD K8 fam10: Refactor logic around SB_HT_CHAIN_ON_BUS0 Change-Id: I452a93af452073eeac4e6cb9bbc232dc59e911c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 14 +++----------- src/northbridge/amd/amdk8/northbridge.c | 12 ++++-------- 2 files changed, 7 insertions(+), 19 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 32e3230..1b91da7 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -197,20 +197,12 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool * so we set the subordinate bus number to 0xff for the moment. */ - if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) { + if ((CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) || !is_sblink) max++; - } else if (is_sblink) { - } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) { - max++; - } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) { - // We can have 16 segmment and every segment have 256 bus, - // For that case need the kernel support mmio pci config. - - /* One node can have 8 link and segn is the same. */ - max++; + /* One node can have 8 link and segn is the same. */ + if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) && !is_sblink) max = ALIGN_UP(max, 8); - } link->secondary = max; link->subordinate = 0xfc; diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index fb2e5bc..12d153a 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -162,17 +162,13 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ * We have no idea how many busses are behind this bridge yet, * so we set the subordinate bus number to 0xff for the moment. */ - if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) { - max++; - } else if (is_sblink) { - } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) { - max++; - } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) { - /* Second chain will be on 0x40, third 0x80, forth 0xc0. */ + if ((CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) || !is_sblink) max++; + + /* Second chain will be on 0x40, third 0x80, forth 0xc0. */ + if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) && !is_sblink) max = ALIGN_UP(max, 0x40); - } link->secondary = max; link->subordinate = 0xff;

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Patch set updated for coreboot: 5165e9f AMD K8 fam10: Drop redundant parameters on scan_chain()
by Kyösti Mälkki 27 Mar '15

27 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8563 -gerrit commit 5165e9fbcd315725ab2062790f317041e3fefecb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 28 12:03:20 2015 +0200 AMD K8 fam10: Drop redundant parameters on scan_chain() Change-Id: I6041b666e6792cf97b8273ed54832d86af8ed23e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 16 +++++----------- src/northbridge/amd/amdk8/northbridge.c | 16 ++++++---------- 2 files changed, 11 insertions(+), 21 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index e6a1dc7..224d451 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -153,17 +153,16 @@ static void ht_route_link(struct bus *link) pci_write_config32(link->dev, link->cap + 0x14, busses); } -static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_sblink, - u32 max) +static u32 amdfam10_scan_chain(struct bus *link, u32 max) { -// I want to put sb chain in bus 0 can I? - - int i; unsigned int next_unitid; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_devfn; + u32 nodeid = amdfam10_nodeid(link->dev); + bool is_sblink = (nodeid == 0) && (link->link_num == sysconf.sblk); + /* See if there is an available configuration space mapping * register in function 1. */ @@ -268,20 +267,15 @@ static void trim_ht_chain(struct device *dev) static void amdfam10_scan_chains(device_t dev) { - unsigned nodeid; struct bus *link; - unsigned sblink = sysconf.sblk; unsigned int max = dev->bus->subordinate; - nodeid = amdfam10_nodeid(dev); - /* Do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 */ trim_ht_chain(dev); for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); if (link->ht_link_up) - max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); + max = amdfam10_scan_chain(link, max); } dev->bus->subordinate = max; diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 7afdbb7..2100cba 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -100,8 +100,7 @@ static u32 amdk8_nodeid(device_t dev) return (dev->path.pci.devfn >> 3) - 0x18; } -static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_sblink, - u32 max) +static u32 amdk8_scan_chain(struct bus *link, u32 max) { int i; unsigned int next_unitid; @@ -110,6 +109,10 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_devfn; + u32 nodeid = amdk8_nodeid(link->dev); + unsigned int sblink = (pci_read_config32(link->dev, 0x64)>>8) & 3; + bool is_sblink = (nodeid == 0) && (link->link_num == sblink); + /* See if there is an available configuration space mapping * register in function 1. */ @@ -242,21 +245,14 @@ static void trim_ht_chain(struct device *dev) static void amdk8_scan_chains(device_t dev) { - unsigned nodeid; struct bus *link; - unsigned sblink = 0; unsigned int max = dev->bus->subordinate; - nodeid = amdk8_nodeid(dev); - if (nodeid == 0) - sblink = (pci_read_config32(dev, 0x64)>>8) & 3; - trim_ht_chain(dev); for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); if (link->ht_link_up) - max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); + max = amdk8_scan_chain(link, max); } dev->bus->subordinate = max;

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Patch set updated for coreboot: 49898c2 AMD K8 fam10: Eliminate local variables busn and max_bus
by Kyösti Mälkki 27 Mar '15

27 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8362 -gerrit commit 49898c236a85f955a16f6963ea08c0b1d4dde962 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 22 09:22:55 2015 +0200 AMD K8 fam10: Eliminate local variables busn and max_bus Change-Id: I297de09dcf93511acece4441593ef958a390fddb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 10 +++------- src/northbridge/amd/amdk8/northbridge.c | 4 +--- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 3aa99c4..9fcd720 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -180,11 +180,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool unsigned int next_unitid; u32 ht_c_index; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain - u32 max_bus; u32 min_bus; -#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 - u32 busn = max&0xff; -#endif u32 max_devfn; /* Check for connected link. */ @@ -213,7 +209,8 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool // i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0 // >4 will use more segments, We can have 16 segmment and every segment have 256 bus, For that case need the kernel support mmio pci config. else { - min_bus = ((busn>>3) + 1) << 3; // one node can have 8 link and segn is the same + /* One node can have 8 link and segn is the same. */ + min_bus = (((max & 0xff) >> 3) + 1) << 3; } max = min_bus; #else @@ -225,10 +222,9 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool #else min_bus = ++max; #endif - max_bus = 0xfc; link->secondary = min_bus; - link->subordinate = max_bus; + link->subordinate = 0xfc; ht_route_link(link); diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index d279cc2..34b9566 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -125,7 +125,6 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ u32 config_busses; u32 free_reg, config_reg; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain - u32 max_bus; u32 min_bus; u32 max_devfn; @@ -184,10 +183,9 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ #else min_bus = ++max; #endif - max_bus = 0xff; link->secondary = min_bus; - link->subordinate = max_bus; + link->subordinate = 0xff; ht_route_link(link);

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Patch set updated for coreboot: 1444110 AMD K8 fam10: Drop local is_sblink in scan_chains
by Kyösti Mälkki 27 Mar '15

27 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8564 -gerrit commit 1444110ea468efe728acdd23a34c73cd4fb2da20 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 22 08:54:45 2015 +0200 AMD K8 fam10: Drop local is_sblink in scan_chains We can define is_sblink = (max == 0) as sblink is always the very first chain we scan. Change-Id: Ibd6b3ea23954ca919ae148604bca2495e9f8753b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 9 +++------ src/northbridge/amd/amdk8/northbridge.c | 9 +++------ 2 files changed, 6 insertions(+), 12 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 224d451..4b18948 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -160,9 +160,6 @@ static u32 amdfam10_scan_chain(struct bus *link, u32 max) u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_devfn; - u32 nodeid = amdfam10_nodeid(link->dev); - bool is_sblink = (nodeid == 0) && (link->link_num == sysconf.sblk); - /* See if there is an available configuration space mapping * register in function 1. */ @@ -174,11 +171,11 @@ static u32 amdfam10_scan_chain(struct bus *link, u32 max) * so we set the subordinate bus number to 0xff for the moment. */ - if (!is_sblink) + if (max != 0) max++; /* One node can have 8 link and segn is the same. */ - if (CONFIG_HT_CHAIN_DISTRIBUTE && !is_sblink) + if (CONFIG_HT_CHAIN_DISTRIBUTE) max = ALIGN_UP(max, 8); link->secondary = max; @@ -202,7 +199,7 @@ static u32 amdfam10_scan_chain(struct bus *link, u32 max) else max_devfn = (0x1f<<3) | 7; - next_unitid = hypertransport_scan_chain(link, 0, max_devfn, ht_unitid_base, offset_unit_id(is_sblink)); + next_unitid = hypertransport_scan_chain(link, 0, max_devfn, ht_unitid_base, offset_unit_id(link->secondary == 0)); /* Now that nothing is overlapping it is safe to scan the children. */ pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7); diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 2100cba..e179237 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -108,10 +108,7 @@ static u32 amdk8_scan_chain(struct bus *link, u32 max) u32 free_reg, config_reg; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_devfn; - u32 nodeid = amdk8_nodeid(link->dev); - unsigned int sblink = (pci_read_config32(link->dev, 0x64)>>8) & 3; - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); /* See if there is an available configuration space mapping * register in function 1. @@ -145,11 +142,11 @@ static u32 amdk8_scan_chain(struct bus *link, u32 max) * so we set the subordinate bus number to 0xff for the moment. */ - if (!is_sblink) + if (max != 0) max++; /* Second chain will be on 0x40, third 0x80, forth 0xc0. */ - if (CONFIG_HT_CHAIN_DISTRIBUTE && !is_sblink) + if (CONFIG_HT_CHAIN_DISTRIBUTE) max = ALIGN_UP(max, 0x40); link->secondary = max; @@ -179,7 +176,7 @@ static u32 amdk8_scan_chain(struct bus *link, u32 max) else max_devfn = (0x1f<<3) | 7; - next_unitid = hypertransport_scan_chain(link, 0, max_devfn, ht_unitid_base, offset_unit_id(is_sblink)); + next_unitid = hypertransport_scan_chain(link, 0, max_devfn, ht_unitid_base, offset_unit_id(link->secondary == 0)); /* Now that nothing is overlapping it is safe to scan the children. */ pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7);

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coreboot-gerrit March 2015