coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 33dbfd4 arm64 libhelpers: Add helper functions for writing sp_elx
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit 33dbfd434e587b0b38d32d5fd0064db0ca397eac Author: Furquan Shaikh <furquan(a)google.com> Date: Sun Sep 7 18:27:16 2014 -0700 arm64 libhelpers: Add helper functions for writing sp_elx BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully Change-Id: Id9367b1fc836b7b8c8fd15b372673853493f67d4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 561e9c4ec2b0657846d50bbc893ef7541230f932 Original-Change-Id: Ie950e893b01456c23af14304bd4dd8f61af9f244 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216905 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9064 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9064 for details. -gerrit

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Patch merged into coreboot/master: e1b87a1 arm64 libhelpers: Add helper functions with el argument
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit e1b87a103290115831226713b1711dcc956ae43d Author: Furquan Shaikh <furquan(a)google.com> Date: Sun Sep 7 18:23:18 2014 -0700 arm64 libhelpers: Add helper functions with el argument Allow read/write to registers at a given el. Also, make read/write registers at current el call this newly added function. BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully Change-Id: I98f35b8d3eb5e292ac895102ad91b675325c08c7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 11d90df1fd92e03c25bfc463429a5f6a8d9d411d Original-Change-Id: I17de4c4f3bc1ee804422efe5f4703b4dd65b51f2 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216904 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9063 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9063 for details. -gerrit

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Patch merged into coreboot/master: 2157ba7 arm64: Add support for read and write registers at current EL in assembly
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit 2157ba76f2fe238cb6bcc97957ac5481df599415 Author: Furquan Shaikh <furquan(a)google.com> Date: Sun Aug 31 12:21:37 2014 -0700 arm64: Add support for read and write registers at current EL in assembly In order to ease the process of reading and writing any register at current EL, provide read_current and write_current assembly macros. These are included in arch/lib_helpers.h under the __ASSEMBLY__ macro condition. This is done to allow the same header file to be included by .c and .S files. BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully Change-Id: I51749b6e4ae7b1ffbaae28d915cd100a28959f26 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c11c7287f507fa398cbbee75abc2bd11140ef19b Original-Change-Id: I1258850438624abfe3b1ed7240df0db0e7905be6 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216373 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9062 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9062 for details. -gerrit

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Patch merged into coreboot/master: 159aa12 tegra132: update MTS version formatting
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit 159aa125ab86a09e2c31f9f1b09eaa6ec8fd396a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Sep 9 11:58:18 2014 -0500 tegra132: update MTS version formatting Nvidia tracks their MTS versions using decimals. Update the format so there isn't an extra step in communicating versions while debugging things. BUG=chrome-os-partner:31864 BRANCH=None TEST=Booted and confirmed decimal print out. Change-Id: I8d8b8a6e9b80548509dd8a30abb17c9970afdead Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b7deb04a1deed41e1a54713320a29f6731401b35 Original-Change-Id: Ia7d0bc49318a4b4c969ee37e762e084ec65de543 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217260 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9061 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9061 for details. -gerrit

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Patch merged into coreboot/master: d79377e tegra132: remove bring_up_secondary_cpu chip option
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit d79377efcfafa2504098339077ac630e091024d6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Sep 6 01:56:52 2014 -0500 tegra132: remove bring_up_secondary_cpu chip option Now that there is cpu devicetree support retire the bring_up_secondary_cpu option as the devicetree is the way going forward to do other CPU bring up. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and booted with 2nd core. Change-Id: I3e8812cd2183f2126c11c36ff4844c15b3cbfc1b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7eab33b763d33d6be210ddb69e3c67411bad0fd0 Original-Change-Id: Ic213fbf56a1846e73462886f876a0a70e48b3158 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216929 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9060 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9060 for details. -gerrit

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Patch merged into coreboot/master: 99759fd ryu: remove bring_up_secondary_cpu from devicetree
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit 99759fdc865678c3f8b6f1b1c07039537872c08e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Sep 6 01:53:19 2014 -0500 ryu: remove bring_up_secondary_cpu from devicetree Now that arm64 and tegra132 has cpu devicetree support stop using the bring_up_secondary_cpu option. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and brought up 2nd core. Change-Id: I3ffca6c1fa0932d8aafea30a160608b5593ae154 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: c45b22ce9fd0345c3e599fd814993db66e2b96cc Original-Change-Id: I210bea73f8249de15f99d0c062600e789184eefd Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216928 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9059 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9059 for details. -gerrit

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Patch set updated for coreboot: f176e98 northbridge/amd/amdfam10: Collect DIMM information for ramstage use
by Timothy Pearson 27 Mar '15

27 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9137 -gerrit commit f176e98bd4bd134e9525430f5d777f6d266426c2 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 27 22:50:09 2015 -0500 northbridge/amd/amdfam10: Collect DIMM information for ramstage use Allow MCT information structures to be copied to cbmem Retrieve DIMM vendor, model, and serial information Allow maximum installable memory to be set via devicetree Change-Id: I0aecd2fb69ebad0a784c01d40ce211f6975a3ece Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/amdfam10.h | 1 + src/northbridge/amd/amdfam10/amdfam10_util.c | 1 + src/northbridge/amd/amdfam10/chip.h | 29 +++++++++++++++++++++++++ src/northbridge/amd/amdfam10/raminit_amdmct.c | 25 +++++++++++++++++++++ src/northbridge/amd/amdmct/mct/mct_d.c | 28 ++++++++++++++++++++++-- src/northbridge/amd/amdmct/mct/mct_d.h | 31 +++++++++++++++++++++++++++ src/northbridge/amd/amdmct/wrappers/mcti_d.c | 2 +- 7 files changed, 114 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index a77d036..238c45f 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -977,6 +977,7 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #include "raminit.h" +#include "../amdmct/wrappers/mcti.h" #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */ #include "../amdmct/mct_ddr3/mct_d.h" #else diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c index 2726b28..9788e54 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_util.c +++ b/src/northbridge/amd/amdfam10/amdfam10_util.c @@ -21,6 +21,7 @@ #include <console/console.h> #include <arch/cpu.h> +#include "northbridge/amd/amdmct/wrappers/mcti.h" #include <northbridge/amd/amdmct/mct/mct_d.h> #include <northbridge/amd/amdmct/amddefs.h> diff --git a/src/northbridge/amd/amdfam10/chip.h b/src/northbridge/amd/amdfam10/chip.h new file mode 100644 index 0000000..ab853d6 --- /dev/null +++ b/src/northbridge/amd/amdfam10/chip.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_FAM10_CHIP_H_ +#define _AMD_FAM10_CHIP_H_ + +#include <stdint.h> + +struct northbridge_amd_amdfam10_config { + uint64_t maximum_memory_capacity; +}; + +#endif /* _AMD_FAM10_CHIP_H_ */ \ No newline at end of file diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 02dc956..b71733d 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -204,3 +204,28 @@ static void raminit_amdmct(struct sys_info *sysinfo) printk(BIOS_DEBUG, "raminit_amdmct end:\n"); } + +static void amdmct_cbmem_store_info(struct sys_info *sysinfo) +{ + /* Save memory info structures for use in ramstage */ + size_t i; + struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat); + struct DCTStatStruc *pDCTstatA = 0; + + if (pMCTstat && sysinfo->DCTstatA) { + /* Initialize memory */ + struct amdmct_memory_info* mem_info; + mem_info = cbmem_add(CBMEM_ID_AMDMCT_MEMINFO, sizeof(struct amdmct_memory_info)); + memset(mem_info, 0, sizeof(struct amdmct_memory_info)); + + /* Copy data */ + memcpy(&mem_info->mct_stat, &(sysinfo->MCTstat), sizeof(struct MCTStatStruc)); + for (i = 0; i < MAX_NODES_SUPPORTED; i++) { + pDCTstatA = sysinfo->DCTstatA + i; + if (pDCTstatA) + memcpy(&mem_info->dct_stat[i], pDCTstatA, sizeof(struct DCTStatStruc)); + } + mem_info->ecc_enabled = mctGet_NVbits(NV_ECC_CAP); + mem_info->ecc_scrub_rate = mctGet_NVbits(NV_DramBKScrub); + } +} \ No newline at end of file diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index bf832da..64cb1bc 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -2122,7 +2122,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, * DATABload=number of ranks on the "B" bus slots. */ - u16 i, j; + u16 i, j, k; u8 smbaddr, Index; u16 Checksum; u8 SPDCtrl; @@ -2183,10 +2183,34 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat, pDCTstat->DIMMValid |= 1 << i; } } + /* Get module information for SMBIOS */ + if (pDCTstat->DIMMValid & (1 << i)) { + pDCTstat->DimmManufacturerID[i] = 0; + for (k = 0; k < 8; k++) + pDCTstat->DimmManufacturerID[i] |= ((uint64_t)mctRead_SPD(smbaddr, SPD_MANID_START + k)) << (k * 8); + for (k = 0; k < SPD_PARTN_LENGTH; k++) + pDCTstat->DimmPartNumber[i][k] = mctRead_SPD(smbaddr, SPD_PARTN_START + k); + pDCTstat->DimmRevisionNumber[i] = 0; + for (k = 0; k < 2; k++) + pDCTstat->DimmRevisionNumber[i] |= ((uint16_t)mctRead_SPD(smbaddr, SPD_REVNO_START + k)) << (k * 8); + pDCTstat->DimmSerialNumber[i] = 0; + for (k = 0; k < 4; k++) + pDCTstat->DimmSerialNumber[i] |= ((uint32_t)mctRead_SPD(smbaddr, SPD_SERIAL_START + k)) << (k * 8); + pDCTstat->DimmRows[i] = mctRead_SPD(smbaddr, SPD_ROWSZ) & 0xf; + pDCTstat->DimmCols[i] = mctRead_SPD(smbaddr, SPD_COLSZ) & 0xf; + pDCTstat->DimmRanks[i] = (mctRead_SPD(smbaddr, SPD_DMBANKS) & 0x7) + 1; + pDCTstat->DimmBanks[i] = mctRead_SPD(smbaddr, SPD_LBANKS); + pDCTstat->DimmWidth[i] = mctRead_SPD(smbaddr, SPD_DEVWIDTH); + } /* Check module type */ byte = mctRead_SPD(smbaddr, SPD_DIMMTYPE); - if (byte & JED_REGADCMSK) + if (byte & JED_REGADCMSK) { RegDIMMPresent |= 1 << i; + pDCTstat->DimmRegistered[i] = 1; + } + else { + pDCTstat->DimmRegistered[i] = 0; + } /* Check ECC capable */ byte = mctRead_SPD(smbaddr, SPD_EDCTYPE); if (byte & JED_ECC) { diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 0a1f925..a200873 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -231,10 +232,17 @@ #define SPD_TRC 41 #define SPD_TRFC 42 +#define SPD_MANID_START 64 +#define SPD_PARTN_START 73 +#define SPD_PARTN_LENGTH 18 +#define SPD_REVNO_START 91 + #define SPD_MANDATEYR 93 /*Module Manufacturing Year (BCD)*/ #define SPD_MANDATEWK 94 /*Module Manufacturing Week (BCD)*/ +#define SPD_SERIAL_START 95 + /*----------------------------- Jedec DDR II related equates -----------------------------*/ @@ -512,6 +520,18 @@ struct DCTStatStruc { /* A per Node structure*/ u32 dev_map; u32 dev_dct; u32 dev_nbmisc; + + uint8_t DimmRows[8]; + uint8_t DimmCols[8]; + uint8_t DimmRanks[8]; + uint8_t DimmBanks[8]; + uint8_t DimmWidth[8]; + uint8_t DimmRegistered[8]; + + uint64_t DimmManufacturerID[8]; + char DimmPartNumber[8][SPD_PARTN_LENGTH]; + uint16_t DimmRevisionNumber[8]; + uint32_t DimmSerialNumber[8]; }; /*=============================================================================== @@ -666,6 +686,17 @@ struct DCTStatStruc { /* A per Node structure*/ xx0b = disable yy1b = enable with DctSelIntLvAddr set to yyb */ +/*=============================================================================== + CBMEM storage +===============================================================================*/ +struct amdmct_memory_info { + struct MCTStatStruc mct_stat; + struct DCTStatStruc dct_stat[MAX_NODES_SUPPORTED]; + uint16_t ecc_enabled; + uint16_t ecc_scrub_rate; +}; + +#define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E u32 Get_NB32(u32 dev, u32 reg); void Set_NB32(u32 dev, u32 reg, u32 val); diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index b2cfad6..39acccf 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -570,4 +570,4 @@ static u8 mctSetNodeBoundary_D(void) { return 0; } -#endif +#endif \ No newline at end of file

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Patch set updated for coreboot: 1faab25 arch/x86/boot/smbios: Rename fill_dimm_manufacturer and make public
by Timothy Pearson 27 Mar '15

27 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9136 -gerrit commit 1faab25ef4f51ff0b80181775c0bf630dabb60a3 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 27 23:05:36 2015 -0500 arch/x86/boot/smbios: Rename fill_dimm_manufacturer and make public Change-Id: Ib85701965337bb6231d8df59d43789dfe8a036d3 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/arch/x86/boot/smbios.c | 4 ++-- src/include/smbios.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 9931ff3..4b96d61 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -123,7 +123,7 @@ static int smbios_processor_name(char *start) } /* this function will fill the corresponding manufacturer */ -static void fill_dimm_manufacturer(uint16_t mod_id, struct smbios_type17 *t) +void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, struct smbios_type17 *t) { switch (mod_id) { case 0x987f: @@ -191,7 +191,7 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm, break; } - fill_dimm_manufacturer(dimm->mod_id, t); + smbios_fill_dimm_manufacturer_from_id(dimm->mod_id, t); /* put '\0' in the end of data */ length = sizeof(dimm->serial); dimm->serial[length - 1] = '\0'; diff --git a/src/include/smbios.h b/src/include/smbios.h index da38419..7d1c333 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -427,4 +427,6 @@ struct smbios_type127 { u8 eos[2]; } __attribute__((packed)); +void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, struct smbios_type17 *t); + #endif

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Patch set updated for coreboot: 477a97b mainboard/asus/kfsn4-dre: Set maximum installable memory
by Timothy Pearson 27 Mar '15

27 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9139 -gerrit commit 477a97b345903a1a8f8b22e05fc01fe283986b2f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 27 22:48:51 2015 -0500 mainboard/asus/kfsn4-dre: Set maximum installable memory Change-Id: I480d6bfe29c77119892fcb1fbb9779fd7e3529c3 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kfsn4-dre/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/asus/kfsn4-dre/devicetree.cb b/src/mainboard/asus/kfsn4-dre/devicetree.cb index 928790b..50e2862 100644 --- a/src/mainboard/asus/kfsn4-dre/devicetree.cb +++ b/src/mainboard/asus/kfsn4-dre/devicetree.cb @@ -7,6 +7,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device domain 0 on # PCI domain subsystemid 0x1043 0x8162 inherit chip northbridge/amd/amdfam10 # Northbridge / RAM controller + register "maximum_memory_capacity" = "0x1000000000" # 64GB device pci 18.0 on end # Link 0 == LDT 0 device pci 18.0 on # Link 1 == LDT 1 [SB on link 1] chip southbridge/nvidia/ck804 # Southbridge

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Patch set updated for coreboot: 7f6832e mainboard/asus/kfsn4-dre: Copy DIMM information to cbmem after romstage
by Timothy Pearson 27 Mar '15

27 Mar '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9138 -gerrit commit 7f6832e0b122f8e3bd7b1d8c8050e485dbfdf73b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Mar 27 22:49:18 2015 -0500 mainboard/asus/kfsn4-dre: Copy DIMM information to cbmem after romstage Change-Id: I07376e276e3e9e3247d2576a09e58780d32a3a76 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kfsn4-dre/romstage.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index af6858f..f7db5fe 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -353,6 +353,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cbmem_initialize_empty(); post_code(0x41); + printk(BIOS_DEBUG, "amdmct_cbmem_store_info()\n"); + amdmct_cbmem_store_info(sysinfo); + printk(BIOS_DEBUG, "disable_spd()\n"); ck804_control(ctrl_conf_disable_spd, ARRAY_SIZE(ctrl_conf_disable_spd), CK804_DEVN_BASE);

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coreboot-gerrit March 2015