coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 5add435 arm64: add spin table support
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit 5add43574dc10b9df3b8d050ce9ef14540e339a8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 17 11:43:20 2014 -0500 arm64: add spin table support There was a hacky and one-off spin table support in tegra132. Make this support generic for all arm64 chips. BUG=chrome-os-partner:32082 BRANCH=None TEST=Ran with and without secure monitor booting smp into the kernel. Change-Id: I3425ab0c30983d4c74d0aa465dda38bb2c91c83b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 024dc3f3e5262433a56ed14934db837b5feb1748 Original-Change-Id: If12083a9afc3b2be663d36cfeed10f9b74bae3c8 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218654 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9084 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9084 for details. -gerrit

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Patch merged into coreboot/master: 74ff69f arm64: add cpu_is_bsp() concept
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit 74ff69feefaf3a34ad458ee641c68e1b62edd8f5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 17 11:51:41 2014 -0500 arm64: add cpu_is_bsp() concept It's helpful to know if the current running CPU is the BSP. Therefore, provide that semantic. BUG=chrome-os-partner:32082 BRANCH=None TEST=Built and booted to kernel. Change-Id: I18cb8ab5149c3337e22b1f6046b1af266be7e47c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b390dc70b658c207cd3b64408713ec4cddab3172 Original-Change-Id: I3d5518d1f6d6a78b14f25bb7ef79727605064561 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218653 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9083 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9083 for details. -gerrit

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Patch merged into coreboot/master: cf5b627 arm64: provide run on all cpu but self semantics
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit cf5b627725bbbe9da5156f334ca00859a6ebde94 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Sep 17 12:00:57 2014 -0500 arm64: provide run on all cpu but self semantics In order to provide richer semantics for running code on all CPUs add an all-but-self construct. BUG=chrome-os-partner:32082 BRANCH=None TEST=Built and booted to kernel. Change-Id: If8dd28ff7f34d93592ab2025a65a2fd665e4e608 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9a4622f63a065f620f0c92ef92eeb2aa5c2b441d Original-Change-Id: Id18dc0423bcb0016ed36ace659b3f858e824c46c Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218652 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9082 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9082 for details. -gerrit

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Patch merged into coreboot/master: ae879bb tegra132: Add secmon support
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit ae879bbecb81812fe65388d1b17447b6a9a982f0 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Aug 26 15:43:16 2014 -0700 tegra132: Add secmon support BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully and secmon loads and jumps to payload successfully. Change-Id: I929cf2c938fb5d8c20e13fbd1fdbd349378914ff Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 2e5d6adc63c4d820417985e34f1f04810b38422b Original-Change-Id: I442546178ad945e7639a99dd2943d13a69b06d09 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214372 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9081 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9081 for details. -gerrit

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Patch merged into coreboot/master: abde3b5 arm64: Add support for secure monitor
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit abde3b56cebc611391a3e3ec63172acefea4daae Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Aug 26 15:39:51 2014 -0700 arm64: Add support for secure monitor Secure monitor runs at EL3 and is responsible for jumping to the payload at specified EL and also to manage features like PSCI. Adding basic implementation of secure monitor as a rmodule. Currently, it just jumps to the the payload at current EL. Support for switching el and PSCI will be added as separate patches. CQ-DEPEND=CL:218300 BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles succesfully and secure monitor loads and runs payload on ryu Change-Id: If0f22299a9bad4e93311154e5546f5bae3f3395c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5e40a21115aeac1cc3c73922bdc3e42d4cdb7d34 Original-Change-Id: I86d5e93583afac141ff61475bd05c8c82d17d926 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214371 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9080 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9080 for details. -gerrit

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Patch merged into coreboot/master: ab020f3 arm64: Adapt stage_entry to make it usable by secmon
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit ab020f304efdac61d38876a95005d8478659faae Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Sep 10 12:19:38 2014 -0700 arm64: Adapt stage_entry to make it usable by secmon stage_entry is the best place to enter for secmon, since it sets up all the stacks right. The only need we need to take care is losing out on the parameter passed to secmon. This patch adds an entry point for secmon rmodule and moves the argument from x0 to x25, which is restored just before the jump to c_entry BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully Change-Id: I9638e9716b3bd5bff272e88fe9d965528d71e394 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ffedb03208bafab6d5886db0259ec205dd20588f Original-Change-Id: I74a7a609fbc08692d68708abe132cd219c89b456 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217570 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9079 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9079 for details. -gerrit

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Patch merged into coreboot/master: f228e8d arm64: initialize SCR_EL3 on all CPUs
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit f228e8d435f2f8c4a7ab954b9d9c2136f74fe560 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Sep 15 14:19:21 2014 -0500 arm64: initialize SCR_EL3 on all CPUs Provide SCR_EL3 initialization on all CPUs. This settings were chosen in such a way that nothing would need to be done if EL3 is abandoned after transitioning to EL2 or EL1. If persistent EL3 program is used those SCR policies can be updated within that program. BUG=chrome-os-partner:31634 BRANCH=None TEST=Built and booted through kernel. Printed out SCR setting for each CPU. Change-Id: Ib44acd8ae40dbca590740340632f5b72998e9dd8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f77b903afbafad7d439ec50fc48f1eaa37827d90 Original-Change-Id: Id659f0a98360fe8bbc80e5a623eba1526e81b400 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218300 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9078 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/9078 for details. -gerrit

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Patch merged into coreboot/master: 5985936 tegra132: use generic GIC driver
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit 5985936411eef8da3ecbdfc2051b64c0d5553dc2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 11 21:54:58 2014 -0500 tegra132: use generic GIC driver As the arm64 boot flow handles initializing the GIC by way of the driver provide the SoC support for that driver and use it. BUG=chrome-os-partner:31945 BRANCH=None TEST=Built and booted kernel on ryu. Change-Id: I6ba20339be8fc823e241b4299ad6c3deb82799fa Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 582cd9cef58e27aef2ce9c9b4fba4a78365bec6e Original-Change-Id: I34efaf28369377f353b4c51d20d19c9433befda4 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217514 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9077 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/9077 for details. -gerrit

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Patch merged into coreboot/master: b9b8ebc arm64: initialize GIC for each CPU
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit b9b8ebca62a661e1ea43574a063f6e3c335f2c06 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 11 21:57:41 2014 -0500 arm64: initialize GIC for each CPU For every CPU that comes online initialize the GIC for that CPU. This allows the per-cpu register state to be initialized for every CPU that comes online. BUG=chrome-os-partner:31945 BRANCH=None TEST=Built and booted to kernel on ryu. Change-Id: I467ca38d51ac67ffc19b1b4fc6fafa9394a876c9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b2faf33fad80fd7ecb884d3ad40917f5a629a5b2 Original-Change-Id: I58d0ffcfe65cffc6a4dd2678c041219e1e698aaf Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217513 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9076 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/9076 for details. -gerrit

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Patch merged into coreboot/master: 27ce094 drivers: add GIC support
by gerrit＠coreboot.org 28 Mar '15

28 Mar '15

the following patch was just integrated into master: commit 27ce094ddfb9bb68741e2d00191a1d825c552f7d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 11 16:07:02 2014 -0500 drivers: add GIC support The GIC is ARM's "Generic Interrupt Controller". This change essentially implements the rudimentary support for a GICv2 implementation that routes all interrupts to Group1. This should also work for GICv1 with security extensions. BUG=chrome-os-partner:31945 BRANCH=None TEST=Built and booted kernel using the code. Change-Id: I9c9202c1309ca9e711e00d742085a6728552c54b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d1cd9b6b76035af107b7dc876f90777698162d34 Original-Change-Id: I4c5b84bfe888ac33fa01c8d64a3dffe1b5ddc823 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217512 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/9075 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/9075 for details. -gerrit

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coreboot-gerrit March 2015