coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: df324f5 tegra132: add preboot MTS to bct generation
by gerrit＠coreboot.org 07 Mar '15

07 Mar '15

the following patch was just integrated into master: commit df324f5a1064da4f9649e8530aba371394c20eb1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jun 20 14:58:05 2014 -0500 tegra132: add preboot MTS to bct generation The preboot MTS microcode needs to be supplied within the bct so the BootROM can load it. The size of the bootblock space in SPI needed to be extended to accomodate the extra length. BUG=chrome-os-partner:29059 BUG=chrome-os-partner:29060 BRANCH=None TEST=Built rush with updated cbootimage with t132 support. Original-Change-Id: Iafc1837cd81cc1165a9be5da6ec7425cec2e2ffc Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204940 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 22e054496465c74fc12afd865d14b87c5858d889) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I5e46c408a7215ecc789b0a0f35070ef9036a7d11 Reviewed-on: http://review.coreboot.org/8466 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/8466 for details. -gerrit

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Patch merged into coreboot/master: 6f713d2 3rdparty: Update submodule to get Tegra 132 binaries
by gerrit＠coreboot.org 07 Mar '15

07 Mar '15

the following patch was just integrated into master: commit 6f713d2c5b67afe133b5d5bf05e074837a01f393 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri Mar 6 15:23:49 2015 -0700 3rdparty: Update submodule to get Tegra 132 binaries Change-Id: Ib5c967708e1f10e78a752ba28c02271f007fd137 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/8613 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/8613 for details. -gerrit

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Patch set updated for coreboot: af7692c genbuild_h.sh: set TZ + LANG variable for predictable `date` and `git` output
by Alexander Couzens 07 Mar '15

07 Mar '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8618 -gerrit commit af7692c9b0c05ec27eb14487382adf14e4f949c9 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sat Mar 7 01:39:55 2015 +0100 genbuild_h.sh: set TZ + LANG variable for predictable `date` and `git` output Change-Id: I10fb0f797b79a2bdbc41c31fe846cc04e26260b3 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- util/genbuild_h/genbuild_h.sh | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh index d814ce5..ffc696e 100755 --- a/util/genbuild_h/genbuild_h.sh +++ b/util/genbuild_h/genbuild_h.sh @@ -29,7 +29,7 @@ printf "#define COREBOOT_VERSION %s\n" "\"$KERNELVERSION\"" #See if the build is running in a git repo and the git command is available if [ -d "${top}/.git" ] && [ -f "$(command -v git)" ]; then printf "/* %s UTC */\n" "$(LANG= TZ=UTC git log --date=local --pretty=format:%cd -1)" - printf "#define COREBOOT_VERSION_TIMESTAMP %s\n" "$(LANG= git log --pretty=format:%ct -1)" + printf "#define COREBOOT_VERSION_TIMESTAMP %s\n" "$(git log --pretty=format:%ct -1)" printf "#define COREBOOT_ORIGIN_GIT_REVISION \"%s\"\n" "$(LANG= git log remotes/origin/master -1 --format=format:%h)" else printf "/* `LANG= TZ=UTC date` */\n" @@ -38,12 +38,12 @@ else fi printf "#define COREBOOT_EXTRA_VERSION \"%s\"\n" "$COREBOOT_EXTRA_VERSION" -printf "#define COREBOOT_BUILD \"%s\"\n" "$(date-d @$DATE)" -printf "#define COREBOOT_BUILD_YEAR_BCD 0x%s\n" "$(date -d @$DATE +%y)" -printf "#define COREBOOT_BUILD_MONTH_BCD 0x%s\n" "$(date -d @$DATE +%m)" -printf "#define COREBOOT_BUILD_DAY_BCD 0x%s\n" "$(date -d @$DATE +%d)" -printf "#define COREBOOT_BUILD_WEEKDAY_BCD 0x%s\n" "$(date -d @$DATE +%w)" -printf "#define COREBOOT_DMI_DATE \"%s\"\n" "$(date -d @$DATE +%m/%d/%Y)" +printf "#define COREBOOT_BUILD \"%s\"\n" "$(LANG= TZ=UTC date -d @$DATE)" +printf "#define COREBOOT_BUILD_YEAR_BCD 0x%s\n" "$(TZ=UTC date -d @$DATE +%y)" +printf "#define COREBOOT_BUILD_MONTH_BCD 0x%s\n" "$(TZ=UTC date -d @$DATE +%m)" +printf "#define COREBOOT_BUILD_DAY_BCD 0x%s\n" "$(TZ=UTC date -d @$DATE +%d)" +printf "#define COREBOOT_BUILD_WEEKDAY_BCD 0x%s\n" "$(TZ=UTC date -d @$DATE +%w)" +printf "#define COREBOOT_DMI_DATE \"%s\"\n" "$(TZ=UTC date -d @$DATE +%m/%d/%Y)" printf "\n" -printf "#define COREBOOT_COMPILE_TIME \"%s\"\n" "$(date -d @$DATE +%T)" +printf "#define COREBOOT_COMPILE_TIME \"%s\"\n" "$(TZ=UTC date -d @$DATE +%T)" printf "#endif\n"

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Patch set updated for coreboot: de56bcd build.h: remove variable for the builduser, -hostname and -domain
by Alexander Couzens 07 Mar '15

07 Mar '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8616 -gerrit commit de56bcd631b78f46cc37be973e95837848032452 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sat Mar 7 00:49:21 2015 +0100 build.h: remove variable for the builduser, -hostname and -domain They don't contain any useful information and also block us from having reproducible builds. Change-Id: Ib03887f6a548230de9f75fb308c73a800e180c48 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/include/version.h | 3 --- src/lib/coreboot_table.c | 3 --- src/lib/version.c | 10 ---------- util/genbuild_h/genbuild_h.sh | 40 ---------------------------------------- 4 files changed, 56 deletions(-) diff --git a/src/include/version.h b/src/include/version.h index 2a70842..f24b893 100644 --- a/src/include/version.h +++ b/src/include/version.h @@ -13,9 +13,6 @@ extern const unsigned int coreboot_version_timestamp; /* When coreboot was compiled */ extern const char coreboot_compile_time[]; -extern const char coreboot_compile_by[]; -extern const char coreboot_compile_host[]; -extern const char coreboot_compile_domain[]; extern const char coreboot_dmi_date[]; struct bcd_date { diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 12090dc..abcb0ed 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -281,9 +281,6 @@ static void lb_strings(struct lb_header *header) { LB_TAG_EXTRA_VERSION, coreboot_extra_version, }, { LB_TAG_BUILD, coreboot_build, }, { LB_TAG_COMPILE_TIME, coreboot_compile_time, }, - { LB_TAG_COMPILE_BY, coreboot_compile_by, }, - { LB_TAG_COMPILE_HOST, coreboot_compile_host, }, - { LB_TAG_COMPILE_DOMAIN, coreboot_compile_domain, }, }; unsigned int i; for(i = 0; i < ARRAY_SIZE(strings); i++) { diff --git a/src/lib/version.c b/src/lib/version.c index 19c14c6..b707e8c 100644 --- a/src/lib/version.c +++ b/src/lib/version.c @@ -18,12 +18,6 @@ #ifndef COREBOOT_COMPILE_TIME #error COREBOOT_COMPILE_TIME not defined #endif -#ifndef COREBOOT_COMPILE_BY -#error COREBOOT_COMPILE_BY not defined -#endif -#ifndef COREBOOT_COMPILE_HOST -#error COREBOOT_COMPILE_HOST not defined -#endif #ifndef COREBOOT_EXTRA_VERSION #define COREBOOT_EXTRA_VERSION "" @@ -38,10 +32,6 @@ const char coreboot_build[] = COREBOOT_BUILD; const unsigned int coreboot_version_timestamp = COREBOOT_VERSION_TIMESTAMP; const char coreboot_compile_time[] = COREBOOT_COMPILE_TIME; -const char coreboot_compile_by[] = COREBOOT_COMPILE_BY; -const char coreboot_compile_host[] = COREBOOT_COMPILE_HOST; -const char coreboot_compile_domain[] = COREBOOT_COMPILE_DOMAIN; - const char coreboot_dmi_date[] = COREBOOT_DMI_DATE; const struct bcd_date coreboot_build_date = { diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh index e79e41b..d500d25 100755 --- a/util/genbuild_h/genbuild_h.sh +++ b/util/genbuild_h/genbuild_h.sh @@ -18,41 +18,6 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -#get the domain name without hanging the build for an extended period if -#the build system doesn't return a domain name as can happen with the -#dnsdomainname or domainname commands by themselves. -get_domainname() { - MAX_DELAY=1 #maximum time to wait in seconds - TIMEOUT_HOSTNAME_TEXT=unknown.domain #text to return if domain name is not found - TEMPFILE_NAME=coreboot_hostname.txt #temp file to put the domain name into - - # Find the domain name - if [ "$(uname -s)" = "Linux" ] - then - dnsdomainname 2>/dev/null > "$TEMPFILE_NAME" & - else - domainname 2>/dev/null >"$TEMPFILE_NAME" & - fi - - # Get ready to kill the process if it's taking too long - PID=$! - sleep "$MAX_DELAY" && kill "$PID" 2>/dev/null & - wait "$PID" 2>/dev/null - - # See what was found, print our timeout text if the process was killed - # or the domain name if we found one. - HN=$(cat "$TEMPFILE_NAME") - if [ "$HN" = "" ] - then - printf "%s" "$TIMEOUT_HOSTNAME_TEXT" - else - printf "%s" "$HN" - fi - - # Clean up and exit. - rm -f "$TEMPFILE_NAME" -} - #Print out the information that goes into build.h printf "/* build system definitions (autogenerated) */\n" printf "#ifndef __BUILD_H\n" @@ -79,9 +44,4 @@ printf "#define COREBOOT_BUILD_WEEKDAY_BCD 0x%s\n" "$(date +%w)" printf "#define COREBOOT_DMI_DATE \"%s\"\n" "$(date +%m/%d/%Y)" printf "\n" printf "#define COREBOOT_COMPILE_TIME \"%s\"\n" "$(date +%T)" -printf "#define COREBOOT_COMPILE_BY \"%s\"\n" "$(whoami)" -printf "#define COREBOOT_COMPILE_HOST \"%s\"\n" "$(hostname -s 2>/dev/null)" -printf "#define COREBOOT_COMPILE_DOMAIN \"" -get_domainname -printf "\"\n" printf "#endif\n"

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Patch set updated for coreboot: 4adf157 ACPI: Get S3 resume state from romstage_handoff
by Kyösti Mälkki 07 Mar '15

07 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8188 -gerrit commit 4adf1577bc6b255abe27f5d14360d102aa55c3ac Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 8 20:03:18 2015 +0200 ACPI: Get S3 resume state from romstage_handoff There is nothing platform specific in retrieving S3 resume state from romstage_handoff structure. Boards without EARLY_CBMEM_INIT update acpi_slp_type from ACPI power-management block or scratchpad registers. Change-Id: Ifc3755f891a0810473b3216c1fec8e45908fc1ab Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/acpi.c | 20 +++++++++++++++++-- src/northbridge/intel/haswell/northbridge.c | 22 -------------------- src/soc/intel/baytrail/ramstage.c | 26 ++++++------------------ src/soc/intel/baytrail/southcluster.c | 3 +-- src/soc/intel/baytrail/xhci.c | 4 ++-- src/soc/intel/broadwell/lpc.c | 4 ++-- src/soc/intel/broadwell/me.c | 4 +--- src/soc/intel/broadwell/ramstage.c | 31 +++++++++-------------------- src/soc/intel/broadwell/refcode.c | 11 +--------- src/soc/intel/broadwell/systemagent.c | 23 --------------------- src/soc/intel/fsp_baytrail/ramstage.c | 24 +++++----------------- src/soc/intel/fsp_baytrail/southcluster.c | 1 - 12 files changed, 45 insertions(+), 128 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 621df2f..fb902db 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -36,6 +36,7 @@ #if CONFIG_COLLECT_TIMESTAMPS #include <timestamp.h> #endif +#include <romstage_handoff.h> /* FIXME: Kconfig doesn't support overridable defaults :-( */ #ifndef CONFIG_HPET_MIN_TICKS @@ -857,10 +858,25 @@ void acpi_resume(void *wake_vec) /* This is filled with acpi_is_wakeup() call early in ramstage. */ int acpi_slp_type = -1; -int __attribute__((weak)) acpi_get_sleep_type(void) +#if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) +int acpi_get_sleep_type(void) { - return 0; + struct romstage_handoff *handoff; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff == NULL) { + printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); + return 0; + } else if (handoff->s3_resume) { + printk(BIOS_DEBUG, "S3 Resume.\n"); + return 3; + } else { + printk(BIOS_DEBUG, "Normal boot.\n"); + return 0; + } } +#endif static void acpi_handoff_wakeup(void) { diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 4909824..7eb9f08 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -35,7 +35,6 @@ #include <cpu/x86/smm.h> #include <boot/tables.h> #include <cbmem.h> -#include <romstage_handoff.h> #include "chip.h" #include "haswell.h" @@ -433,26 +432,6 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) -{ -#if CONFIG_HAVE_ACPI_RESUME - struct romstage_handoff *handoff; - - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff == NULL) { - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - } else if (handoff->s3_resume) { - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - } else { - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - } -#endif -} - static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, }; @@ -462,7 +441,6 @@ static struct device_operations mc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .acpi_fill_ssdt_generator = generate_cpu_entries, .scan_bus = 0, .ops_pci = &intel_pci_ops, diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 9622930..9e429ab 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -27,8 +27,8 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <romstage_handoff.h> #include <stdlib.h> +#include <string.h> #include <baytrail/gpio.h> #include <baytrail/lpc.h> @@ -130,13 +130,6 @@ static void fill_in_pattrs(void) attrs->bclk_khz = bus_freq_khz(); } -static inline void set_acpi_sleep_type(int val) -{ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = val; -#endif -} - /* Save bit index for first enabled event in PM1_STS for \_SB._SWS */ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) { @@ -166,22 +159,15 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) static void s3_resume_prepare(void) { global_nvs_t *gnvs; - struct romstage_handoff *romstage_handoff; gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - - romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { - if (gnvs != NULL) { - memset(gnvs, 0, sizeof(global_nvs_t)); - } - set_acpi_sleep_type(0); + if (gnvs == NULL) return; - } - - set_acpi_sleep_type(3); - s3_save_acpi_wake_source(gnvs); + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); + else + s3_save_acpi_wake_source(gnvs); } void baytrail_init_pre_device(struct soc_intel_baytrail_config *config) diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index d0569b4..c392447 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -29,7 +29,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <pc80/mc146818rtc.h> -#include <romstage_handoff.h> #include <drivers/uart/uart8250reg.h> #include <baytrail/iomap.h> @@ -215,7 +214,7 @@ static void sc_init(device_t dev) read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); } - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) com1_configure_resume(dev); } diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 8d076c2..19339e4 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -184,7 +184,7 @@ static void xhci_route_all(device_t dev) /* Route ports to XHCI controller */ reg_script_run_on_dev(dev, xhci_route_all_script); - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) return; /* Reset enabled USB3 ports */ @@ -222,7 +222,7 @@ static void xhci_init(device_t dev) }; /* Initialize XHCI controller for boot or resume path */ - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) reg_script_run_on_dev(dev, xhci_init_resume_script); else reg_script_run_on_dev(dev, xhci_init_boot_script); diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 53cc4b8..b8eff27 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -394,7 +394,7 @@ static void pch_cg_init(device_t dev) static void pch_set_acpi_mode(void) { #if CONFIG_HAVE_SMI_HANDLER - if (acpi_slp_type != 3) { + if (!acpi_is_wakeup_s3()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); @@ -551,7 +551,7 @@ static void pch_lpc_read_resources(device_t dev) /* Allocate ACPI NVS in CBMEM */ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - if (acpi_slp_type != 3 && gnvs) + if (!acpi_is_wakeup_s3() && gnvs) memset(gnvs, 0, sizeof(global_nvs_t)); } diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 9ec1d44..2a0ce66 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -830,13 +830,11 @@ static void intel_me_init(device_t dev) static void intel_me_enable(device_t dev) { -#if CONFIG_HAVE_ACPI_RESUME /* Avoid talking to the device in S3 path */ - if (acpi_slp_type == 3) { + if (acpi_is_wakeup_s3()) { dev->enabled = 0; pch_disable_devfn(dev); } -#endif } static struct device_operations device_ops = { diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index 0563064..2097f2f 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -21,8 +21,8 @@ #include <cbmem.h> #include <console/console.h> #include <device/device.h> -#include <romstage_handoff.h> #include <stdlib.h> +#include <string.h> #include <broadwell/nvs.h> #include <broadwell/pm.h> #include <broadwell/ramstage.h> @@ -54,31 +54,18 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) gnvs->pm1i); } -static inline void set_acpi_sleep_type(int val) -{ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = val; -#endif -} - static void s3_resume_prepare(void) { - global_nvs_t *gnvs; - struct romstage_handoff *romstage_handoff; + global_nvs_t *gnvs; - gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - - romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { - if (gnvs != NULL) { - memset(gnvs, 0, sizeof(global_nvs_t)); - } - set_acpi_sleep_type(0); - return; - } + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + if (gnvs == NULL) + return; - set_acpi_sleep_type(3); - s3_save_acpi_wake_source(gnvs); + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); + else + s3_save_acpi_wake_source(gnvs); } void broadwell_init_pre_device(void *chip_info) diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index a745101..d66d036 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -30,15 +30,6 @@ #include <broadwell/pei_wrapper.h> #include <broadwell/ramstage.h> -static inline int is_s3_resume(void) -{ -#if CONFIG_HAVE_ACPI_RESUME - return acpi_slp_type == 3; -#else - return 0; -#endif -} - static inline struct ramstage_cache *next_cache(struct ramstage_cache *c) { return (struct ramstage_cache *)&c->program[c->size]; @@ -136,7 +127,7 @@ static pei_wrapper_entry_t load_reference_code(void) }; int ret; - if (is_s3_resume()) { + if (acpi_is_wakeup_s3()) { return load_refcode_from_cache(); } diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 74c43f2..ac021fb 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -29,7 +29,6 @@ #include <stdlib.h> #include <string.h> #include <cbmem.h> -#include <romstage_handoff.h> #include <vendorcode/google/chromeos/chromeos.h> #include <broadwell/cpu.h> #include <broadwell/iomap.h> @@ -412,27 +411,6 @@ static void systemagent_init(struct device *dev) set_power_limits(28); } -static void systemagent_enable(device_t dev) -{ -#if CONFIG_HAVE_ACPI_RESUME - struct romstage_handoff *handoff; - - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff == NULL) { - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - } else if (handoff->s3_resume) { - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - } else { - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - } -#endif -} - - unsigned long acpi_fill_slit(unsigned long current) { // Not implemented @@ -451,7 +429,6 @@ static struct device_operations systemagent_ops = { .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .init = &systemagent_init, - .enable = &systemagent_enable, .ops_pci = &broadwell_pci_ops, }; diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index 814b16e..ad1db33 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -19,6 +19,7 @@ #include <arch/cpu.h> #include <arch/acpi.h> +#include <cbmem.h> #include <console/console.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cr.h> @@ -26,8 +27,8 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <romstage_handoff.h> #include <stdlib.h> +#include <string.h> #include <baytrail/gpio.h> #include <baytrail/lpc.h> @@ -125,31 +126,16 @@ static void fill_in_pattrs(void) attrs->bclk_khz = bus_freq_khz(); } - -static inline void set_acpi_sleep_type(int val) -{ -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = val; -#endif -} - static void s3_resume_prepare(void) { global_nvs_t *gnvs; - struct romstage_handoff *romstage_handoff; gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - - romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { - if (gnvs != NULL) { - memset(gnvs, 0, sizeof(global_nvs_t)); - } - set_acpi_sleep_type(0); + if (gnvs == NULL) return; - } - set_acpi_sleep_type(3); + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); } void baytrail_init_pre_device(void) diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index ec2f94f..d515286 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -33,7 +33,6 @@ #include <pc80/i8254.h> #include <pc80/i8259.h> #include <pc80/isa-dma.h> -#include <romstage_handoff.h> #include <baytrail/baytrail.h> #include <baytrail/iomap.h>

1 0

Patch set updated for coreboot: 340f7db coreboot: common stage cache
by Aaron Durbin 07 Mar '15

07 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8625 -gerrit commit 340f7dbf7419dea2f2e15c03752c31b8d00b05dd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 6 23:17:33 2015 -0600 coreboot: common stage cache Many chipsets were using a stage cache for reference code or when using a relocatable ramstage. Provide a common API for the chipsets to use while reducing code duplication. Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/romstage.c | 12 +-- src/include/cbfs.h | 35 +++----- src/include/cbmem.h | 2 + src/include/ramstage_cache.h | 53 ------------ src/include/romstage_handoff.h | 4 - src/include/stage_cache.h | 48 +++++++++++ src/lib/Makefile.inc | 3 + src/lib/dynamic_cbmem.c | 50 +++++++++++ src/lib/ext_stage_cache.c | 110 ++++++++++++++++++++++++ src/lib/loaders/load_and_run_ramstage.c | 23 ++---- src/lib/ramstage_cache.c | 124 +++------------------------- src/soc/intel/baytrail/refcode.c | 59 ++----------- src/soc/intel/baytrail/romstage/raminit.c | 17 ++-- src/soc/intel/baytrail/romstage/romstage.c | 6 +- src/soc/intel/baytrail/stage_cache.c | 6 +- src/soc/intel/broadwell/refcode.c | 59 ++----------- src/soc/intel/broadwell/romstage/romstage.c | 5 +- src/soc/intel/broadwell/stage_cache.c | 6 +- 18 files changed, 287 insertions(+), 335 deletions(-) diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 50150cf..d000272 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <string.h> +#include <cbfs.h> #include <cbmem.h> #include <console/console.h> #include <arch/cpu.h> @@ -33,9 +34,9 @@ #include <device/pci_def.h> #include <cpu/x86/lapic.h> #include <cbfs.h> -#include <ramstage_cache.h> #include <romstage_handoff.h> #include <reset.h> +#include <stage_cache.h> #include <vendorcode/google/chromeos/chromeos.h> #if CONFIG_EC_GOOGLE_CHROMEEC #include <ec/google/chromeec/ec.h> @@ -307,18 +308,17 @@ void romstage_after_car(void) } -#if CONFIG_RELOCATABLE_RAMSTAGE -#include <ramstage_cache.h> +#if IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) -struct ramstage_cache *ramstage_cache_location(long *size) +void stage_cache_external_region(void **base, size_t *size) { /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. * The top of ram is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; - return (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); + *base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); } -void ramstage_cache_invalid(struct ramstage_cache *cache) +void ramstage_cache_invalid(void) { #if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE reset_system(); diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 5297230..8e74d58 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Jordan Crouse <jordan(a)cosmicpenguin.net> - * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2013-2015 Google, Inc. * * This file is dual-licensed. You can choose between: * - The GNU GPL, version 2, as published by the Free Software Foundation @@ -88,30 +88,17 @@ struct cbmem_entry; * relocated ramstage is saved using the cbmem infrastructure. These * functions are only valid during romstage. */ -/* The implementer of cache_loaded_ramstage() may use the romstage_handoff - * structure to store information, but note that the handoff variable can be - * NULL. The ramstage cbmem_entry represents the region occupied by the loaded - * ramstage. */ -void cache_loaded_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage, void *entry_point); -/* Return NULL on error or entry point on success. The ramstage cbmem_entry is - * the region where to load the cached contents to. */ -void * load_cached_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage); +/* Cache the loaded ramstage provided the cbmem_entry for ramstage location + * and the provided entry point. */ +void cache_loaded_ramstage(const struct cbmem_entry *ramstage, void *entry); +/* Return NULL on error or entry point on success. */ +void *load_cached_ramstage(void); +/* Chipset/Board function called when cache is invalid on resume. */ +void ramstage_cache_invalid(void); #else /* CONFIG_RELOCATABLE_RAMSTAGE */ - -static inline void cache_loaded_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage, void *entry_point) -{ -} - -static inline void * -load_cached_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage) -{ - return NULL; -} - +static inline void cache_loaded_ramstage(const struct cbmem_entry *ramstage, + void *entry_point) { } +static inline void *load_cached_ramstage(void) { return NULL; } #endif /* CONFIG_RELOCATABLE_RAMSTAGE */ #endif /* defined(__PRE_RAM__) */ diff --git a/src/include/cbmem.h b/src/include/cbmem.h index a8c96ee..f904683 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -75,6 +75,8 @@ #define CBMEM_ID_NONE 0x00000000 #define CBMEM_ID_AGESA_RUNTIME 0x41474553 #define CBMEM_ID_HOB_POINTER 0x484f4221 +#define CBMEM_ID_STAGEx_META 0x57a9e000 +#define CBMEM_ID_STAGEx_CACHE 0x57a9e100 #ifndef __ASSEMBLER__ #include <stddef.h> diff --git a/src/include/ramstage_cache.h b/src/include/ramstage_cache.h deleted file mode 100644 index 8d9b095..0000000 --- a/src/include/ramstage_cache.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _RAMSTAGE_CACHE_ -#define _RAMSTAGE_CACHE_ - -#include <stddef.h> -#include <stdint.h> - -/* This structure is saved along with the relocated ramstage program when - * CONFIG_RELOCATED_RAMSTAGE is employed. For x86, it can used to protect - * the integrity of the ramstage program on S3 resume by saving a copy of - * the relocated ramstage in SMM space with the assumption that the SMM region - * cannot be altered from the OS. The magic value just serves as a quick sanity - * check. */ - -#define RAMSTAGE_CACHE_MAGIC 0xf3c3a02a - -struct ramstage_cache { - uint32_t magic; - uint32_t entry_point; - uint32_t load_address; - uint32_t size; - char program[0]; -} __attribute__((packed)); - -/* Chipset/Board function for obtaining cache location and size. */ -struct ramstage_cache *ramstage_cache_location(long *size); -/* Chipset/Board function called when cache is invalid on resume. */ -void ramstage_cache_invalid(struct ramstage_cache *cache); - -static inline int ramstage_cache_is_valid(const struct ramstage_cache *c) -{ - return (c != NULL && c->magic == RAMSTAGE_CACHE_MAGIC); -} - -#endif /* _RAMSTAGE_CACHE_ */ diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index 307babd..679633d 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -34,10 +34,6 @@ struct romstage_handoff { * will be re-loaded from cbfs (which can be slower since it lives * in flash). */ uint32_t s3_resume; - /* The ramstage_entry_point is cached in the stag loading path. This - * cached value can only be utilized when the chipset code properly - * fills in the s3_resume field above. */ - uint32_t ramstage_entry_point; }; #if defined(__PRE_RAM__) diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h new file mode 100644 index 0000000..ac40f91 --- /dev/null +++ b/src/include/stage_cache.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _STAGE_CACHE_H_ +#define _STAGE_CACHE_H_ + +#include <stddef.h> +#include <stdint.h> + +enum { + STAGE_RAMSTAGE, + STAGE_REFCODE, +}; + +/* Create an empty stage cache. */ +void stage_cache_create_empty(void); +/* Recover existing stage cache. */ +void stage_cache_recover(void); +/* Cache the loaded stage provided according to the parameters. */ +void stage_cache_add(int stage_id, void *base, size_t size, void *entry); +/* Load the cached stage at given location returning the stage entry point. */ +void *stage_cache_load_stage(int stage_id); +/* Fill in parameters for the external stage cache, if utilized. */ +void stage_cache_external_region(void **base, size_t *size); + +/* Metadata associated with each stage. */ +struct stage_cache { + uint64_t load_addr; + uint64_t entry_addr; +}; + +#endif /* _STAGE_CACHE_H_ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 0aa08e6..514e5cd 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -96,6 +96,9 @@ ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += ramstage_cache.c +ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += ext_stage_cache.c +romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += ext_stage_cache.c + smm-y += cbfs.c cbfs_core.c memcmp.c smm-$(CONFIG_COMPILER_GCC) += gcc.c diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index fa73527..8f7a9cd 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <cbmem.h> #include <imd.h> +#include <stage_cache.h> #include <string.h> #include <stdlib.h> #include <arch/early_variables.h> @@ -255,3 +256,52 @@ void cbmem_list(void) imd_print_entries(cbmem_get_imd(), lookup, ARRAY_SIZE(lookup)); } #endif /* __PRE_RAM__ */ + +/* Provide empty implementations by default. */ +void __attribute__((weak)) stage_cache_create_empty(void) {} +void __attribute__((weak)) stage_cache_recover(void) {} + +#if !IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) +/* Stage cache uses cbmem. */ +void stage_cache_add(int stage_id, void *base, size_t size, void *entry) +{ + struct stage_cache *meta; + void *c; + + meta = cbmem_add(CBMEM_ID_STAGEx_META + stage_id, sizeof(*meta)); + if (meta == NULL) + return; + meta->load_addr = (uintptr_t)base; + meta->entry_addr = (uintptr_t)entry; + + c = cbmem_add(CBMEM_ID_STAGEx_CACHE + stage_id, size); + if (c == NULL) + return; + + memcpy(c, base, size); +} + +void *stage_cache_load_stage(int stage_id) +{ + struct stage_cache *meta; + const struct cbmem_entry *e; + void *c; + size_t size; + + meta = cbmem_find(CBMEM_ID_STAGEx_META + stage_id); + if (meta == NULL) + return NULL; + + e = cbmem_entry_find(CBMEM_ID_STAGEx_CACHE + stage_id); + + if (e == NULL) + return NULL; + + c = cbmem_entry_start(e); + size = cbmem_entry_size(e); + + memcpy((void *)(uintptr_t)meta->load_addr, c, size); + + return (void *)(uintptr_t)meta->entry_addr; +} +#endif /* !IS_ENABLED(CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) */ diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c new file mode 100644 index 0000000..65b4327 --- /dev/null +++ b/src/lib/ext_stage_cache.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/early_variables.h> +#include <cbmem.h> +#include <imd.h> +#include <stage_cache.h> +#include <string.h> + +static struct imd imd_stage_cache CAR_GLOBAL = { }; + +static inline struct imd *imd_get(void) +{ + return car_get_var_ptr(&imd_stage_cache); +} + +static struct imd *sc_imd_init(void) +{ + struct imd *imd; + void *base; + size_t size; + + imd = imd_get(); + stage_cache_external_region(&base, &size); + imd_handle_init(imd, (void *)(size + (uintptr_t)base)); + + return imd; +} + +void stage_cache_create_empty(void) +{ + imd_create_tiered_empty(sc_imd_init(), 4096, 4096, 1024, 32); +} + +void stage_cache_recover(void) +{ + imd_recover(sc_imd_init()); +} + +void stage_cache_add(int stage_id, void *base, size_t size, void *entry) +{ + struct imd *imd; + const struct imd_entry *e; + struct stage_cache *meta; + void *c; + + imd = imd_get(); + e = imd_entry_add(imd, CBMEM_ID_STAGEx_META + stage_id, sizeof(*meta)); + + if (e == NULL) + return; + + meta = imd_entry_at(imd, e); + + meta->load_addr = (uintptr_t)base; + meta->entry_addr = (uintptr_t)entry; + + e = imd_entry_add(imd, CBMEM_ID_STAGEx_CACHE + stage_id, size); + + if (e == NULL) + return; + + c = imd_entry_at(imd, e); + + memcpy(c, base, size); +} + +void *stage_cache_load_stage(int stage_id) +{ + struct imd *imd; + struct stage_cache *meta; + const struct imd_entry *e; + void *c; + size_t size; + + imd = imd_get(); + e = imd_entry_find(imd, CBMEM_ID_STAGEx_META + stage_id); + if (e == NULL) + return NULL; + + meta = imd_entry_at(imd, e); + + e = imd_entry_find(imd, CBMEM_ID_STAGEx_CACHE + stage_id); + + if (e == NULL) + return NULL; + + c = imd_entry_at(imd, e); + size = imd_entry_size(imd, e); + + memcpy((void *)(uintptr_t)meta->load_addr, c, size); + + return (void *)(uintptr_t)meta->entry_addr; +} diff --git a/src/lib/loaders/load_and_run_ramstage.c b/src/lib/loaders/load_and_run_ramstage.c index 5237e20..0b0b4bf 100644 --- a/src/lib/loaders/load_and_run_ramstage.c +++ b/src/lib/loaders/load_and_run_ramstage.c @@ -39,8 +39,7 @@ static const struct ramstage_loader_ops *loaders[] = { static const char *ramstage_name = CONFIG_CBFS_PREFIX "/ramstage"; static const uint32_t ramstage_id = CBMEM_ID_RAMSTAGE; -static void -load_ramstage(const struct ramstage_loader_ops *ops, struct romstage_handoff *handoff) +static void load_ramstage(const struct ramstage_loader_ops *ops) { const struct cbmem_entry *cbmem_entry; void *entry_point; @@ -51,7 +50,7 @@ load_ramstage(const struct ramstage_loader_ops *ops, struct romstage_handoff *ha if (entry_point == NULL) return; - cache_loaded_ramstage(handoff, cbmem_entry, entry_point); + cache_loaded_ramstage(cbmem_entry, entry_point); timestamp_add_now(TS_END_COPYRAM); @@ -60,18 +59,9 @@ load_ramstage(const struct ramstage_loader_ops *ops, struct romstage_handoff *ha static void run_ramstage_from_resume(struct romstage_handoff *handoff) { - void *entry; - const struct cbmem_entry *cbmem_entry; - if (handoff != NULL && handoff->s3_resume) { - cbmem_entry = cbmem_entry_find(ramstage_id); - - /* No place to load ramstage. */ - if (cbmem_entry == NULL) - return; - /* Load the cached ramstage to runtime location. */ - entry = load_cached_ramstage(handoff, cbmem_entry); + void *entry = load_cached_ramstage(); if (entry != NULL) { printk(BIOS_DEBUG, "Jumping to image.\n"); @@ -82,18 +72,15 @@ static void run_ramstage_from_resume(struct romstage_handoff *handoff) void run_ramstage(void) { - struct romstage_handoff *handoff; const struct ramstage_loader_ops *ops; int i; - handoff = romstage_handoff_find_or_add(); - - run_ramstage_from_resume(handoff); + run_ramstage_from_resume(romstage_handoff_find_or_add()); for (i = 0; i < ARRAY_SIZE(loaders); i++) { ops = loaders[i]; printk(BIOS_DEBUG, "Trying %s ramstage loader.\n", ops->name); - load_ramstage(ops, handoff); + load_ramstage(ops); } die("Ramstage was not loaded!\n"); diff --git a/src/lib/ramstage_cache.c b/src/lib/ramstage_cache.c index 814d807..8cedc70 100644 --- a/src/lib/ramstage_cache.c +++ b/src/lib/ramstage_cache.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. + * Copyright 2013-2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,123 +20,21 @@ #include <stddef.h> #include <string.h> #include <cbfs.h> -#include <console/console.h> -#include <ramstage_cache.h> -#include <romstage_handoff.h> +#include <cbmem.h> +#include <stage_cache.h> -#if CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM - -void cache_loaded_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage, - void *entry_point) -{ - struct ramstage_cache *cache; - uint32_t total_size; - uint32_t ramstage_size; - void *ramstage_base; - long cache_size = 0; - - ramstage_size = cbmem_entry_size(ramstage); - ramstage_base = cbmem_entry_start(ramstage); - - cache = ramstage_cache_location(&cache_size); - - if (cache == NULL) { - printk(BIOS_DEBUG, "No ramstage cache location provided.\n"); - return; - } - - total_size = sizeof(*cache) + ramstage_size; - if (total_size > cache_size) { - printk(BIOS_DEBUG, "cache size too small: 0x%08x > 0x%08lx\n", - total_size, cache_size); - /* Nuke whatever may be there now just in case. */ - cache->magic = ~RAMSTAGE_CACHE_MAGIC; - return; - } - - cache->magic = RAMSTAGE_CACHE_MAGIC; - cache->entry_point = (uint32_t)entry_point; - cache->load_address = (uint32_t)ramstage_base; - cache->size = ramstage_size; - - printk(BIOS_DEBUG, "Saving ramstage to %p.\n", cache); - - /* Copy over the program. */ - memcpy(&cache->program[0], ramstage_base, ramstage_size); - - if (handoff == NULL) - return; - - handoff->ramstage_entry_point = (uint32_t)entry_point; -} - -void *load_cached_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage) -{ - struct ramstage_cache *cache; - long size = 0; - - cache = ramstage_cache_location(&size); - - if (!ramstage_cache_is_valid(cache)) { - printk(BIOS_DEBUG, "Invalid ramstage cache found.\n"); - ramstage_cache_invalid(cache); - return NULL; - } - - printk(BIOS_DEBUG, "Loading ramstage from %p.\n", cache); - - memcpy((void *)cache->load_address, &cache->program[0], cache->size); - - return (void *)cache->entry_point; -} - -#else - -/* Cache relocated ramstage in CBMEM. */ - -void cache_loaded_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage, void *entry_point) +void cache_loaded_ramstage(const struct cbmem_entry *ramstage, void *entry) { - uint32_t ramstage_size; - const struct cbmem_entry *entry; - - if (handoff == NULL) - return; + void *base; + size_t size; - ramstage_size = cbmem_entry_size(ramstage); - /* cbmem_entry_add() does a find() before add(). */ - entry = cbmem_entry_add(CBMEM_ID_RAMSTAGE_CACHE, ramstage_size); + base = cbmem_entry_start(ramstage); + size = cbmem_entry_size(ramstage); - if (entry == NULL) - return; - - /* Keep track of the entry point in the handoff structure. */ - handoff->ramstage_entry_point = (uint32_t)entry_point; - - memcpy(cbmem_entry_start(entry), cbmem_entry_start(ramstage), - ramstage_size); + stage_cache_add(STAGE_RAMSTAGE, base, size, entry); } -void *load_cached_ramstage(struct romstage_handoff *handoff, - const struct cbmem_entry *ramstage) +void *load_cached_ramstage(void) { - const struct cbmem_entry *entry_cache; - - if (handoff == NULL) - return NULL; - - entry_cache = cbmem_entry_find(CBMEM_ID_RAMSTAGE_CACHE); - - if (entry_cache == NULL) - return NULL; - - /* Load the cached ramstage copy into the to-be-run region. */ - memcpy(cbmem_entry_start(ramstage), cbmem_entry_start(entry_cache), - cbmem_entry_size(ramstage)); - - return (void *)handoff->ramstage_entry_point; + return stage_cache_load_stage(STAGE_RAMSTAGE); } - -#endif diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c index e855218..1e066d5 100644 --- a/src/soc/intel/baytrail/refcode.c +++ b/src/soc/intel/baytrail/refcode.c @@ -23,17 +23,12 @@ #include <console/console.h> #include <cpu/x86/tsc.h> #include <rmodule.h> -#include <ramstage_cache.h> +#include <stage_cache.h> #include <vendorcode/google/chromeos/vboot_handoff.h> #include <baytrail/ramstage.h> #include <baytrail/efi_wrapper.h> -static inline struct ramstage_cache *next_cache(struct ramstage_cache *c) -{ - return (struct ramstage_cache *)&c->program[c->size]; -} - static void ABI_X86 send_to_console(unsigned char b) { console_tx_byte(b); @@ -41,60 +36,24 @@ static void ABI_X86 send_to_console(unsigned char b) static efi_wrapper_entry_t load_refcode_from_cache(void) { - struct ramstage_cache *c; - long cache_size; + void *entry; printk(BIOS_DEBUG, "refcode loading from cache.\n"); - c = ramstage_cache_location(&cache_size); - - if (!ramstage_cache_is_valid(c)) { - printk(BIOS_DEBUG, "Invalid ramstage cache descriptor.\n"); - return NULL; - } - - c = next_cache(c); - if (!ramstage_cache_is_valid(c)) { - printk(BIOS_DEBUG, "Invalid refcode cache descriptor.\n"); - return NULL; - } - - printk(BIOS_DEBUG, "Loading cached reference code from 0x%08x(%x)\n", - c->load_address, c->size); - memcpy((void *)c->load_address, &c->program[0], c->size); + entry = stage_cache_load_stage(STAGE_REFCODE); - return (efi_wrapper_entry_t)c->entry_point; + return (efi_wrapper_entry_t)entry; } static void cache_refcode(const struct rmod_stage_load *rsl) { - struct ramstage_cache *c; - long cache_size; - - c = ramstage_cache_location(&cache_size); - - if (!ramstage_cache_is_valid(c)) { - printk(BIOS_DEBUG, "No place to cache reference code.\n"); - return; - } - - /* Determine how much remaining cache available. */ - cache_size -= c->size + sizeof(*c); - - if (cache_size < (sizeof(*c) + cbmem_entry_size(rsl->cbmem_entry))) { - printk(BIOS_DEBUG, "Not enough cache space for ref code.\n"); - return; - } + void *load_addr; + size_t size; - c = next_cache(c); - c->magic = RAMSTAGE_CACHE_MAGIC; - c->entry_point = (uint32_t)rsl->entry; - c->load_address = (uint32_t)cbmem_entry_start(rsl->cbmem_entry); - c->size = cbmem_entry_size(rsl->cbmem_entry); + load_adr = cbmem_entry_start(rsl->cbmem_entry); + size = cbmem_entry_size(rsl->cbmem_entry); - printk(BIOS_DEBUG, "Caching refcode at 0x%p(%x)\n", - &c->program[0], c->size); - memcpy(&c->program[0], (void *)c->load_address, c->size); + stage_cache_add(STAGE_REFCODE, load_addr, size, rsl->entry); } static int load_refcode_from_vboot(struct rmod_stage_load *refcode, diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index a51853a..7488215 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -25,6 +25,7 @@ #include <console/console.h> #include <device/pci_def.h> #include <halt.h> +#include <stage_cache.h> #include <baytrail/gpio.h> #include <soc/intel/common/mrc_cache.h> #include <baytrail/iomap.h> @@ -169,12 +170,16 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) if (prev_sleep_state != 3) { cbmem_initialize_empty(); - } else if (cbmem_initialize()) { - #if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); - /* Failed S3 resume, reset to come up cleanly */ - reset_system(); - #endif + stage_cache_create_empty(); + } else { + stage_cache_recover(); + if (cbmem_initialize()) { + #if CONFIG_HAVE_ACPI_RESUME + printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); + /* Failed S3 resume, reset to come up cleanly */ + reset_system(); + #endif + } } printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 91548e3..e961ccd 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -20,18 +20,18 @@ #include <stddef.h> #include <arch/cpu.h> #include <arch/io.h> -#include <arch/cbfs.h> #include <arch/stages.h> #include <arch/early_variables.h> #include <console/console.h> +#include <cbfs.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> #if CONFIG_EC_GOOGLE_CHROMEEC #include <ec/google/chromeec/ec.h> #endif #include <elog.h> -#include <ramstage_cache.h> #include <romstage_handoff.h> +#include <stage_cache.h> #include <timestamp.h> #include <vendorcode/google/chromeos/chromeos.h> #include <baytrail/gpio.h> @@ -359,7 +359,7 @@ static void *setup_stack_and_mttrs(void) return slot; } -void ramstage_cache_invalid(struct ramstage_cache *cache) +void ramstage_cache_invalid(void) { #if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE /* Perform cold reset on invalid ramstage cache. */ diff --git a/src/soc/intel/baytrail/stage_cache.c b/src/soc/intel/baytrail/stage_cache.c index 3bda56d..c133bc8 100644 --- a/src/soc/intel/baytrail/stage_cache.c +++ b/src/soc/intel/baytrail/stage_cache.c @@ -18,10 +18,10 @@ */ #include <cbmem.h> -#include <ramstage_cache.h> +#include <stage_cache.h> #include <baytrail/smm.h> -struct ramstage_cache *ramstage_cache_location(long *size) +void stage_cache_external_region(void **base, size_t *size) { char *smm_base; /* 1MiB cache size */ @@ -31,5 +31,5 @@ struct ramstage_cache *ramstage_cache_location(long *size) * cbmem_top(). */ smm_base = cbmem_top(); *size = cache_size; - return (void *)&smm_base[smm_region_size() - cache_size]; + *base = &smm_base[smm_region_size() - cache_size]; } diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index a745101..d1bdb18 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -23,7 +23,7 @@ #include <console/console.h> #include <cpu/x86/tsc.h> #include <rmodule.h> -#include <ramstage_cache.h> +#include <stage_cache.h> #include <string.h> #include <vendorcode/google/chromeos/vboot_handoff.h> #include <broadwell/pei_data.h> @@ -39,67 +39,26 @@ static inline int is_s3_resume(void) #endif } -static inline struct ramstage_cache *next_cache(struct ramstage_cache *c) -{ - return (struct ramstage_cache *)&c->program[c->size]; -} - static pei_wrapper_entry_t load_refcode_from_cache(void) { - struct ramstage_cache *c; - long cache_size; + void *entry; printk(BIOS_DEBUG, "refcode loading from cache.\n"); - c = ramstage_cache_location(&cache_size); - - if (!ramstage_cache_is_valid(c)) { - printk(BIOS_DEBUG, "Invalid ramstage cache descriptor.\n"); - return NULL; - } - - c = next_cache(c); - if (!ramstage_cache_is_valid(c)) { - printk(BIOS_DEBUG, "Invalid refcode cache descriptor.\n"); - return NULL; - } - - printk(BIOS_DEBUG, "Loading cached reference code from 0x%08x(%x)\n", - c->load_address, c->size); - memcpy((void *)c->load_address, &c->program[0], c->size); + entry = stage_cache_load_stage(STAGE_REFCODE); - return (pei_wrapper_entry_t)c->entry_point; + return (pei_wrapper_entry_t)entry; } static void cache_refcode(const struct rmod_stage_load *rsl) { - struct ramstage_cache *c; - long cache_size; - - c = ramstage_cache_location(&cache_size); - - if (!ramstage_cache_is_valid(c)) { - printk(BIOS_DEBUG, "No place to cache reference code.\n"); - return; - } - - /* Determine how much remaining cache available. */ - cache_size -= c->size + sizeof(*c); - - if (cache_size < (sizeof(*c) + cbmem_entry_size(rsl->cbmem_entry))) { - printk(BIOS_DEBUG, "Not enough cache space for ref code.\n"); - return; - } + void *load_addr; + size_t size; - c = next_cache(c); - c->magic = RAMSTAGE_CACHE_MAGIC; - c->entry_point = (uint32_t)rsl->entry; - c->load_address = (uint32_t)cbmem_entry_start(rsl->cbmem_entry); - c->size = cbmem_entry_size(rsl->cbmem_entry); + load_adr = cbmem_entry_start(rsl->cbmem_entry); + size = cbmem_entry_size(rsl->cbmem_entry); - printk(BIOS_DEBUG, "Caching refcode at 0x%p(%x)\n", - &c->program[0], c->size); - memcpy(&c->program[0], (void *)c->load_address, c->size); + stage_cache_add(STAGE_REFCODE, load_addr, size, rsl->entry); } static int load_refcode_from_vboot(struct rmod_stage_load *refcode, diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 5ca57d0..202cd42 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -25,11 +25,12 @@ #include <arch/stages.h> #include <arch/early_variables.h> #include <console/console.h> +#include <cbfs.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> #include <elog.h> -#include <ramstage_cache.h> #include <romstage_handoff.h> +#include <stage_cache.h> #include <timestamp.h> #include <broadwell/me.h> #include <broadwell/pei_data.h> @@ -130,7 +131,7 @@ void asmlinkage romstage_after_car(void) while (1); } -void ramstage_cache_invalid(struct ramstage_cache *cache) +void ramstage_cache_invalid(void) { #if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE /* Perform cold reset on invalid ramstage cache. */ diff --git a/src/soc/intel/broadwell/stage_cache.c b/src/soc/intel/broadwell/stage_cache.c index 6c6b6fb..80c7cc5 100644 --- a/src/soc/intel/broadwell/stage_cache.c +++ b/src/soc/intel/broadwell/stage_cache.c @@ -18,11 +18,11 @@ */ #include <cbmem.h> -#include <ramstage_cache.h> +#include <stage_cache.h> #include <broadwell/smm.h> #include <stdint.h> -struct ramstage_cache *ramstage_cache_location(long *size) +void stage_cache_external_region(void **base, size_t *size) { /* The ramstage cache lives in the TSEG region. * The top of ram is defined to be the TSEG base address. */ @@ -30,6 +30,6 @@ struct ramstage_cache *ramstage_cache_location(long *size) offset -= CONFIG_IED_REGION_SIZE; offset -= CONFIG_SMM_RESERVED_SIZE; + *base = (void *)(cbmem_top() + offset); *size = CONFIG_SMM_RESERVED_SIZE; - return (void *)(cbmem_top() + offset); }

1 0

Patch set updated for coreboot: 87cd5d0 coreboot: use tiered imd for cbmem
by Aaron Durbin 07 Mar '15

07 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8624 -gerrit commit 87cd5d0f2d81a3e1b430f8af97163a3efbb1f52c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 6 20:41:20 2015 -0600 coreboot: use tiered imd for cbmem In order to reduce internal fragmentation within cbmem employ a tiered imd. Change-Id: I53040a5a96f41fd99d3de2dcb6f4fb6619346012 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/dynamic_cbmem.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index 529c589..fa73527 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -31,6 +31,9 @@ /* The root region is at least DYN_CBMEM_ALIGN_SIZE . */ #define ROOT_MIN_SIZE DYN_CBMEM_ALIGN_SIZE +/* Small allocation parameters. */ +#define SM_ROOT_SIZE 1024 +#define SM_ALIGN 32 #if !defined(__PRE_RAM__) static void *cached_cbmem_top; @@ -80,7 +83,8 @@ void cbmem_initialize_empty(void) printk(BIOS_DEBUG, "CBMEM: "); - if (imd_create_empty(imd, DYN_CBMEM_ALIGN_SIZE, DYN_CBMEM_ALIGN_SIZE)) + if (imd_create_tiered_empty(imd, DYN_CBMEM_ALIGN_SIZE, + DYN_CBMEM_ALIGN_SIZE, SM_ROOT_SIZE, SM_ALIGN)) return; /* Complete migration to CBMEM. */

1 0

Patch set updated for coreboot: a02a962 coreboot: fix munged license text
by Aaron Durbin 07 Mar '15

07 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8620 -gerrit commit a02a962e06851047877a0a05e1464a35729ce186 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 6 23:26:06 2015 -0600 coreboot: fix munged license text At some point the license text for a file was incorrectly changed. That license was then copied and pasted. I'm sure it was myself. Anyhow, fix the bustedness. Change-Id: I276083d40ea03782e11da7b7518eb708a08ff7cd Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/cbmem_common.c | 2 +- src/lib/dynamic_cbmem.c | 2 +- src/soc/intel/baytrail/baytrail/acpi.h | 2 +- src/soc/intel/baytrail/baytrail/iosf.h | 2 +- src/soc/intel/baytrail/baytrail/msr.h | 2 +- src/soc/intel/baytrail/baytrail/pcie.h | 2 +- src/soc/intel/baytrail/bootblock/bootblock.c | 2 +- src/soc/intel/baytrail/iosf.c | 2 +- src/soc/intel/baytrail/memmap.c | 2 +- src/soc/intel/fsp_baytrail/baytrail/iosf.h | 2 +- src/soc/intel/fsp_baytrail/baytrail/msr.h | 2 +- src/soc/intel/fsp_baytrail/baytrail/pcie.h | 2 +- src/soc/intel/fsp_baytrail/iosf.c | 2 +- src/soc/intel/fsp_baytrail/memmap.c | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index 33f16b5..c3e8383 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -8,7 +8,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index 6ec56c7..daa3717 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -8,7 +8,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * diff --git a/src/soc/intel/baytrail/baytrail/acpi.h b/src/soc/intel/baytrail/baytrail/acpi.h index 279c2cb..a8c32e4 100644 --- a/src/soc/intel/baytrail/baytrail/acpi.h +++ b/src/soc/intel/baytrail/baytrail/acpi.h @@ -8,7 +8,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index 220d022..572630b 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -8,7 +8,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * diff --git a/src/soc/intel/baytrail/baytrail/msr.h b/src/soc/intel/baytrail/baytrail/msr.h index 656d26a..47b9543 100644 --- a/src/soc/intel/baytrail/baytrail/msr.h +++ b/src/soc/intel/baytrail/baytrail/msr.h @@ -8,7 +8,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * diff --git a/src/soc/intel/baytrail/baytrail/pcie.h b/src/soc/intel/baytrail/baytrail/pcie.h index 98effea..f76d3da 100644 --- a/src/soc/intel/baytrail/baytrail/pcie.h +++ b/src/soc/intel/baytrail/baytrail/pcie.h @@ -8,7 +8,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index fa0d9ee..1ff9369 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -8,7 +8,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 0834f4b..c4e7626 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -8,7 +8,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index f2e14b3..2412820 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -8,7 +8,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * diff --git a/src/soc/intel/fsp_baytrail/baytrail/iosf.h b/src/soc/intel/fsp_baytrail/baytrail/iosf.h index 976e4ac..6f0006f 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/iosf.h +++ b/src/soc/intel/fsp_baytrail/baytrail/iosf.h @@ -8,7 +8,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * diff --git a/src/soc/intel/fsp_baytrail/baytrail/msr.h b/src/soc/intel/fsp_baytrail/baytrail/msr.h index 882346c..c11cefa 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/msr.h +++ b/src/soc/intel/fsp_baytrail/baytrail/msr.h @@ -8,7 +8,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * diff --git a/src/soc/intel/fsp_baytrail/baytrail/pcie.h b/src/soc/intel/fsp_baytrail/baytrail/pcie.h index 98effea..f76d3da 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/pcie.h +++ b/src/soc/intel/fsp_baytrail/baytrail/pcie.h @@ -8,7 +8,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * diff --git a/src/soc/intel/fsp_baytrail/iosf.c b/src/soc/intel/fsp_baytrail/iosf.c index eee7c64..daef235 100644 --- a/src/soc/intel/fsp_baytrail/iosf.c +++ b/src/soc/intel/fsp_baytrail/iosf.c @@ -9,7 +9,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c index 8a10ac8..480bbeb 100644 --- a/src/soc/intel/fsp_baytrail/memmap.c +++ b/src/soc/intel/fsp_baytrail/memmap.c @@ -9,7 +9,7 @@ * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. *

1 0

Patch set updated for coreboot: 215fef9 coreboot: add imd library
by Aaron Durbin 07 Mar '15

07 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8621 -gerrit commit 215fef9c1775eafbe1148172ac34743498b8d27a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 5 14:11:27 2015 -0600 coreboot: add imd library The imd (internal memory database) library provides a way to track memory regions by assigning ids to each region. The implementation is a direct descendant of dynamic cbmem. The intent is to replace the existing mechanisms which do similar things: dynamic cbmem, stage cache, etc. Differences between dynamic cbmem and imd: - All structures/objects are relative to one another. There are no absolute pointers serialized to memory. - Allow limiting the size of the idm. i.e. provide a maximum memory usage. - Allow limiting the size of the root structure for tracking entries. Change-Id: Id7438cff80d396a594d6a7330d09b45bb4fedf2e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/imd.h | 126 ++++++++++++++ src/lib/Makefile.inc | 3 + src/lib/imd.c | 457 +++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 586 insertions(+) diff --git a/src/include/imd.h b/src/include/imd.h new file mode 100644 index 0000000..effa2da --- /dev/null +++ b/src/include/imd.h @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _IMD_H_ +#define _IMD_H_ + +#include <stdint.h> +#include <stddef.h> + +/* + * imd is an in-memory database/directory/datastore (whatever d word you + * desire). It grows downwards in memory from provided upper limit and + * root size. Each entry has a size alignment which is also provided by + * the caller. + * + * +----------------------+ <- upper_limit + * | +----| root pointer | + * | | +----------------------+ + * | | | |--------+ + * | +--->| root block |-----+ | + * | +----------------------+-----|--|--- root_size + * | | | | | + * | | | | | + * | | alloc N |<----+ | + * | +----------------------+ | + * | | | | + * | | | | + * \|/ | alloc N + 1 |<-------+ + * v +----------------------+ + * + */ + +/* + * NOTE: This API has the following calling conventions: all functions + * returning int supply 0 on success or < 0 on error. + */ + +struct imd_entry; +struct imd; + +/* + * Initialize handle to use for working with an imd. Upper limit is the + * exclusive address to start allocating down from. This function needs + * to be called at least once before any other imd related functions + * can be used. + */ +void imd_handle_init(struct imd *imd, void *upper_limit); + +/* + * Create an empty imd with a specified root_size and each entry is aligned to + * the provided entry_align. + */ +int imd_create_empty(struct imd *imd, size_t root_size, size_t entry_align); + +/* + * Recover a previously created imd. + */ +int imd_recover(struct imd *imd); + +/* Limit imd to provided max_size. */ +int imd_limit_size(struct imd *imd, size_t max_size); + +/* Lock down imd from further modifications. */ +int imd_lockdown(struct imd *imd); + +/* Fill in base address and size of region used by imd. */ +int imd_region_used(struct imd *imd, void **base, size_t *size); + +/* Add an entry to the imd. If id already exists NULL is returned. */ +const struct imd_entry *imd_entry_add(const struct imd *imd, uint32_t id, + size_t size); + +/* Locate an entry within the imd. NULL is returned when not found. */ +const struct imd_entry *imd_entry_find(const struct imd *imd, uint32_t id); + +/* Find an existing entry or add a new one. */ +const struct imd_entry *imd_entry_find_or_add(const struct imd *imd, + uint32_t id, size_t size); + +/* Returns size of entry or 0 on failure. */ +size_t imd_entry_size(const struct imd *imd, const struct imd_entry *entry); + +/* Returns pointer to region described by entry or NULL on failure. */ +void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry); + +/* Attempt to remove entry from imd. */ +int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry); + +/* Print the entry information provided by lookup with the specified size. */ +struct imd_lookup { + uint32_t id; + const char *name; +}; + +int imd_print_entries(const struct imd *imd, const struct imd_lookup *lookup, + size_t size); + + +/* + * The struct imd is a handle for working with an in-memory directory. + * + * NOTE: Do not directly touch any fields within this structure. An imd pointer + * is meant to be opaque, but the fields are exposed for stack allocation. + */ +struct imd { + uintptr_t limit; + void *r; +}; + +#endif /* _IMD_H_ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 9650fd5..0aa08e6 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -85,6 +85,9 @@ ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c romstage-y += cbmem_common.c dynamic_cbmem.c ramstage-y += cbmem_common.c dynamic_cbmem.c +romstage-y += imd.c +ramstage-y += imd.c + ramstage-y += hexdump.c romstage-y += hexdump.c diff --git a/src/lib/imd.c b/src/lib/imd.c new file mode 100644 index 0000000..6170050 --- /dev/null +++ b/src/lib/imd.c @@ -0,0 +1,457 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <assert.h> +#include <console/console.h> +#include <imd.h> +#include <stdlib.h> +#include <string.h> + +static const uint32_t IMD_ROOT_PTR_MAGIC = 0xc0389481; +static const uint32_t IMD_ENTRY_MAGIC = ~0xc0389481; +static const size_t LIMIT_ALIGN = 4096; + +/* In-memory data structures. */ +struct imd_root_pointer { + uint32_t magic; + /* Relative to upper limit/offset. */ + int32_t root_offset; +} __attribute__((packed)); + +struct imd_entry { + uint32_t magic; + /* start is located relative to imd_root */ + int32_t start_offset; + uint32_t size; + uint32_t id; +} __attribute__((packed)); + +struct imd_root { + uint32_t max_entries; + uint32_t num_entries; + uint32_t flags; + uint32_t entry_align; + /* Used for fixing the size of an imd. Relative to the root. */ + int32_t max_offset; + struct imd_entry entries[0]; +} __attribute__((packed)); + +#define IMD_FLAG_LOCKED 1 + +static inline bool is_power_of_2(size_t v) +{ + return !!((v & -v) == v); +} + +static void *relative_pointer(void *base, ssize_t offset) +{ + intptr_t b = (intptr_t)base; + b += offset; + return (void *)b; +} + +static bool imd_root_pointer_valid(const struct imd_root_pointer *rp) +{ + return !!(rp->magic == IMD_ROOT_PTR_MAGIC); +} + +static struct imd_root *imd_root(const struct imd *imd) +{ + return imd->r; +} + +static struct imd_root_pointer *imd_root_pointer(const struct imd *imd) +{ + struct imd_root_pointer *rp; + + rp = (void *)(imd->limit - sizeof(*rp)); + + return rp; +} + +static void imd_link_root(struct imd_root_pointer *rp, struct imd_root *r) +{ + rp->magic = IMD_ROOT_PTR_MAGIC; + rp->root_offset = (int32_t)((intptr_t)rp - (intptr_t)r); +} + +static void imd_entry_assign(struct imd_entry *e, uint32_t id, + ssize_t offset, size_t size) +{ + e->magic = IMD_ENTRY_MAGIC; + e->start_offset = offset; + e->size = size; + e->id = id; +} + +static bool root_is_locked(const struct imd_root *r) +{ + return !!(r->flags & IMD_FLAG_LOCKED); +} + +static struct imd_entry *root_last_entry(struct imd_root *r) +{ + return &r->entries[r->num_entries - 1]; +} + +/* Initialize imd handle. */ +void imd_handle_init(struct imd *imd, void *upper_limit) +{ + uintptr_t limit = (uintptr_t)upper_limit; + /* Upper limit is aligned down to 4KiB */ + imd->limit = ALIGN_DOWN(limit, LIMIT_ALIGN); + imd->r = NULL; +} + +int imd_create_empty(struct imd *imd, size_t root_size, size_t entry_align) +{ + struct imd_root_pointer *rp; + struct imd_root *r; + struct imd_entry *e; + ssize_t root_offset; + size_t entries_size; + + /* root_size and entry_align should be a power of 2. */ + assert(is_power_of_2(root_size)); + assert(is_power_of_2(entry_align)); + + /* + * root_size needs to be large enough to accomodate root pointer and + * root book keeping structure. The caller needs to ensure there's + * enough room for tracking individual allocations. + */ + if (root_size < (sizeof(*rp) + sizeof(*r))) + return -1; + + /* For simplicity don't allow sizes or alignments to exceed LIMIT_ALIGN. */ + if (root_size > LIMIT_ALIGN || entry_align > LIMIT_ALIGN) + return -1; + + /* Additionally, don't handle an entry alignment > root_size. */ + if (entry_align > root_size) + return -1; + + rp = imd_root_pointer(imd); + + root_offset = root_size; + root_offset = -root_offset; + /* Set root pointer. */ + imd->r = relative_pointer((void *)imd->limit, root_offset); + r = imd_root(imd); + imd_link_root(rp, r); + + memset(r, 0, sizeof(*r)); + r->entry_align = entry_align; + + /* Calculate size left for entries. */ + entries_size = root_size; + entries_size -= sizeof(*rp); + entries_size -= sizeof(*r); + + r->max_entries = entries_size / sizeof(r->entries[0]); + + /* Fill in first entry covering the root region. */ + r->num_entries = 1; + e = &r->entries[0]; + imd_entry_assign(e, 0xff4007ff, 0, root_size); + + printk(BIOS_DEBUG, "IMD: root @ %p %u entries.\n", r, r->max_entries); + + return 0; +} + +int imd_limit_size(struct imd *imd, size_t max_size) +{ + struct imd_root *r; + ssize_t smax_size; + size_t root_size; + + r = imd_root(imd); + if (r == NULL) + return -1; + + root_size = imd->limit - (uintptr_t)r; + + if (max_size < root_size) + return -1; + + /* Take into account the root size. */ + smax_size = max_size - root_size; + smax_size = -smax_size; + + r->max_offset = smax_size; + + return 0; +} + +int imd_recover(struct imd *imd) +{ + struct imd_root_pointer *rp; + struct imd_root *r; + uintptr_t low_limit; + size_t i; + + rp = imd_root_pointer(imd); + + if (!imd_root_pointer_valid(rp)) + return -1; + + r = relative_pointer(rp, rp->root_offset); + + /* Confirm the root and root pointer are just under the limit. */ + if (ALIGN_UP((uintptr_t)&r->entries[r->max_entries], LIMIT_ALIGN) != + imd->limit) + return -1; + + if (r->num_entries > r->max_entries) + return -1; + + /* Entry alignment should be power of 2. */ + if (!is_power_of_2(r->entry_align)) + return -1; + + low_limit = (uintptr_t)relative_pointer(r, r->max_offset); + + /* If no max_offset then lowest limit is 0. */ + if (low_limit == (uintptr_t)r) + low_limit = 0; + + for (i = 0; i < r->num_entries; i++) { + uintptr_t start_addr; + const struct imd_entry *e = &r->entries[i]; + + if (e->magic != IMD_ENTRY_MAGIC) + return -1; + + start_addr = (uintptr_t)relative_pointer(r, e->start_offset); + if (start_addr < low_limit) + return -1; + if (start_addr >= imd->limit || + (start_addr + e->size) >= imd->limit) + return -1; + } + + /* Set root pointer. */ + imd->r = r; + + return 0; +} + +int imd_lockdown(struct imd *imd) +{ + struct imd_root *r; + + r = imd_root(imd); + if (r == NULL) + return -1; + + r->flags |= IMD_FLAG_LOCKED; + + return 0; +} + +int imd_region_used(struct imd *imd, void **base, size_t *size) +{ + struct imd_root *r; + struct imd_entry *e; + void *low_addr; + size_t sz_used; + size_t i; + + r = imd_root(imd); + + if (r == NULL) + return -1; + + /* Use last entry to obtain lowest address. */ + e = root_last_entry(r); + + low_addr = relative_pointer(r, e->start_offset); + + /* + * This could be calculated differently, but it's easy to just + * loop through the entries accumulating their sizes. + */ + for (i = 0, sz_used = 0; i < r->num_entries; i++) + sz_used += r->entries[i].size; + + *base = low_addr; + *size = sz_used; + + return 0; +} + +static struct imd_entry *imd_entry_add_to_root(struct imd_root *r, uint32_t id, + size_t size) +{ + struct imd_entry *entry; + struct imd_entry *last_entry; + ssize_t e_offset; + + if (r->num_entries == r->max_entries) + return NULL; + + last_entry = root_last_entry(r); + + /* See if size overflows imd total size. */ + if (r->max_offset != 0) { + size_t remaining = last_entry->start_offset - r->max_offset; + + if (size > remaining) + return NULL; + } + + /* + * Determine if offset field overflows. All offsets should be lower + * than the previous one. + */ + e_offset = last_entry->start_offset; + e_offset -= (ssize_t)size; + if (e_offset > last_entry->start_offset) + return NULL; + + entry = root_last_entry(r) + 1; + r->num_entries++; + + imd_entry_assign(entry, id, e_offset, size); + + return entry; +} + +const struct imd_entry *imd_entry_add(const struct imd *imd, uint32_t id, + size_t size) +{ + struct imd_root *r; + + r = imd_root(imd); + + if (r == NULL) + return NULL; + + return imd_entry_add_to_root(r, id, size); +} + +const struct imd_entry *imd_entry_find(const struct imd *imd, uint32_t id) +{ + struct imd_root *r; + struct imd_entry *e; + size_t i; + + r = imd_root(imd); + + if (r == NULL) + return NULL; + + e = NULL; + /* Skip first entry covering the root. */ + for (i = 1; i < r->num_entries; i++) { + if (id != r->entries[i].id) + continue; + e = &r->entries[i]; + break; + } + + return e; +} + +const struct imd_entry *imd_entry_find_or_add(const struct imd *imd, + uint32_t id, size_t size) +{ + const struct imd_entry *e; + + e = imd_entry_find(imd, id); + + if (e != NULL) + return e; + + return imd_entry_add(imd, id, size); +} + +size_t imd_entry_size(const struct imd *imd, const struct imd_entry *entry) +{ + return entry->size; +} + +void *imd_entry_at(const struct imd *imd, const struct imd_entry *entry) +{ + struct imd_root *r; + + r = imd_root(imd); + + if (r == NULL) + return NULL; + + return relative_pointer(r, entry->start_offset); +} + +int imd_entry_remove(const struct imd *imd, const struct imd_entry *entry) +{ + struct imd_root *r; + + r = imd_root(imd); + + if (r == NULL) + return -1; + + if (root_is_locked(r)) + return -1; + + if (entry != root_last_entry(r)) + return -1; + + r->num_entries--; + + return 0; +} + +int imd_print_entries(const struct imd *imd, const struct imd_lookup *lookup, + size_t size) +{ + struct imd_root *r; + size_t i; + size_t j; + + r = imd_root(imd); + + if (r == NULL) + return -1; + + for (i = 0; i < r->num_entries; i++) { + const char *name = NULL; + const struct imd_entry *e = &r->entries[i]; + + for (j = 0; j < size; j++) { + if (lookup[j].id != e->id) + continue; + + name = lookup[j].name; + break; + } + + if (name == NULL) + printk(BIOS_DEBUG, "%08x ", e->id); + else + printk(BIOS_DEBUG, "%s", name); + printk(BIOS_DEBUG, "%2zu. ", i); + printk(BIOS_DEBUG, "%p", imd_entry_at(imd, e)); + printk(BIOS_DEBUG, "%08zx\n", imd_entry_size(imd, e)); + } + + return 0; +}

1 0

Patch set updated for coreboot: 4a886da coreboot: use imd library for cbmem
by Aaron Durbin 07 Mar '15

07 Mar '15

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8622 -gerrit commit 4a886dac090a5786dacffc14ae5bf28e5a16d06a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Mar 5 21:18:33 2015 -0600 coreboot: use imd library for cbmem Utilize the newly introduced imd library for the guts of the dynamic cbmem code. Change-Id: I47bb71d95895bd5cbbf27a8c2a47ce94f4f4a702 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/cbmem.h | 12 -- src/lib/cbmem_common.c | 28 ---- src/lib/dynamic_cbmem.c | 330 +++++++----------------------------------------- 3 files changed, 48 insertions(+), 322 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 2f86b85..a8c96ee 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -80,11 +80,6 @@ #include <stddef.h> #include <stdint.h> -struct cbmem_id_to_name { - u32 id; - const char *name; -}; - #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_FREESPACE, "FREE SPACE " }, \ { CBMEM_ID_GDT, "GDT " }, \ @@ -128,13 +123,6 @@ struct cbmem_entry; * dynamic cbmem infrastructure allocates new regions below the last allocated * region. Regions are defined by a cbmem_entry struct that is opaque. Regions * may be removed, but the last one added is the only that can be removed. - * - * Dynamic cbmem has two allocators within it. All allocators use a top down - * allocation scheme. However, there are 2 modes for each allocation depending - * on the requested size. There are large allocations and small allocations. - * An allocation is considered to be small when it is less than or equal to - * DYN_CBMEM_ALIGN_SIZE / 2. The smaller allocations are fit into a larger - * allocation region. */ #define DYN_CBMEM_ALIGN_SIZE (4096) diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index c3e8383..ea2d63d 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -24,34 +24,6 @@ #include <console/cbmem_console.h> #include <timestamp.h> -#ifndef __PRE_RAM__ - -static const struct cbmem_id_to_name cbmem_ids[] = { CBMEM_ID_TO_NAME_TABLE }; - -void cbmem_print_entry(int n, u32 id, u64 base, u64 size) -{ - int i; - const char *name; - - name = NULL; - for (i = 0; i < ARRAY_SIZE(cbmem_ids); i++) { - if (cbmem_ids[i].id == id) { - name = cbmem_ids[i].name; - break; - } - } - - if (name == NULL) - printk(BIOS_DEBUG, "%08x ", id); - else - printk(BIOS_DEBUG, "%s", name); - printk(BIOS_DEBUG, "%2d. ", n); - printk(BIOS_DEBUG, "%08llx ", base); - printk(BIOS_DEBUG, "%08llx\n", size); -} - -#endif /* !__PRE_RAM__ */ - /* FIXME: Replace with CBMEM_INIT_HOOKS API. */ #if !IS_ENABLED(CONFIG_ARCH_X86) void cbmem_run_init_hooks(void) diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index daa3717..529c589 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -21,52 +21,16 @@ #include <bootmem.h> #include <console/console.h> #include <cbmem.h> +#include <imd.h> #include <string.h> #include <stdlib.h> #include <arch/early_variables.h> #if IS_ENABLED(CONFIG_ARCH_X86) && !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) #include <arch/acpi.h> #endif -#ifndef UINT_MAX -#define UINT_MAX 4294967295U -#endif - -/* - * The dynamic cbmem code uses a root region. The root region boundary - * addresses are determined by cbmem_top() and ROOT_MIN_SIZE. Just below - * the address returned by cbmem_top() is a pointer that points to the - * root data structure. The root data structure provides the book keeping - * for each large entry. - */ /* The root region is at least DYN_CBMEM_ALIGN_SIZE . */ #define ROOT_MIN_SIZE DYN_CBMEM_ALIGN_SIZE -#define CBMEM_POINTER_MAGIC 0xc0389479 -#define CBMEM_ENTRY_MAGIC ~(CBMEM_POINTER_MAGIC) - -/* The cbmem_root_pointer structure lives just below address returned - * from cbmem_top(). It points to the root data structure that - * maintains the entries. */ -struct cbmem_root_pointer { - u32 magic; - u32 root; -} __attribute__((packed)); - -struct cbmem_entry { - u32 magic; - u32 start; - u32 size; - u32 id; -} __attribute__((packed)); - -struct cbmem_root { - u32 max_entries; - u32 num_entries; - u32 locked; - u32 size; - struct cbmem_entry entries[0]; -} __attribute__((packed)); - #if !defined(__PRE_RAM__) static void *cached_cbmem_top; @@ -89,98 +53,35 @@ static inline void *cbmem_top_cached(void) #endif } -static inline uintptr_t get_top_aligned(void) -{ - uintptr_t top; +static struct imd imd_cbmem CAR_GLOBAL = { }; - /* Align down what is returned from cbmem_top(). */ - top = (uintptr_t)cbmem_top_cached(); - top &= ~(DYN_CBMEM_ALIGN_SIZE - 1); - - return top; -} - -static inline void *get_root(void) +static inline struct imd *cbmem_get_imd(void) { - uintptr_t pointer_addr; - struct cbmem_root_pointer *pointer; - - pointer_addr = get_top_aligned(); - if (pointer_addr == 0) - return NULL; - - pointer_addr -= sizeof(struct cbmem_root_pointer); - - pointer = (void *)pointer_addr; - if (pointer->magic != CBMEM_POINTER_MAGIC) - return NULL; - - pointer_addr = pointer->root; - return (void *)pointer_addr; + return car_get_var_ptr(&imd_cbmem); } -static inline void cbmem_entry_assign(struct cbmem_entry *entry, - u32 id, u32 start, u32 size) +static inline const struct cbmem_entry *imd_to_cbmem(const struct imd_entry *e) { - entry->magic = CBMEM_ENTRY_MAGIC; - entry->start = start; - entry->size = size; - entry->id = id; + return (const struct cbmem_entry *)e; } -static inline const struct cbmem_entry * -cbmem_entry_append(struct cbmem_root *root, u32 id, u32 start, u32 size) +static inline const struct imd_entry *cbmem_to_imd(const struct cbmem_entry *e) { - struct cbmem_entry *cbmem_entry; - - cbmem_entry = &root->entries[root->num_entries]; - root->num_entries++; - - cbmem_entry_assign(cbmem_entry, id, start, size); - - return cbmem_entry; + return (const struct imd_entry *)e; } void cbmem_initialize_empty(void) { - uintptr_t pointer_addr; - uintptr_t root_addr; - unsigned long max_entries; - struct cbmem_root *root; - struct cbmem_root_pointer *pointer; - - /* Place the root pointer and the root. The number of entries is - * dictated by difference between the root address and the pointer - * where the root address is aligned down to - * DYN_CBMEM_ALIGN_SIZE. The pointer falls just below the - * address returned by get_top_aligned(). */ - pointer_addr = get_top_aligned(); - if (pointer_addr == 0) - return; - - root_addr = pointer_addr - ROOT_MIN_SIZE; - root_addr &= ~(DYN_CBMEM_ALIGN_SIZE - 1); - pointer_addr -= sizeof(struct cbmem_root_pointer); - - max_entries = (pointer_addr - (root_addr + sizeof(*root))) / - sizeof(struct cbmem_entry); + struct imd *imd; - pointer = (void *)pointer_addr; - pointer->magic = CBMEM_POINTER_MAGIC; - pointer->root = root_addr; + imd = cbmem_get_imd(); - root = (void *)root_addr; - root->max_entries = max_entries; - root->num_entries = 0; - root->locked = 0; - root->size = pointer_addr - root_addr + - sizeof(struct cbmem_root_pointer); + imd_handle_init(imd, cbmem_top_cached()); - /* Add an entry covering the root region. */ - cbmem_entry_append(root, CBMEM_ID_ROOT, root_addr, root->size); + printk(BIOS_DEBUG, "CBMEM: "); - printk(BIOS_DEBUG, "CBMEM: root @ %p %d entries.\n", - root, root->max_entries); + if (imd_create_empty(imd, DYN_CBMEM_ALIGN_SIZE, DYN_CBMEM_ALIGN_SIZE)) + return; /* Complete migration to CBMEM. */ cbmem_run_init_hooks(); @@ -193,67 +94,24 @@ static inline int cbmem_fail_recovery(void) return 1; } -static int validate_entries(struct cbmem_root *root) -{ - unsigned int i; - uintptr_t current_end; - - current_end = get_top_aligned(); - - printk(BIOS_DEBUG, "CBMEM: recovering %d/%d entries from root @ %p\n", - root->num_entries, root->max_entries, root); - - /* Check that all regions are properly aligned and are just below - * the previous entry */ - for (i = 0; i < root->num_entries; i++) { - struct cbmem_entry *entry = &root->entries[i]; - - if (entry->magic != CBMEM_ENTRY_MAGIC) - return -1; - - if (entry->start & (DYN_CBMEM_ALIGN_SIZE - 1)) - return -1; - - if (entry->start + entry->size != current_end) - return -1; - - current_end = entry->start; - } - - return 0; -} - int cbmem_initialize(void) { - struct cbmem_root *root; - uintptr_t top_according_to_root; - - root = get_root(); - - /* No recovery possible since root couldn't be recovered. */ - if (root == NULL) - return cbmem_fail_recovery(); + struct imd *imd; - /* Sanity check the root. */ - top_according_to_root = (root->size + (uintptr_t)root); - if (get_top_aligned() != top_according_to_root) - return cbmem_fail_recovery(); + imd = cbmem_get_imd(); - if (root->num_entries > root->max_entries) - return cbmem_fail_recovery(); - - if ((root->max_entries * sizeof(struct cbmem_entry)) > - (root->size - sizeof(struct cbmem_root_pointer) - sizeof(*root))) - return cbmem_fail_recovery(); + imd_handle_init(imd, cbmem_top_cached()); - /* Validate current entries. */ - if (validate_entries(root)) + if (imd_recover(imd) != 0) return cbmem_fail_recovery(); #if defined(__PRE_RAM__) - /* Lock the root in the romstage on a recovery. The assumption is that - * recovery is called during romstage on the S3 resume path. */ - root->locked = 1; + /* + * Lock the imd in romstage on a recovery. The assumption is that + * if the imd area was recovered in romstage then S3 resume path + * is being taken. + */ + imd_lockdown(imd); #endif /* Complete migration to CBMEM. */ @@ -273,65 +131,16 @@ int cbmem_recovery(int is_wakeup) return rv; } -static uintptr_t cbmem_base(void) -{ - struct cbmem_root *root; - uintptr_t low_addr; - - root = get_root(); - - if (root == NULL) - return 0; - - low_addr = (uintptr_t)root; - /* a low address is low. */ - low_addr &= 0xffffffff; - - /* Assume the lowest address is the last one added. */ - if (root->num_entries > 0) { - low_addr = root->entries[root->num_entries - 1].start; - } - - return low_addr; -} - - const struct cbmem_entry *cbmem_entry_add(u32 id, u64 size64) { - struct cbmem_root *root; - const struct cbmem_entry *entry; - uintptr_t base; - u32 size; - u32 aligned_size; - - entry = cbmem_entry_find(id); - - if (entry != NULL) - return entry; - - /* Only handle sizes <= UINT_MAX internally. */ - if (size64 > (u64)UINT_MAX) - return NULL; - - size = size64; - - root = get_root(); - - if (root == NULL) - return NULL; - - /* Nothing can be added once it is locked down. */ - if (root->locked) - return NULL; + struct imd *imd; + const struct imd_entry *e; - if (root->max_entries == root->num_entries) - return NULL; + imd = cbmem_get_imd(); - aligned_size = ALIGN(size, DYN_CBMEM_ALIGN_SIZE); - base = cbmem_base(); - base -= aligned_size; + e = imd_entry_find_or_add(imd, id, size64); - return cbmem_entry_append(root, id, base, aligned_size); + return imd_to_cbmem(e); } void *cbmem_add(u32 id, u64 size) @@ -349,25 +158,14 @@ void *cbmem_add(u32 id, u64 size) /* Retrieve a region provided a given id. */ const struct cbmem_entry *cbmem_entry_find(u32 id) { - struct cbmem_root *root; - const struct cbmem_entry *entry; - unsigned int i; - - root = get_root(); - - if (root == NULL) - return NULL; + struct imd *imd; + const struct imd_entry *e; - entry = NULL; + imd = cbmem_get_imd(); - for (i = 0; i < root->num_entries; i++) { - if (root->entries[i].id == id) { - entry = &root->entries[i]; - break; - } - } + e = imd_entry_find(imd, id); - return entry; + return imd_to_cbmem(e); } void *cbmem_find(u32 id) @@ -386,43 +184,24 @@ void *cbmem_find(u32 id) * cannot be removed unless it was the last one added. */ int cbmem_entry_remove(const struct cbmem_entry *entry) { - unsigned long entry_num; - struct cbmem_root *root; - - root = get_root(); - - if (root == NULL) - return -1; - - if (root->num_entries == 0) - return -1; - - /* Nothing can be removed. */ - if (root->locked) - return -1; + const struct imd_entry *e = cbmem_to_imd(entry); - entry_num = entry - &root->entries[0]; - - /* If the entry is the last one in the root it can be removed. */ - if (entry_num == (root->num_entries - 1)) { - root->num_entries--; - return 0; - } - - return -1; + return imd_entry_remove(cbmem_get_imd(), e); } u64 cbmem_entry_size(const struct cbmem_entry *entry) { - return entry->size; + const struct imd_entry *e = cbmem_to_imd(entry); + + return imd_entry_size(cbmem_get_imd(), e); } void *cbmem_entry_start(const struct cbmem_entry *entry) { - uintptr_t addr = entry->start; - return (void *)addr; -} + const struct imd_entry *e = cbmem_to_imd(entry); + return imd_entry_at(cbmem_get_imd(), e); +} #if !defined(__PRE_RAM__) @@ -458,30 +237,17 @@ BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { void cbmem_add_bootmem(void) { - uintptr_t base; - uintptr_t top; + void *base = NULL; + size_t size = 0; - base = cbmem_base(); - top = get_top_aligned(); - bootmem_add_range(base, top - base, LB_MEM_TABLE); + imd_region_used(cbmem_get_imd(), &base, &size); + bootmem_add_range((uintptr_t)base, size, LB_MEM_TABLE); } void cbmem_list(void) { - unsigned int i; - struct cbmem_root *root; - - root = get_root(); - - if (root == NULL) - return; - - for (i = 0; i < root->num_entries; i++) { - struct cbmem_entry *entry; - - entry = &root->entries[i]; + static const struct imd_lookup lookup[] = { CBMEM_ID_TO_NAME_TABLE }; - cbmem_print_entry(i, entry->id, entry->start, entry->size); - } + imd_print_entries(cbmem_get_imd(), lookup, ARRAY_SIZE(lookup)); } #endif /* __PRE_RAM__ */

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coreboot-gerrit March 2015