coreboot-gerrit March 2015

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Patch merged into coreboot/master: b706288 crossgcc: Unify tool tests, add check for g++ or clang
by gerrit＠coreboot.org 09 Mar '15

09 Mar '15

the following patch was just integrated into master: commit b706288d95824f09de15b7d6343ef169b010ff3e Author: Patrick Georgi <pgeorgi(a)google.com> Date: Tue Feb 24 10:52:14 2015 +0100 crossgcc: Unify tool tests, add check for g++ or clang Change-Id: I406f5cfc61bc87ccc2c0b9283b4fbb8cef8dfc1b Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: http://review.coreboot.org/8522 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8522 for details. -gerrit

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Patch set updated for coreboot: 7650899 AMD fam10: Fix include of conf.c
by Kyösti Mälkki 09 Mar '15

09 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8553 -gerrit commit 76508991b01ea4eccceeabed2dc0d41365ec0d18 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 22 00:12:43 2015 +0200 AMD fam10: Fix include of conf.c Change-Id: I982acb0b36f2cef8281ffbac4511f831f08fc89a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/Makefile.inc | 2 + src/northbridge/amd/amdfam10/conf.c | 244 ---------------------------- src/northbridge/amd/amdfam10/ht_config.c | 248 +++++++++++++++++++++++++++++ src/northbridge/amd/amdfam10/ht_config.h | 62 ++++++++ src/northbridge/amd/amdfam10/northbridge.c | 8 +- 5 files changed, 315 insertions(+), 249 deletions(-) diff --git a/src/northbridge/amd/amdfam10/Makefile.inc b/src/northbridge/amd/amdfam10/Makefile.inc index fdbfa12..65bdc03 100644 --- a/src/northbridge/amd/amdfam10/Makefile.inc +++ b/src/northbridge/amd/amdfam10/Makefile.inc @@ -3,6 +3,8 @@ ramstage-y += misc_control.c romstage-y += amdfam10_util.c ramstage-y += amdfam10_util.c +ramstage-y += ht_config.c + ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += get_pci1234.c diff --git a/src/northbridge/amd/amdfam10/conf.c b/src/northbridge/amd/amdfam10/conf.c deleted file mode 100644 index ba488bf..0000000 --- a/src/northbridge/amd/amdfam10/conf.c +++ /dev/null @@ -1,244 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -typedef struct amdfam10_sysconf_t sys_info_conf_t; - -struct dram_base_mask_t { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 -}; - -static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) -{ - struct dram_base_mask_t d; - device_t dev = __f1_dev[0]; - - u32 temp; - temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] - d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too - temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp<<21; - - temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] - d.mask |= (temp & 1); // enable bit - - d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too - temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] - d.base |= temp<<21; - return d; -} - - -static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, u32 segbit, - u32 nodes) -{ - u32 tempreg; - u32 i; - - busn_min>>=segbit; - busn_max>>=segbit; - - tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24); - for (i=0; i<nodes; i++) { - device_t dev = __f1_dev[i]; - pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg); - } -} - -static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, u32 nodes) -{ - u32 i; - - for (i=0; i<nodes; i++) { - device_t dev = __f1_dev[i]; - pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0); - } -} - -#if CONFIG_PCI_BUS_SEGN_BITS -static u32 check_segn(device_t dev, u32 segbusn, u32 nodes, - sys_info_conf_t *sysinfo) -{ - //check segbusn here, We need every node have the same segn - if ((segbusn & 0xff)>(0xe0-1)) {// use next segn - u32 segn = (segbusn >> 8) & 0x0f; - segn++; - segbusn = segn<<8; - } - if (segbusn>>8) { - u32 val; - val = pci_read_config32(dev, 0x160); - val &= ~(0xf<<25); - val |= (segbusn & 0xf00)<<(25-8); - pci_write_config32(dev, 0x160, val); - } - - return segbusn; -} -#endif - -static u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo) -{ - u32 tempreg; - u32 ht_c_index = 0; - -#if 0 - tempreg = 3 | ((nodeid & 0xf) <<4) | ((nodeid & 0x30)<<(12-4)) | (linkn<<8); - - for (ht_c_index=0;ht_c_index<4; ht_c_index++) { - reg = pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1), 0xe0 + ht_c_index * 4); - if (((reg & 0xffff) == 0x0000)) { /*found free*/ - break; - } - } -#endif - tempreg = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8); - for (ht_c_index=0; ht_c_index<32; ht_c_index++) { - if ((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == tempreg) { - return ht_c_index; - } - } - - for (ht_c_index=0; ht_c_index<32; ht_c_index++) { - if (sysinfo->ht_c_conf_bus[ht_c_index] == 0) { - return ht_c_index; - } - } - - return -1; -} - -static void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, - sys_info_conf_t *sysinfo) -{ - u32 val; - val = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8); - sysinfo->ht_c_conf_bus[ht_c_index] = val | ((busn_min & 0xff) <<12) | (busn_max<<20); // same node need segn are same - -} - -static u32 get_io_addr_index(u32 nodeid, u32 linkn) -{ - u32 index; - - for (index=0; index<256; index++) { - if (sysconf.conf_io_addrx[index+4] == 0) { - sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; - sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); - return index; - } - } - - return 0; -} - -static u32 get_mmio_addr_index(u32 nodeid, u32 linkn) -{ - u32 index; - - for (index=0; index<64; index++) { - if (sysconf.conf_mmio_addrx[index+8] == 0) { - sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; - sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); - return index; - } - } - - return 0; -} - -static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, - u32 io_min, u32 io_max) -{ - u32 val; - - /* io range allocation */ - index = (reg-0xc0)>>3; - - val = (nodeid & 0x3f); // 6 bits used - sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid - val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used - sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit - - if (sysconf.io_addr_num < (index+1)) - sysconf.io_addr_num = index+1; -} - - -static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, - u32 mmio_min, u32 mmio_max) -{ - u32 val; - - /* io range allocation */ - index = (reg-0x80)>>3; - - val = (nodeid & 0x3f) ; // 6 bits used - sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn - val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used - sysconf.conf_mmio_addrx[index] = val | (mmio_min & 0xffffff00); // base : with enable bit - - if ( sysconf.mmio_addr_num<(index+1)) - sysconf.mmio_addr_num = index+1; -} - - -static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, - u32 io_min, u32 io_max) -{ - u32 i; - u32 tempreg; - - /* io range allocation */ - tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit - for (i=0; i<sysconf.nodes; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - - tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? -#if 0 - // FIXME: can we use VGA reg instead? - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { - printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", - __func__, dev_path(dev), link); - tempreg |= PCI_IO_BASE_VGA_EN; - } - if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { - tempreg |= PCI_IO_BASE_NO_ISA; - } -#endif - for (i=0; i<sysconf.nodes; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} - -static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) -{ - u32 i; - u32 tempreg; - - /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i=0; i<nodes; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i=0; i<sysconf.nodes; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c new file mode 100644 index 0000000..cfd8a24 --- /dev/null +++ b/src/northbridge/amd/amdfam10/ht_config.c @@ -0,0 +1,248 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci_ops.h> + +#include <cpu/amd/amdfam10_sysconf.h> +#include "northbridge.h" +#include "amdfam10.h" +#include "ht_config.h" + +struct dram_base_mask_t get_dram_base_mask(u32 nodeid) +{ + struct dram_base_mask_t d; + device_t dev = __f1_dev[0]; + + u32 temp; + temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] + d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too + temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] + d.mask |= temp<<21; + + temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] + d.mask |= (temp & 1); // enable bit + + d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too + temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] + d.base |= temp<<21; + return d; +} + + +void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, + u32 busn_min, u32 busn_max, u32 segbit, + u32 nodes) +{ + u32 tempreg; + u32 i; + + busn_min>>=segbit; + busn_max>>=segbit; + + tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24); + for (i=0; i<nodes; i++) { + device_t dev = __f1_dev[i]; + pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg); + } +} + +void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, + u32 busn_min, u32 busn_max, u32 nodes) +{ + u32 i; + + for (i=0; i<nodes; i++) { + device_t dev = __f1_dev[i]; + pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0); + } +} + +#if CONFIG_PCI_BUS_SEGN_BITS +u32 check_segn(device_t dev, u32 segbusn, u32 nodes, + sys_info_conf_t *sysinfo) +{ + //check segbusn here, We need every node have the same segn + if ((segbusn & 0xff)>(0xe0-1)) {// use next segn + u32 segn = (segbusn >> 8) & 0x0f; + segn++; + segbusn = segn<<8; + } + if (segbusn>>8) { + u32 val; + val = pci_read_config32(dev, 0x160); + val &= ~(0xf<<25); + val |= (segbusn & 0xf00)<<(25-8); + pci_write_config32(dev, 0x160, val); + } + + return segbusn; +} +#endif + +u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo) +{ + u32 tempreg; + u32 ht_c_index = 0; + +#if 0 + tempreg = 3 | ((nodeid & 0xf) <<4) | ((nodeid & 0x30)<<(12-4)) | (linkn<<8); + + for (ht_c_index=0;ht_c_index<4; ht_c_index++) { + reg = pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1), 0xe0 + ht_c_index * 4); + if (((reg & 0xffff) == 0x0000)) { /*found free*/ + break; + } + } +#endif + tempreg = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8); + for (ht_c_index=0; ht_c_index<32; ht_c_index++) { + if ((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == tempreg) { + return ht_c_index; + } + } + + for (ht_c_index=0; ht_c_index<32; ht_c_index++) { + if (sysinfo->ht_c_conf_bus[ht_c_index] == 0) { + return ht_c_index; + } + } + + return -1; +} + +void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index, + u32 busn_min, u32 busn_max, + sys_info_conf_t *sysinfo) +{ + u32 val; + val = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8); + sysinfo->ht_c_conf_bus[ht_c_index] = val | ((busn_min & 0xff) <<12) | (busn_max<<20); // same node need segn are same + +} + +u32 get_io_addr_index(u32 nodeid, u32 linkn) +{ + u32 index; + + for (index=0; index<256; index++) { + if (sysconf.conf_io_addrx[index+4] == 0) { + sysconf.conf_io_addr[index+4] = (nodeid & 0x3f) ; + sysconf.conf_io_addrx[index+4] = 1 | ((linkn & 0x7)<<4); + return index; + } + } + + return 0; +} + +u32 get_mmio_addr_index(u32 nodeid, u32 linkn) +{ + u32 index; + + for (index=0; index<64; index++) { + if (sysconf.conf_mmio_addrx[index+8] == 0) { + sysconf.conf_mmio_addr[index+8] = (nodeid & 0x3f) ; + sysconf.conf_mmio_addrx[index+8] = 1 | ((linkn & 0x7)<<4); + return index; + } + } + + return 0; +} + + +void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, + u32 io_min, u32 io_max) +{ + u32 val; + + /* io range allocation */ + index = (reg-0xc0)>>3; + + val = (nodeid & 0x3f); // 6 bits used + sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid + val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used + sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit + + if (sysconf.io_addr_num < (index+1)) + sysconf.io_addr_num = index+1; +} + + +void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, + u32 mmio_min, u32 mmio_max) +{ + u32 val; + + /* io range allocation */ + index = (reg-0x80)>>3; + + val = (nodeid & 0x3f) ; // 6 bits used + sysconf.conf_mmio_addr[index] = val | (mmio_max & 0xffffff00); //limit : with nodeid and linkn + val = 3 | ((linkn & 0x7)<<4) ; // 8 bits used + sysconf.conf_mmio_addrx[index] = val | (mmio_min & 0xffffff00); // base : with enable bit + + if ( sysconf.mmio_addr_num<(index+1)) + sysconf.mmio_addr_num = index+1; +} + + +void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, + u32 io_min, u32 io_max) +{ + u32 i; + u32 tempreg; + + /* io range allocation */ + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + for (i=0; i<sysconf.nodes; i++) + pci_write_config32(__f1_dev[i], reg+4, tempreg); + + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? +#if 0 + // FIXME: can we use VGA reg instead? + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", + __func__, dev_path(dev), link); + tempreg |= PCI_IO_BASE_VGA_EN; + } + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { + tempreg |= PCI_IO_BASE_NO_ISA; + } +#endif + for (i=0; i<sysconf.nodes; i++) + pci_write_config32(__f1_dev[i], reg, tempreg); +} + +void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) +{ + u32 i; + u32 tempreg; + + /* io range allocation */ + tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + for (i=0; i<nodes; i++) + pci_write_config32(__f1_dev[i], reg+4, tempreg); + tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); + for (i=0; i<sysconf.nodes; i++) + pci_write_config32(__f1_dev[i], reg, tempreg); +} diff --git a/src/northbridge/amd/amdfam10/ht_config.h b/src/northbridge/amd/amdfam10/ht_config.h new file mode 100644 index 0000000..9b82f54 --- /dev/null +++ b/src/northbridge/amd/amdfam10/ht_config.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +typedef struct amdfam10_sysconf_t sys_info_conf_t; + +/* FIXME */ +extern device_t __f1_dev[]; + +struct dram_base_mask_t { + u32 base; //[47:27] at [28:8] + u32 mask; //[47:27] at [28:8] and enable at bit 0 +}; + +struct dram_base_mask_t get_dram_base_mask(u32 nodeid); + +void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, + u32 busn_min, u32 busn_max, u32 segbit, + u32 nodes); +void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, + u32 busn_min, u32 busn_max, u32 nodes); +u32 check_segn(device_t dev, u32 segbusn, u32 nodes, + sys_info_conf_t *sysinfo); + +void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index, + u32 busn_min, u32 busn_max, + sys_info_conf_t *sysinfo); + +u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo); + + +void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, + u32 io_min, u32 io_max); + +void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, + u32 mmio_min, u32 mmio_max); + + +u32 get_io_addr_index(u32 nodeid, u32 linkn); +u32 get_mmio_addr_index(u32 nodeid, u32 linkn); + +void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, + u32 io_min, u32 io_max); + +void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes); + + diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index cbeddf2..503dcf9 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -32,6 +32,7 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam10_sysconf.h> #if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> @@ -39,14 +40,13 @@ #endif #include "northbridge.h" - #include "amdfam10.h" +#include "ht_config.h" #if CONFIG_HW_MEM_HOLE_SIZEK != 0 #include <cpu/amd/model_10xxx_rev.h> #endif -#include <cpu/amd/amdfam10_sysconf.h> #if CONFIG_AMD_SB_CIMX #include <sb_cimx.h> #endif @@ -55,7 +55,7 @@ struct amdfam10_sysconf_t sysconf; #define FX_DEVS NODE_NUMS static device_t __f0_dev[FX_DEVS]; -static device_t __f1_dev[FX_DEVS]; +device_t __f1_dev[FX_DEVS]; static device_t __f2_dev[FX_DEVS]; static device_t __f4_dev[FX_DEVS]; static unsigned fx_devs=0; @@ -127,8 +127,6 @@ static u32 amdfam10_nodeid(device_t dev) #endif } -#include "conf.c" - static void set_vga_enable_reg(u32 nodeid, u32 linkn) { u32 val;

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Patch set updated for coreboot: cf5af3f AMD fam10: Drop PCI_BUS_SEGN_BITS
by Kyösti Mälkki 09 Mar '15

09 Mar '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8554 -gerrit commit cf5af3f1593ad51b528544c21cc1867481415218 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 21 12:42:51 2015 +0200 AMD fam10: Drop PCI_BUS_SEGN_BITS All boards in tree use 0. Looks like this is all work that was never completed and tested. We also have static setting sysconf.segbit=0 which would conflict with PCI_BUS_SEGN_BITS>0. Having PCI_BUS_SEGN_BITS>0 would also require PCI MMCONF support to cover over 255 buses. Change-Id: I060efc44d1560541473b01690c2e8192863c1eb5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/io.h | 2 +- src/device/Kconfig | 4 ---- src/device/device_util.c | 28 ---------------------------- src/device/pci_device.c | 5 ----- src/northbridge/amd/amdfam10/debug.c | 4 ---- src/northbridge/amd/amdfam10/ht_config.c | 21 --------------------- src/northbridge/amd/amdfam10/ht_config.h | 2 -- src/northbridge/amd/amdfam10/northbridge.c | 9 ++------- 8 files changed, 3 insertions(+), 72 deletions(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 9987578..3130f64 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -267,7 +267,7 @@ static inline pci_devfn_t pci_io_locate_device(unsigned pci_id, pci_devfn_t dev) static inline pci_devfn_t pci_locate_device(unsigned pci_id, pci_devfn_t dev) { - for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) { + for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { unsigned int id; id = pci_read_config32(dev, 0); if (id == pci_id) { diff --git a/src/device/Kconfig b/src/device/Kconfig index 42a68d2..7f43888 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -259,10 +259,6 @@ config PCIEXP_CLK_PM help Detect and enable Clock Power Management on PCIe. -config PCI_BUS_SEGN_BITS - int - default 0 - config EARLY_PCI_BRIDGE bool "Early PCI bridge" depends on PCI diff --git a/src/device/device_util.c b/src/device/device_util.c index 62a815f..d970429 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -251,20 +251,11 @@ const char *dev_path(device_t dev) memcpy(buffer, "Root Device", 12); break; case DEVICE_PATH_PCI: -#if CONFIG_PCI_BUS_SEGN_BITS - snprintf(buffer, sizeof (buffer), - "PCI: %04x:%02x:%02x.%01x", - dev->bus->secondary >> 8, - dev->bus->secondary & 0xff, - PCI_SLOT(dev->path.pci.devfn), - PCI_FUNC(dev->path.pci.devfn)); -#else snprintf(buffer, sizeof (buffer), "PCI: %02x:%02x.%01x", dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); -#endif break; case DEVICE_PATH_PNP: snprintf(buffer, sizeof (buffer), "PNP: %04x.%01x", @@ -643,14 +634,8 @@ void report_resource_stored(device_t dev, struct resource *resource, buf[0] = '\0'; if (resource->flags & IORESOURCE_PCI_BRIDGE) { -#if CONFIG_PCI_BUS_SEGN_BITS - snprintf(buf, sizeof (buf), - "bus %04x:%02x ", dev->bus->secondary >> 8, - dev->link_list->secondary & 0xff); -#else snprintf(buf, sizeof (buf), "bus %02x ", dev->link_list->secondary); -#endif } printk(BIOS_DEBUG, "%s %02lx <- [0x%010llx - 0x%010llx] size 0x%08llx " "gran 0x%02x %s%s%s\n", dev_path(dev), resource->index, @@ -855,19 +840,6 @@ void show_one_resource(int debug_level, struct device *dev, end = resource_end(resource); buf[0] = '\0'; -/* - if (resource->flags & IORESOURCE_BRIDGE) { -#if CONFIG_PCI_BUS_SEGN_BITS - snprintf(buf, sizeof (buf), "bus %04x:%02x ", - dev->bus->secondary >> 8, - dev->link[0].secondary & 0xff); -#else - snprintf(buf, sizeof (buf), - "bus %02x ", dev->link[0].secondary); -#endif - } -*/ - do_printk(debug_level, "%s %02lx <- [0x%010llx - 0x%010llx] " "size 0x%08llx gran 0x%02x %s%s%s\n", dev_path(dev), resource->index, base, end, resource->size, resource->gran, diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 127ee32..4651258 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1090,12 +1090,7 @@ unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, struct device *old_devices; struct device *child; -#if CONFIG_PCI_BUS_SEGN_BITS - printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %04x:%02x\n", - bus->secondary >> 8, bus->secondary & 0xff); -#else printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary); -#endif /* Maximum sane devfn is 0xFF. */ if (max_devfn > 0xff) { diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index d1fdaf8..6aed390 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -33,11 +33,7 @@ static inline void print_debug_addr(const char *str, void *val) static void print_debug_pci_dev(u32 dev) { -#if !CONFIG_PCI_BUS_SEGN_BITS printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7); -#else - printk(BIOS_DEBUG, "PCI: %04x:%02x:%02x.%02x", (dev>>28) & 0x0f, (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7); -#endif } static inline void print_pci_devices(void) diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c index cfd8a24..efb3148 100644 --- a/src/northbridge/amd/amdfam10/ht_config.c +++ b/src/northbridge/amd/amdfam10/ht_config.c @@ -76,27 +76,6 @@ void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, } } -#if CONFIG_PCI_BUS_SEGN_BITS -u32 check_segn(device_t dev, u32 segbusn, u32 nodes, - sys_info_conf_t *sysinfo) -{ - //check segbusn here, We need every node have the same segn - if ((segbusn & 0xff)>(0xe0-1)) {// use next segn - u32 segn = (segbusn >> 8) & 0x0f; - segn++; - segbusn = segn<<8; - } - if (segbusn>>8) { - u32 val; - val = pci_read_config32(dev, 0x160); - val &= ~(0xf<<25); - val |= (segbusn & 0xf00)<<(25-8); - pci_write_config32(dev, 0x160, val); - } - - return segbusn; -} -#endif u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo) { diff --git a/src/northbridge/amd/amdfam10/ht_config.h b/src/northbridge/amd/amdfam10/ht_config.h index 9b82f54..54356c1 100644 --- a/src/northbridge/amd/amdfam10/ht_config.h +++ b/src/northbridge/amd/amdfam10/ht_config.h @@ -34,8 +34,6 @@ void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 nodes); void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 busn_min, u32 busn_max, u32 nodes); -u32 check_segn(device_t dev, u32 segbusn, u32 nodes, - sys_info_conf_t *sysinfo); void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index, u32 busn_min, u32 busn_max, diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 503dcf9..5ce7ae6 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -167,7 +167,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool u32 max_bus; u32 min_bus; u32 busses; - u32 segn = max>>8; #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 u32 busn = max&0xff; #endif @@ -211,7 +210,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool else { min_bus = ((busn>>3) + 1) << 3; // one node can have 8 link and segn is the same } - max = min_bus | (segn<<8); + max = min_bus; #else //other ... else { @@ -221,7 +220,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool #else min_bus = ++max; #endif - max_bus = 0xfc | (segn<<8); + max_bus = 0xfc; link->secondary = min_bus; link->subordinate = max_bus; @@ -299,10 +298,6 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max) max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); } -#if CONFIG_PCI_BUS_SEGN_BITS - max = check_segn(dev, max, sysconf.nodes, &sysconf); -#endif - for (link = dev->link_list; link; link = link->next) { bool is_sblink = (nodeid == 0) && (link->link_num == sblink); if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink)

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Patch merged into coreboot/master: bd29530 AMD fam10: Remove __PRE_RAM__ from ramstage-only code
by gerrit＠coreboot.org 09 Mar '15

09 Mar '15

the following patch was just integrated into master: commit bd295300619fb3f6040e00d8100a0b688b9651c1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 21 07:48:35 2015 +0200 AMD fam10: Remove __PRE_RAM__ from ramstage-only code Change-Id: I41aba81def13c99671eb609dd1e76a9a45299622 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8552 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8552 for details. -gerrit

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Patch merged into coreboot/master: 5ef269b AMD fam10: Always have AMDMCT
by gerrit＠coreboot.org 09 Mar '15

09 Mar '15

the following patch was just integrated into master: commit 5ef269b5a36d73570e596d0417d64f3979d9d257 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 22 00:09:14 2015 +0200 AMD fam10: Always have AMDMCT Also drop some more #if UNUSED_CODE. Change-Id: I1bbe96a65c9240636ff7cfaf70c2ecbfb3aee715 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8551 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8551 for details. -gerrit

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Patch merged into coreboot/master: c0ee937 AMD K8: Fix allocation size for HyperTransport links
by gerrit＠coreboot.org 09 Mar '15

09 Mar '15

the following patch was just integrated into master: commit c0ee937e92c901f30d38c10800012781db4a2b83 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 21 23:56:07 2015 +0200 AMD K8: Fix allocation size for HyperTransport links There is no requirement that in dev->link_list the last element would have the highest link->link_num. Also fix off-by-one error when allocating for more links. Change-Id: Id8a7db3ffb4111eb31e70ea14fd522b70368dd8c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8550 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8550 for details. -gerrit

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Patch merged into coreboot/master: 11c79d7 AMD K8: Move the test for connected HyperTransport link
by gerrit＠coreboot.org 09 Mar '15

09 Mar '15

the following patch was just integrated into master: commit 11c79d7fc2c9e04828db8e54c199822e5fa749b8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 4 15:23:03 2015 +0200 AMD K8: Move the test for connected HyperTransport link Change-Id: I7f8cbfcae7ec2a49e91ceda1eecdcf76b2137d8b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8549 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8549 for details. -gerrit

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Patch merged into coreboot/master: e0b6fbd google/samus/acpi/mainboard.asl: Correctly align comment
by gerrit＠coreboot.org 09 Mar '15

09 Mar '15

the following patch was just integrated into master: commit e0b6fbde41ffd92fe2c2ac9f9905b15a1ccc5846 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Jan 19 12:58:25 2015 +0100 google/samus/acpi/mainboard.asl: Correctly align comment Fix up commit 00aedc5e (samus: add acpi resource for supporting RT5677 codec). Change-Id: I98b8c6f1a46f9f3bfd79da92bb070cebe8f20dc0 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/8234 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8234 for details. -gerrit

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Patch merged into coreboot/master: bdaeea5 cpu/Kconfig: Make in-tree microcode generation dependent on BLOBs repository
by gerrit＠coreboot.org 09 Mar '15

09 Mar '15

the following patch was just integrated into master: commit bdaeea5396b2455ac093535450686ac12b9a0cfc Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Mar 7 09:15:02 2015 +0100 cpu/Kconfig: Make in-tree microcode generation dependent on BLOBs repository Since commit ee894357 (cpu/intel (non-FSP): Use microcode from blobs repository), selecting the option to generate the microcode from tree fails without allowing to use the BLOBs/ 3rdparty repository, which is the default setting. Therefore, only show the option, if the user has selected the option to allow the use of the BLOBs repository. Change-Id: Ide20da0f946aae43dc2c8cdce54941c704d3d288 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/8627 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8627 for details. -gerrit

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Patch set updated for coreboot: d360b10 src/arch/arm/Makefile.inc: Remove trailing whitespace
by Stefan Reinauer 09 Mar '15

09 Mar '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8211 -gerrit commit d360b1044d839d120127aac8564fe89850f194cf Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Jan 13 23:29:05 2015 +0100 src/arch/arm/Makefile.inc: Remove trailing whitespace Remove trailing space introduced in commit 320647ab (vboot2: add verstage). Change-Id: I936eb03457ea161716a1a59890bc3c9c33051265 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>

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coreboot-gerrit March 2015