coreboot-gerrit March 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 9604474 broadwell: enable PCIe endpoint CLK power management
by gerrit＠coreboot.org 09 Mar '15

09 Mar '15

the following patch was just integrated into master: commit 9604474d4cdd8577807d86b04892f60598905abf Author: Kane Chen <kane.chen(a)intel.com> Date: Wed Oct 1 13:22:52 2014 +0800 broadwell: enable PCIe endpoint CLK power management BUG=chrome-os-partner:31424 BRANCH=none TEST=build only, due to I don't have broadwell system with wifi to test need somebody help me to verify Change-Id: I52360176e135ea7f01cc67a926be4870265f57d1 Signed-off-by: Kane Chen <kane.chen(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/220743 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/8448 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8448 for details. -gerrit

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Patch merged into coreboot/master: 18cb134 device/pciexp: Add support for PCIe CLK power management
by gerrit＠coreboot.org 09 Mar '15

09 Mar '15

the following patch was just integrated into master: commit 18cb1340f185150b9708257ba8024b6900706083 Author: Kane Chen <kane.chen(a)intel.com> Date: Wed Oct 1 11:13:54 2014 +0800 device/pciexp: Add support for PCIe CLK power management Set PCIe "Enable Clock Power Management", if endpoint supports it. BUG=chrome-os-partner:31424 BRANCH=none TEST=build and boot on rambi, check Enable Clock Power Management in link control register is set properly Change-Id: Ie54110d1ef42184cfcf47c9fe4d735960aebe47f Signed-off-by: Kane Chen <kane.chen(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/220742 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> [Edit commit message.] Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/8447 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8447 for details. -gerrit

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Patch set updated for coreboot: 2a8e571 genbuild_h.sh: derive all timestamp variables from one timestamp
by Stefan Reinauer 09 Mar '15

09 Mar '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8617 -gerrit commit 2a8e571df0c4981d3b60a2a31da55e32bd43d25d Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sat Mar 7 01:34:55 2015 +0100 genbuild_h.sh: derive all timestamp variables from one timestamp If not derived it's possible it defines inconsistent timestamps which differ from each other. Change-Id: I090fdce4c4c1c24135ec72818eecb69e168df565 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- util/genbuild_h/genbuild_h.sh | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh index d500d25..d814ce5 100755 --- a/util/genbuild_h/genbuild_h.sh +++ b/util/genbuild_h/genbuild_h.sh @@ -18,6 +18,8 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +DATE=$(date +%s) + #Print out the information that goes into build.h printf "/* build system definitions (autogenerated) */\n" printf "#ifndef __BUILD_H\n" @@ -31,17 +33,17 @@ if [ -d "${top}/.git" ] && [ -f "$(command -v git)" ]; then printf "#define COREBOOT_ORIGIN_GIT_REVISION \"%s\"\n" "$(LANG= git log remotes/origin/master -1 --format=format:%h)" else printf "/* `LANG= TZ=UTC date` */\n" - printf "#define COREBOOT_VERSION_TIMESTAMP %s\n" "$(LANG= date +%s)" + printf "#define COREBOOT_VERSION_TIMESTAMP %s\n" "$(LANG= date -d @$DATE +%s)" printf "#define COREBOOT_ORIGIN_GIT_REVISION \"Unknown\"\n" fi printf "#define COREBOOT_EXTRA_VERSION \"%s\"\n" "$COREBOOT_EXTRA_VERSION" -printf "#define COREBOOT_BUILD \"%s\"\n" "$(date)" -printf "#define COREBOOT_BUILD_YEAR_BCD 0x%s\n" "$(date +%y)" -printf "#define COREBOOT_BUILD_MONTH_BCD 0x%s\n" "$(date +%m)" -printf "#define COREBOOT_BUILD_DAY_BCD 0x%s\n" "$(date +%d)" -printf "#define COREBOOT_BUILD_WEEKDAY_BCD 0x%s\n" "$(date +%w)" -printf "#define COREBOOT_DMI_DATE \"%s\"\n" "$(date +%m/%d/%Y)" +printf "#define COREBOOT_BUILD \"%s\"\n" "$(date-d @$DATE)" +printf "#define COREBOOT_BUILD_YEAR_BCD 0x%s\n" "$(date -d @$DATE +%y)" +printf "#define COREBOOT_BUILD_MONTH_BCD 0x%s\n" "$(date -d @$DATE +%m)" +printf "#define COREBOOT_BUILD_DAY_BCD 0x%s\n" "$(date -d @$DATE +%d)" +printf "#define COREBOOT_BUILD_WEEKDAY_BCD 0x%s\n" "$(date -d @$DATE +%w)" +printf "#define COREBOOT_DMI_DATE \"%s\"\n" "$(date -d @$DATE +%m/%d/%Y)" printf "\n" -printf "#define COREBOOT_COMPILE_TIME \"%s\"\n" "$(date +%T)" +printf "#define COREBOOT_COMPILE_TIME \"%s\"\n" "$(date -d @$DATE +%T)" printf "#endif\n"

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Patch set updated for coreboot: d4801b8 rambi: Change RAM_ID GPIOs to GPIO_INPUT
by Stefan Reinauer 09 Mar '15

09 Mar '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5053 -gerrit commit d4801b8b322247a1f3a0ff8ee9838587a18e8966 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Thu Jan 16 17:52:21 2014 -0800 rambi: Change RAM_ID GPIOs to GPIO_INPUT RAM_ID GPIOs were previously changed to GPIO_FUNC0 to configure for MMIO access when legacy was the default. Now, MMIO is the default, so these GPIOs can conform to the normal labeling scheme. This change should have no functional impact. BUG=chrome-os-partner:25043 TEST=Manual on Rambi. Verify RAM_ID GPIOs on test unit are read with identical values as before. BRANCH=Rambi. Change-Id: I2f76395064ea6e4170b2eaad6e67bfc1aa22b54e Reviewed-on: https://chromium-review.googlesource.com/182934 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>

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Patch merged into coreboot/master: 2c4aab3 coreboot: fix munged license text
by gerrit＠coreboot.org 09 Mar '15

09 Mar '15

the following patch was just integrated into master: commit 2c4aab3fd6cd7b357b8389c20a95a6ad59cc75a0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 6 23:26:06 2015 -0600 coreboot: fix munged license text At some point the license text for a file was incorrectly changed. That license was then copied and pasted. I'm sure it was myself. Anyhow, fix the bustedness. Change-Id: I276083d40ea03782e11da7b7518eb708a08ff7cd Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/8620 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/8620 for details. -gerrit

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New patch to review for coreboot: 5f18817 mainboard: Define DRIVERS_PS2_KEYBOARD to false where desired
by Patrick Georgi 08 Mar '15

08 Mar '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8632 -gerrit commit 5f1881740309b4ac6a26d0252288e0d0135f03e8 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sun Mar 8 21:29:24 2015 +0100 mainboard: Define DRIVERS_PS2_KEYBOARD to false where desired This is a partial revert of Icc603dfe92360d978221a25ad28517da43942bea, because it actually changed behaviour. Background: mainboard Kconfigs are parsed first, so they actually can set "n" defaults. That language's semantics suck, but unfortunately it won out over CML2. We'll deal somehow. Change-Id: Icb676c7c5df7159bdb92fd6cad5b1e6e8403db17 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/mainboard/amd/persimmon/Kconfig | 4 ++++ src/mainboard/amd/south_station/Kconfig | 4 ++++ src/mainboard/amd/union_station/Kconfig | 4 ++++ src/mainboard/asrock/e350m1/Kconfig | 4 ++++ src/mainboard/gizmosphere/gizmo/Kconfig | 4 ++++ src/mainboard/intel/bakersport_fsp/Kconfig | 4 ++++ src/mainboard/intel/bayleybay_fsp/Kconfig | 4 ++++ src/mainboard/intel/minnowmax/Kconfig | 4 ++++ src/mainboard/intel/mohonpeak/Kconfig | 4 ++++ src/mainboard/lippert/frontrunner-af/Kconfig | 4 ++++ src/mainboard/lippert/toucan-af/Kconfig | 4 ++++ 11 files changed, 44 insertions(+) diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig index 9a3209c..d64c88e 100644 --- a/src/mainboard/amd/persimmon/Kconfig +++ b/src/mainboard/amd/persimmon/Kconfig @@ -78,4 +78,8 @@ config SB800_AHCI_ROM bool default n +config DRIVERS_PS2_KEYBOARD + bool + default n + endif # BOARD_AMD_PERSIMMON diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index 32f4004..7982a06 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -72,5 +72,9 @@ config VGA_BIOS_ID string default "1002,9806" +config DRIVERS_PS2_KEYBOARD + bool + default n + endif # BOARD_AMD_SOUTHSTATION diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index a9c08aa..faaa8e8 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -71,5 +71,9 @@ config VGA_BIOS_ID string default "1002,9802" +config DRIVERS_PS2_KEYBOARD + bool + default n + endif # BOARD_AMD_UNIONSTATION diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index feb7d69..5992035 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -65,5 +65,9 @@ config VGA_BIOS_ID string default "1002,9802" +config DRIVERS_PS2_KEYBOARD + bool + default n + endif # BOARD_ASROCK_E350M1 diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index 873f2ad..d949c59 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -74,4 +74,8 @@ config SB800_AHCI_ROM bool default n +config DRIVERS_PS2_KEYBOARD + bool + default n + endif # BOARD_GIZMOSPHERE_GIZMO diff --git a/src/mainboard/intel/bakersport_fsp/Kconfig b/src/mainboard/intel/bakersport_fsp/Kconfig index 4a4f743..d105ae0 100644 --- a/src/mainboard/intel/bakersport_fsp/Kconfig +++ b/src/mainboard/intel/bakersport_fsp/Kconfig @@ -86,4 +86,8 @@ config VGA_BIOS bool default y if FSP_PACKAGE_DEFAULT +config DRIVERS_PS2_KEYBOARD + bool + default n + endif # BOARD_INTEL_BAKERSPORT_FSP diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index 4a70239..2932a37 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -86,4 +86,8 @@ config VGA_BIOS bool default y if FSP_PACKAGE_DEFAULT +config DRIVERS_PS2_KEYBOARD + bool + default n + endif # BOARD_INTEL_BAYLEYBAY_FSP diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index 77725f8..a4c1483 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -89,4 +89,8 @@ config VGA_BIOS bool default y if FSP_PACKAGE_DEFAULT +config DRIVERS_PS2_KEYBOARD + bool + default n + endif # BOARD_INTEL_MINNOWMAX diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig index f9ad07d..0196ef5 100644 --- a/src/mainboard/intel/mohonpeak/Kconfig +++ b/src/mainboard/intel/mohonpeak/Kconfig @@ -92,4 +92,8 @@ config SEABIOS_MALLOC_UPPERMEMORY segment. This means that USB/SATA devices will not work in SeaBIOS unless we put the SeaBIOS buffer area down in the 0x9000 segment. +config DRIVERS_PS2_KEYBOARD + bool + default n + endif # BOARD_INTEL_MOHONPEAK diff --git a/src/mainboard/lippert/frontrunner-af/Kconfig b/src/mainboard/lippert/frontrunner-af/Kconfig index b6c8ff7..0e1b17b 100644 --- a/src/mainboard/lippert/frontrunner-af/Kconfig +++ b/src/mainboard/lippert/frontrunner-af/Kconfig @@ -80,4 +80,8 @@ config SB800_AHCI_ROM bool default n +config DRIVERS_PS2_KEYBOARD + bool + default n + endif # BOARD_LIPPERT_FRONTRUNNER_AF diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index cf6ac60..72c0390 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -82,4 +82,8 @@ config SB800_AHCI_ROM bool default n +config DRIVERS_PS2_KEYBOARD + bool + default n + endif # BOARD_LIPPERT_TOUCAN_AF

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New patch to review for coreboot: 0a30731 global: Refactor get_option usage
by Varad 08 Mar '15

08 Mar '15

Varad (varadgautam(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8631 -gerrit commit 0a3073134dc86b8dc344c3a94d86e3dedda022e0 Author: Varad Gautam <varadgautam(a)gmail.com> Date: Sun Mar 8 23:10:21 2015 +0530 global: Refactor get_option usage Assign option to its default value to avoid checking what get_option returns. Change-Id: I9159afe149a8eeed0785d1efd6eee8420b88b8f4 Signed-off-by: Varad Gautam <varadgautam(a)gmail.com> --- src/console/init.c | 4 ++-- src/cpu/amd/model_fxx/model_fxx_init.c | 4 ++-- src/mainboard/ibase/mb899/superio_hwm.c | 26 +++++++++++++------------- src/mainboard/kontron/986lcd-m/mainboard.c | 26 +++++++++++++------------- src/northbridge/amd/amdk8/misc_control.c | 4 ++-- src/southbridge/amd/sb600/sata.c | 6 ++---- src/southbridge/intel/i82801dx/lpc.c | 4 ++-- src/southbridge/intel/i82801gx/lpc.c | 4 ++-- src/southbridge/intel/i82801ix/lpc.c | 4 ++-- 9 files changed, 40 insertions(+), 42 deletions(-) diff --git a/src/console/init.c b/src/console/init.c index e638216..1fbe22a 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -37,8 +37,8 @@ int console_log_level(int msg_level) void console_init(void) { #if !defined(__PRE_RAM__) - if(get_option(&console_loglevel, "debug_level") != CB_SUCCESS) - console_loglevel=CONFIG_DEFAULT_CONSOLE_LOGLEVEL; + console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; + get_option(&console_loglevel, "debug_level"); #endif #if CONFIG_EARLY_PCI_BRIDGE && !defined(__SMM__) diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 341bb62..d33f4bb 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -251,8 +251,8 @@ static void init_ecc_memory(unsigned node_id) /* See if we scrubbing should be enabled */ enable_scrubbing = 1; - if (get_option(&enable_scrubbing, "hw_scrubber") != CB_SUCCESS) - enable_scrubbing = CONFIG_HW_SCRUBBER; + enable_scrubbing = CONFIG_HW_SCRUBBER; + get_option(&enable_scrubbing, "hw_scrubber"); /* Enable cache scrubbing at the lowest possible rate */ if (enable_scrubbing) { diff --git a/src/mainboard/ibase/mb899/superio_hwm.c b/src/mainboard/ibase/mb899/superio_hwm.c index 7864264..4c7d123 100644 --- a/src/mainboard/ibase/mb899/superio_hwm.c +++ b/src/mainboard/ibase/mb899/superio_hwm.c @@ -80,19 +80,19 @@ void hwm_setup(void) int cpufan_speed = 0, sysfan_speed = 0; int cpufan_temperature = 0, sysfan_temperature = 0; - if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS) - cpufan_control = FAN_CRUISE_CONTROL_DISABLED; - if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS) - cpufan_speed = FAN_SPEED_5625; - //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS) - // cpufan_temperature = FAN_TEMPERATURE_30DEGC; - - if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS) - sysfan_control = FAN_CRUISE_CONTROL_DISABLED; - if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS) - sysfan_speed = FAN_SPEED_5625; - //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) - // sysfan_temperature = FAN_TEMPERATURE_30DEGC; + cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + get_option(&cpufan_control, "cpufan_cruise_control"); + cpufan_speed = FAN_SPEED_5625; + get_option(&cpufan_speed, "cpufan_speed"); + //cpufan_temperature = FAN_TEMPERATURE_30DEGC; + //get_option(&cpufan_temperature, "cpufan_temperature"); + + sysfan_control = FAN_CRUISE_CONTROL_DISABLED; + get_option(&sysfan_control, "sysfan_cruise_control"); + sysfan_speed = FAN_SPEED_5625; + get_option(&sysfan_speed, "sysfan_speed"); + //sysfan_temperature = FAN_TEMPERATURE_30DEGC; + //get_option(&sysfan_temperature, "sysfan_temperature"); // hwm_write(0x31, 0x20); // AVCC high limit // hwm_write(0x34, 0x06); // VIN2 low limit diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index afca796..d943127 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -79,19 +79,19 @@ static void hwm_setup(void) int cpufan_speed = 0, sysfan_speed = 0; int cpufan_temperature = 0, sysfan_temperature = 0; - if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS) - cpufan_control = FAN_CRUISE_CONTROL_DISABLED; - if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS) - cpufan_speed = FAN_SPEED_5625; - //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS) - // cpufan_temperature = FAN_TEMPERATURE_30DEGC; - - if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS) - sysfan_control = FAN_CRUISE_CONTROL_DISABLED; - if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS) - sysfan_speed = FAN_SPEED_5625; - //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) - // sysfan_temperature = FAN_TEMPERATURE_30DEGC; + cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + get_option(&cpufan_control, "cpufan_cruise_control"); + cpufan_speed = FAN_SPEED_5625; + get_option(&cpufan_speed, "cpufan_speed"); + //cpufan_temperature = FAN_TEMPERATURE_30DEGC; + //get_option(&cpufan_temperature, "cpufan_temperature"); + + sysfan_control = FAN_CRUISE_CONTROL_DISABLED; + get_option(&sysfan_control, "sysfan_cruise_control"); + sysfan_speed = FAN_SPEED_5625; + get_option(&sysfan_speed, "sysfan_speed"); + //sysfan_temperature = FAN_TEMPERATURE_30DEGC; + //get_option(&sysfan_temperature, "sysfan_temperature"); // hwm_write(0x31, 0x20); // AVCC high limit // hwm_write(0x34, 0x06); // VIN2 low limit diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index 956692d..d4747fd 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -48,8 +48,8 @@ static void mcf3_read_resources(device_t dev) } iommu = 1; - if (get_option(&iommu, "iommu") != CB_SUCCESS) - iommu = CONFIG_IOMMU; + iommu = CONFIG_IOMMU; + get_option(&iommu, "iommu"); if (iommu) { /* Add a GART aperture resource */ diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c index 2ff7182..34ac0ac 100644 --- a/src/southbridge/amd/sb600/sata.c +++ b/src/southbridge/amd/sb600/sata.c @@ -119,10 +119,8 @@ static void sata_init(struct device *dev) pci_write_config8(dev, 0x40, byte); // 1 means IDE, 0 means AHCI - if (get_option(&i, "sata_mode") != CB_SUCCESS) { - // no cmos option - i = CONFIG_SATA_MODE; - } + i = CONFIG_SATA_MODE; + get_option(&i, "sata_mode"); printk(BIOS_INFO, "%s: setting sata mode = %s\n", __func__, (i == SATA_MODE_IDE)?"ide":"ahci" ); dword = pci_read_config32(dev, 0x8); diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 83d6178..2f3db86 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -116,8 +116,8 @@ static void i82801dx_power_options(device_t dev) * * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - if (get_option(&pwr_on, "power_on_after_fail") != CB_SUCCESS) - pwr_on = MAINBOARD_POWER_ON; + pwr_on = MAINBOARD_POWER_ON; + get_option(&pwr_on, "power_on_after_fail"); reg8 = pci_read_config8(dev, GEN_PMCON_3); reg8 &= 0xfe; diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index cbc0106..b8edfe3 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -179,8 +179,8 @@ static void i82801gx_power_options(device_t dev) * * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - if (get_option(&pwr_on, "power_on_after_fail") != CB_SUCCESS) - pwr_on = MAINBOARD_POWER_ON; + pwr_on = MAINBOARD_POWER_ON; + get_option(&pwr_on, "power_on_after_fail"); reg8 = pci_read_config8(dev, GEN_PMCON_3); reg8 &= 0xfe; diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 0ba33d6..4f576c4 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -186,8 +186,8 @@ static void i82801ix_power_options(device_t dev) * * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. */ - if (get_option(&pwr_on, "power_on_after_fail") != CB_SUCCESS) - pwr_on = MAINBOARD_POWER_ON; + pwr_on = MAINBOARD_POWER_ON; + get_option(&pwr_on, "power_on_after_fail"); reg8 = pci_read_config8(dev, D31F0_GEN_PMCON_3); reg8 &= 0xfe;

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Patch merged into coreboot/master: f69a27b device: drop i915 specific headers from resource allocator includes
by gerrit＠coreboot.org 08 Mar '15

08 Mar '15

the following patch was just integrated into master: commit f69a27bcd38e44d9aa3df9c7c159c85ad90817ad Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jan 6 13:08:23 2015 -0800 device: drop i915 specific headers from resource allocator includes src/include/device/ is the place for include files of the resource allocator. Hence, drop the i915 include file copies and use the ones supplied with the i915 driver instead. The only remaining user of this was the Intel Whitetip Mountain 2 reference board, all other occurences have been previously fixed already. Change-Id: Ib9f72df4e8f847597508971e9dbf671f49019767 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/8140 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/8140 for details. -gerrit

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Patch merged into coreboot/master: f0bbc95 crossgcc: Add RISC-V support
by gerrit＠coreboot.org 08 Mar '15

08 Mar '15

the following patch was just integrated into master: commit f0bbc95f12c99ac956c9d8a85bac38db4ad6bcb4 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Mar 7 10:57:25 2015 +0100 crossgcc: Add RISC-V support Change-Id: If1e0f7ed21f67d7a185dad251ede81ddbc18c4e5 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/8629 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/8629 for details. -gerrit

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Patch merged into coreboot/master: 53c388f crossgcc: Update toolchain
by gerrit＠coreboot.org 08 Mar '15

08 Mar '15

the following patch was just integrated into master: commit 53c388fe6dfb4fc4ffcee6c58345d353c6ec33bf Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Mar 7 09:55:18 2015 +0100 crossgcc: Update toolchain Update GCC to 4.9.2, binutils to 2.25. Change-Id: Iae9763163b7f42c55a39e26b4beedee67d14a6e4 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/8628 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/8628 for details. -gerrit

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coreboot-gerrit March 2015