coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: nb/amd/mct_ddr3: Fix odd rank data corruption
by Timothy Pearson 29 Nov '15

29 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12058 -gerrit commit 80aa032684310a6a10e0169bb0a4ae246d3ad0bb Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Aug 27 13:19:34 2015 -0500 nb/amd/mct_ddr3: Fix odd rank data corruption The odd rank of each DIMM could experience data corruption due to incorrect DQS training. Fix the DQS training algorithm by executing the relevant portions of the training algorithm on the odd ranks. Change-Id: Ibc51f5052d5189e45b3d9aa98ca8febbfe13f178 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 06597e2..9362a60 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1320,9 +1320,9 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, Receiver = receiver_start; /* There are four receiver pairs, loosely associated with chipselects. - * This is essentially looping over each DIMM. + * This is essentially looping over each rank within each DIMM. */ - for (; Receiver < receiver_end; Receiver += 2) { + for (; Receiver < receiver_end; Receiver++) { dimm = (Receiver >> 1); if ((Receiver & 0x1) == 0) { /* Even rank of DIMM */ @@ -1336,18 +1336,27 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, continue; } +#if DQS_TRAIN_DEBUG > 0 + printk(BIOS_DEBUG, "TrainDQSRdWrPos: Training DQS read/write position for receiver %d (DIMM %d)\n", Receiver, dimm); +#endif + /* Initialize variables */ for (lane = lane_start; lane < lane_end; lane++) { passing_dqs_delay_found[lane] = 0; } - memset(dqs_results_array, 0, sizeof(dqs_results_array)); + if ((Receiver & 0x1) == 0) { + /* Even rank of DIMM */ + memset(dqs_results_array, 0, sizeof(dqs_results_array)); + + /* Read initial read / write DQS delays */ + read_dqs_write_timing_control_registers(initial_write_dqs_delay, dev, dct, dimm, index_reg); + read_dqs_read_data_timing_registers(initial_read_dqs_delay, dev, dct, dimm, index_reg); - /* Read initial read / write DQS delays */ - read_dqs_write_timing_control_registers(initial_write_dqs_delay, dev, dct, dimm, index_reg); - read_dqs_read_data_timing_registers(initial_read_dqs_delay, dev, dct, dimm, index_reg); + /* Read current settings of other (previously trained) lanes */ + read_dqs_write_data_timing_registers(initial_write_data_timing, dev, dct, dimm, index_reg); + } - /* Read current settings of other (previously trained) lanes */ - read_dqs_write_data_timing_registers(initial_write_data_timing, dev, dct, dimm, index_reg); + /* Initialize iterators */ memcpy(current_write_data_delay, initial_write_data_timing, sizeof(current_write_data_delay)); for (lane = lane_start; lane < lane_end; lane++) {

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New patch to review for coreboot: SeaBIOS/Kconfig: Remove SEABIOS_MALLOC_UPPERMEMORY option
by Martin Roth 29 Nov '15

29 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12570 -gerrit commit 17a2aa428c4ee415581dff1028c240f43daf0db7 Author: Martin Roth <martinroth(a)google.com> Date: Sat Nov 28 16:32:25 2015 -0700 SeaBIOS/Kconfig: Remove SEABIOS_MALLOC_UPPERMEMORY option This has been replaced by the PAYLOAD_CONFIGFILE option, allowing any SeaBIOS config option to be set by a platform. Change-Id: I584c4c481266740840158baba76581d68e69b448 Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/external/Makefile.inc | 3 +-- payloads/external/SeaBIOS/Kconfig | 12 ------------ payloads/external/SeaBIOS/Makefile.inc | 3 --- 3 files changed, 1 insertion(+), 17 deletions(-) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index b044a48..847eef1 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -54,8 +54,7 @@ seabios: CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ CONFIG_SEABIOS_VGA_COREBOOT=$(CONFIG_SEABIOS_VGA_COREBOOT) \ CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \ - CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) \ - CONFIG_SEABIOS_MALLOC_UPPERMEMORY=$(CONFIG_SEABIOS_MALLOC_UPPERMEMORY) + CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) filo: $(MAKE) -C payloads/external/FILO -f Makefile.inc \ diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 468c689..4f4fb02 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -35,18 +35,6 @@ config SEABIOS_THREAD_OPTIONROMS variations during option ROM code execution. It is not known if all option ROMs will behave properly with this option. -config SEABIOS_MALLOC_UPPERMEMORY - bool - default y - help - Use the "Upper Memory Block" area (0xc0000-0xf0000) for internal - "low memory" allocations. If this is not selected, the memory is - instead allocated from the "9-segment" (0x90000-0xa0000). - This is not typically needed, but may be required on some platforms - to allow USB and SATA buffers to be written correctly by the - hardware. In general, if this is desired, the option will be - set to 'N' by the chipset Kconfig. - config SEABIOS_VGA_COREBOOT prompt "Include generated option rom that implements legacy VGA BIOS compatibility" default n diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 21da35e..7754afb 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -31,9 +31,6 @@ ifeq ($(CONFIG_CONSOLE_SERIAL),y) else echo "# CONFIG_DEBUG_SERIAL is not set" >> seabios/.config endif -ifneq ($(CONFIG_SEABIOS_MALLOC_UPPERMEMORY),y) - echo "# CONFIG_MALLOC_UPPERMEMORY is not set" >> seabios/.config -endif ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) echo "# CONFIG_THREAD_OPTIONROMS is not set" >> seabios/.config endif

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New patch to review for coreboot: intel/mohonpeak: Change SEABIOS_MALLOC_UPPERMEMORY to config_seabios
by Martin Roth 29 Nov '15

29 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12569 -gerrit commit 44c8816e6ff099abc3e3ecd43714aa34c2ae0aff Author: Martin Roth <martinroth(a)google.com> Date: Sat Nov 28 16:30:40 2015 -0700 intel/mohonpeak: Change SEABIOS_MALLOC_UPPERMEMORY to config_seabios Instead of the SEABIOS_MALLOC_UPPERMEMORY option, use a saved SeaBIOS .config file to do the same thing. Change-Id: I29110a382b7770329ef938876426e571fbbbb339 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/intel/mohonpeak/Kconfig | 8 ++++---- src/mainboard/intel/mohonpeak/config_seabios | 5 +++++ 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig index 8ea184b..8f6e077 100644 --- a/src/mainboard/intel/mohonpeak/Kconfig +++ b/src/mainboard/intel/mohonpeak/Kconfig @@ -71,10 +71,10 @@ config UART_FOR_CONSOLE help The Mohon Peak board uses COM2 (2f8) for the serial console. -config SEABIOS_MALLOC_UPPERMEMORY - bool - default n - help + config PAYLOAD_CONFIGFILE + string + default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" + help The Avoton/Rangeley chip does not allow devices to write into the 0xe000 segment. This means that USB/SATA devices will not work in SeaBIOS unless we put the SeaBIOS buffer area down in the 0x9000 segment. diff --git a/src/mainboard/intel/mohonpeak/config_seabios b/src/mainboard/intel/mohonpeak/config_seabios new file mode 100644 index 0000000..f688f2b --- /dev/null +++ b/src/mainboard/intel/mohonpeak/config_seabios @@ -0,0 +1,5 @@ +# The Avoton/Rangeley chip does not allow devices to write into the 0xe000 +# segment. This means that USB/SATA devices will not work in SeaBIOS unless +# we put the SeaBIOS buffer area down in the 0x9000 segment. + +# CONFIG_MALLOC_UPPERMEMORY is not set

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New patch to review for coreboot: payloads/external/SeaBIOS: Add option for saved SeaBIOS .config
by Martin Roth 29 Nov '15

29 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12568 -gerrit commit c0b34efb010a689335316ef9bbdfd92456c3dad9 Author: Martin Roth <martinroth(a)google.com> Date: Sat Nov 28 15:44:34 2015 -0700 payloads/external/SeaBIOS: Add option for saved SeaBIOS .config Instead of adding various SeaBIOS options into the coreboot Kconfig, just add a way to use saved SeaBIOS .config files. These files can contain full SeaBIOS .configs, but is really intended for individual options. The coreboot Kconfig options take precedence over the settings in the saved .config. Change-Id: Ia7f9c76555b8e290777207b3f637c94c4d67a782 Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/external/Makefile.inc | 1 + payloads/external/SeaBIOS/Kconfig | 10 +++++++++- payloads/external/SeaBIOS/Makefile.inc | 8 ++++++++ 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index c5f413f..b044a48 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -50,6 +50,7 @@ seabios: AS="$(AS_x86_32)" IASL="$(IASL)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ + CONFIG_PAYLOAD_CONFIGFILE=$(CONFIG_PAYLOAD_CONFIGFILE) \ CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ CONFIG_SEABIOS_VGA_COREBOOT=$(CONFIG_SEABIOS_VGA_COREBOOT) \ CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \ diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 6224697..468c689 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -54,10 +54,18 @@ config SEABIOS_VGA_COREBOOT bool help Coreboot can initialize the GPU of some mainboards. - + After initializing the GPU, the information about it can be passed to the payload. Provide an option rom that implements this legacy VGA BIOS compatibility requirement. +config PAYLOAD_CONFIGFILE + string "SeaBIOS config file" + default "" + help + This option allows a platform to set Kconfig options for a basic + SeaBIOS payload. In general, if the option is used, the default + would be "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" + config PAYLOAD_FILE default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf" diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index ec877a9..21da35e 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -41,6 +41,14 @@ ifeq ($(CONFIG_SEABIOS_VGA_COREBOOT),y) echo "CONFIG_VGA_COREBOOT=y" >> seabios/.config echo "CONFIG_BUILD_VGABIOS=y" >> seabios/.config endif +ifneq ($(CONFIG_PAYLOAD_CONFIGFILE),) +ifneq ("$(wildcard $(CONFIG_PAYLOAD_CONFIGFILE))","") + cat $(CONFIG_PAYLOAD_CONFIGFILE) >> seabios/.config +else + echo "Error: File $(CONFIG_PAYLOAD_CONFIGFILE) does not exist" + false +endif +endif # This shows how to force a previously set .config option *off* #echo "# CONFIG_SMBIOS is not set" >> seabios/.config $(MAKE) -C seabios olddefconfig OUT=out/

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Patch set updated for coreboot: nb/amd/amdmct/mct_ddr3: Ensure channel clock skew is properly set
by Timothy Pearson 28 Nov '15

28 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12055 -gerrit commit 60e2466cbdfe7cef2d94fa0bc9481ac9722e221f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Aug 27 13:17:14 2015 -0500 nb/amd/amdmct/mct_ddr3: Ensure channel clock skew is properly set Also fix incorrect Trfc[0-3] value on Family 15h. Change-Id: Iafc233984ae1d44fe6a1cb5b109d36397cbd991a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 46 ++++++++++++++++------------- 1 file changed, 25 insertions(+), 21 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 248fc65..74d5a8d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -3068,6 +3068,23 @@ static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTst printk(BIOS_DEBUG, "\t\tDCTInit_D: mct_SPDCalcWidth Done\n"); if (AutoCycTiming_D(pMCTstat, pDCTstat, dct) < SC_StopError) { printk(BIOS_DEBUG, "\t\tDCTInit_D: AutoCycTiming_D Done\n"); + + /* SkewMemClk must be set before MemClkFreqVal is set + * This relies on DCTInit_D being called for DCT 1 after + * it has already been called for DCT 0... + */ + if (is_fam15h()) { + /* Set memory clock skew if needed */ + if (dct == 1) { + if (!pDCTstat->stopDCT[0]) { + printk(BIOS_DEBUG, "\t\tDCTInit_D: enabling intra-channel clock skew\n"); + dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, 0, 0x98, 0x0d0fe00a); + dword |= (0x1 << 4); /* SkewMemClk = 1 */ + Set_NB32_index_wait_DCT(pDCTstat->dev_dct, 0, 0x98, 0x0d0fe00a, dword); + } + } + } + if (AutoConfig_D(pMCTstat, pDCTstat, dct) < SC_StopError) { printk(BIOS_DEBUG, "\t\tDCTInit_D: AutoConfig_D Done\n"); if (PlatformSpec_D(pMCTstat, pDCTstat, dct) < SC_StopError) { @@ -3077,8 +3094,6 @@ static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTst } } } - - } static void DCTFinalInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) @@ -3086,17 +3101,6 @@ static void DCTFinalInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *p uint32_t dword; /* Finalize DRAM init on a single node */ - if (is_fam15h()) { - /* Set memory clock skew if needed */ - if (dct == 0) { - if (!pDCTstat->stopDCT[0] && !pDCTstat->stopDCT[1]) { - dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, 0x98, 0x0d0fe00a); - dword |= (0x1 << 4); /* SkewMemClk = 1 */ - Set_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, 0x98, 0x0d0fe00a, dword); - } - } - } - if (!pDCTstat->stopDCT[dct]) { if (!(pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW))) { printk(BIOS_DEBUG, "\t\tDCTFinalInit_D: StartupDCT_D Start\n"); @@ -3299,28 +3303,28 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, if (Twtr < val) Twtr = val; - val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_Upper_tRAS_tRC] & 0xFF; + val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_Upper_tRAS_tRC] & 0xff; val >>= 4; val <<= 8; - val |= pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRCmin] & 0xFF; + val |= pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRCmin] & 0xff; val *= MTB16x; if (Trc < val) Trc = val; - byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_Density] & 0xF; + byte = pDCTstat->spd_data.spd_bytes[dct + i][SPD_Density] & 0xf; if (Trfc[LDIMM] < byte) Trfc[LDIMM] = byte; - val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_Upper_tRAS_tRC] & 0xF; + val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_Upper_tRAS_tRC] & 0xf; val <<= 8; - val |= (pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRASmin] & 0xFF); + val |= (pDCTstat->spd_data.spd_bytes[dct + i][SPD_tRASmin] & 0xff); val *= MTB16x; if (Tras < val) Tras = val; - val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_Upper_tFAW] & 0xF; + val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_Upper_tFAW] & 0xf; val <<= 8; - val |= pDCTstat->spd_data.spd_bytes[dct + i][SPD_tFAWmin] & 0xFF; + val |= pDCTstat->spd_data.spd_bytes[dct + i][SPD_tFAWmin] & 0xff; val *= MTB16x; if (Tfaw < val) Tfaw = val; @@ -3527,7 +3531,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat, /* Trfc0-Trfc3 */ for (i=0; i<4; i++) if (pDCTstat->Trfc[i] == 0x0) - pDCTstat->Trfc[i] = 0x4; + pDCTstat->Trfc[i] = 0x1; dword = Get_NB32_DCT(dev, dct, 0x208); /* DRAM Timing 2 */ dword &= ~(0x07070707); dword |= (pDCTstat->Trfc[3] & 0x7) << 24; /* Trfc3 */

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New patch to review for coreboot: external/Makefile.inc: Update SeaBIOS version file
by Martin Roth 28 Nov '15

28 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12567 -gerrit commit 2066b5b423cf787e1961f81a89222e452f95fd50 Author: Martin Roth <martinroth(a)google.com> Date: Sat Nov 28 13:23:48 2015 -0700 external/Makefile.inc: Update SeaBIOS version file SeaBIOS updated how versioning is done, and out/version.c no longer exists. The new file with version information is autoversion.h. Change-Id: I10abee73ecc51e52c9ff7a2e7a9099339b1a4b40 Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/external/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index eedee05..c5f413f 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -32,7 +32,7 @@ endif # set up payload config and version files for later inclusion ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) PAYLOAD_CONFIG=payloads/external/SeaBIOS/seabios/.config -PAYLOAD_VERSION=payloads/external/SeaBIOS/seabios/out/version.c +PAYLOAD_VERSION=payloads/external/SeaBIOS/seabios/out/autoversion.h endif ifeq ($(CONFIG_PAYLOAD_FILO),y) PAYLOAD_CONFIG=payloads/external/FILO/filo/.config

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Patch set updated for coreboot: SeaBIOS: update stable release from 1.8.2 to 1.9.0
by Alexander Couzens 28 Nov '15

28 Nov '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12566 -gerrit commit 63e5230b4793b76011424d238b0bece85daab41b Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sat Nov 28 18:40:27 2015 +0100 SeaBIOS: update stable release from 1.8.2 to 1.9.0 * The default boot menu key is now the ESC key (instead of F12) * Initial support for Trusted Platform Module (TPM) hardware and BIOS calls * Initial support for chain loading SeaBIOS from Grub (via multiboot support) * Initial support for booting from SD cards on real hardware * virtio 1.0 device support * The build will no longer include the build hostname or build time on "clean" builds. This makes the build binaries more "reproducible". * Basic support for running SeaBIOS on Baytrail Chromebooks * SeaVGABIOS improvements: * Improved support for old versions of x86emu (the "leal" instruction is now emulated) * Several bug fixes and code cleanups Change-Id: Ifbd50f1884959fed4c4f666b87f2ef7b4769c6d3 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- payloads/external/SeaBIOS/Kconfig | 2 +- payloads/external/SeaBIOS/Makefile.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 6224697..0d3f92d 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -5,7 +5,7 @@ choice default SEABIOS_STABLE config SEABIOS_STABLE - bool "1.8.2" + bool "1.9.0" help Stable SeaBIOS version config SEABIOS_MASTER diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index ec877a9..714dce4 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=33fbe13a3e2a01e0ba1087a8feed801a0451db21 +TAG-$(CONFIG_SEABIOS_STABLE)=01a84bea2d28a19d2405c1ecac4bdef17683cc0c unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG

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Patch set updated for coreboot: SeaBIOS: update stable release from 1.8.2 to 1.9.0
by Alexander Couzens 28 Nov '15

28 Nov '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12566 -gerrit commit aa10a5367dee3fa04d6669de490f22a210a535cf Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sat Nov 28 18:40:27 2015 +0100 SeaBIOS: update stable release from 1.8.2 to 1.9.0 * The default boot menu key is now the ESC key (instead of F12) * Initial support for Trusted Platform Module (TPM) hardware and BIOS calls * Initial support for chain loading SeaBIOS from Grub (via multiboot support) * Initial support for booting from SD cards on real hardware * virtio 1.0 device support * The build will no longer include the build hostname or build time on "clean" builds. This makes the build binaries more "reproducible". * Basic support for running SeaBIOS on Baytrail Chromebooks * SeaVGABIOS improvements: * Improved support for old versions of x86emu (the "leal" instruction is now emulated) * Several bug fixes and code cleanups For a complete changelog see http://seabios.org/Releases#SeaBIOS_1.9.0 Change-Id: Ifbd50f1884959fed4c4f666b87f2ef7b4769c6d3 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- payloads/external/SeaBIOS/Kconfig | 2 +- payloads/external/SeaBIOS/Makefile.inc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 6224697..0d3f92d 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -5,7 +5,7 @@ choice default SEABIOS_STABLE config SEABIOS_STABLE - bool "1.8.2" + bool "1.9.0" help Stable SeaBIOS version config SEABIOS_MASTER diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index ec877a9..714dce4 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=33fbe13a3e2a01e0ba1087a8feed801a0451db21 +TAG-$(CONFIG_SEABIOS_STABLE)=01a84bea2d28a19d2405c1ecac4bdef17683cc0c unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG

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Patch merged into coreboot/master: nb/amd/amdfam10: Work around sporadic lockups when CC6 enabled
by gerrit＠coreboot.org 28 Nov '15

28 Nov '15

the following patch was just integrated into master: commit 8528e39fbab6473a61ad3250ef25afb53546bb15 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Aug 20 15:53:25 2015 -0500 nb/amd/amdfam10: Work around sporadic lockups when CC6 enabled The silicon in control of CC6 appears to contain minor bugs and / or deviations from the BKDG; through trial and error it was found that these issues can be worked around by reserving the entire possible CC6 save region, regardless of currently installed node count. Change-Id: If31140651f25f9c524a824b2da552ce3690eae18 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12054 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/12054 for details. -gerrit

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Patch merged into coreboot/master: libpayload: Remove redundant 8250 MMIO32 UART driver
by gerrit＠coreboot.org 28 Nov '15

28 Nov '15

the following patch was just integrated into master: commit 4d5317e5a4dc1a84ddddeadb3222125d8581644d Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Nov 23 16:18:12 2015 -0800 libpayload: Remove redundant 8250 MMIO32 UART driver The more generic 8250 driver can handle both port-mapped and memory- mapped 8250-compatible UARTs, with different register sizes. Thus, a separate driver for MMIO32 is not needed. The generic 8250 driver was tested to work for both output and input, on Apollolake SoC, which only presents an MMIO32 UART. Change-Id: Idab766588ddd097649a37de92394b0078ecc660a Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: https://review.coreboot.org/12524 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/12524 for details. -gerrit

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coreboot-gerrit November 2015