coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

1 participants
1544 discussions

Patch set updated for coreboot: x86/smm: Initialize SMM on some CPUs one-by-one
by Patrick Georgi 28 Nov '15

28 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/6311 -gerrit commit d55a0b843f451ec79602c8fa49cd266ae7bf2836 Author: Damien Zammit <damien(a)zamaudio.com> Date: Sat Nov 28 21:27:05 2015 +1100 x86/smm: Initialize SMM on some CPUs one-by-one We currently race in SMM init on Atom 230 (and potentially other CPUs). At least on the 230, this leads to a hang on RSM, likely because both hyperthreads mess around with SMBASE and other SMM state variables in parallel without coordination. The same behaviour occurs with Atom D5xx. Change it so first APs are spun up and sent to sleep, then BSP initializes SMM, then every CPU, one after another. Only do this when SERIALIZE_SMM_INITIALIZATION is set. Set the flag for Atom CPUs. Change-Id: I1ae864e37546298ea222e81349c27cf774ed251f Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/cpu/intel/model_106cx/Kconfig | 1 + src/cpu/x86/Kconfig | 4 ++++ src/cpu/x86/lapic/lapic_cpu_init.c | 47 +++++++++++++++++++++++++++++++++++++- 3 files changed, 51 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 09acfd9..a005ba2 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -11,6 +11,7 @@ config CPU_INTEL_MODEL_106CX select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS + select SERIALIZED_SMM_INITIALIZATION if CPU_INTEL_MODEL_106CX diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 131cbf2..afec4de 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -96,6 +96,10 @@ config SMM_LAPIC_REMAP_MITIGATION default y if NORTHBRIDGE_INTEL_NEHALEM default n +config SERIALIZED_SMM_INITIALIZATION + bool + default n + config X86_AMD_FIXED_MTRRS bool default n diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index ef150a5..4bfe5fd 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -458,6 +458,41 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu) } +#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 +static void smm_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) +{ + device_t cpu; + int pre_count = atomic_read(&active_cpus); + + /* Loop through the cpus once to let them run through SMM relocator */ + + for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) { + if (cpu->path.type != DEVICE_PATH_APIC) { + continue; + } + + printk(BIOS_ERR, "considering CPU 0x%02x for SMM init\n", + cpu->path.apic.apic_id); + + if (cpu==bsp_cpu) + continue; + + if (!cpu->enabled) { + continue; + } + + if (!start_cpu(cpu)) { + /* Record the error in cpu? */ + printk(BIOS_ERR, "CPU 0x%02x would not start!\n", + cpu->path.apic.apic_id); + } + + /* FIXME: endless loop */ + while (atomic_read(&active_cpus) != pre_count) ; + } +} +#endif + static void wait_other_cpus_stop(struct bus *cpu_bus) { struct device *cpu; @@ -528,7 +563,8 @@ void initialize_cpus(struct bus *cpu_bus) #endif #if CONFIG_HAVE_SMI_HANDLER - smm_init(); + if (!IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION)) + smm_init(); #endif #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 @@ -547,4 +583,13 @@ void initialize_cpus(struct bus *cpu_bus) /* Now wait the rest of the cpus stop*/ wait_other_cpus_stop(cpu_bus); #endif + + if (IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION)) { + /* BSP only, all APs are sleeping */ + smm_init(); +#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 + last_cpu_index = 0; + smm_other_cpus(cpu_bus, info->cpu); +#endif + } }

1 0

Patch set updated for coreboot: x86/smm: Initialize SMM on some CPUs one-by-one
by Damien Zammit 28 Nov '15

28 Nov '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/6311 -gerrit commit 3b6b222b7c8acada9dd9ec124301eb45e7104f0c Author: Damien Zammit <damien(a)zamaudio.com> Date: Sat Nov 28 21:27:05 2015 +1100 x86/smm: Initialize SMM on some CPUs one-by-one We currently race in SMM init on Atom 230 (and potentially other CPUs). At least on the 230, this leads to a hang on RSM, likely because both hyperthreads mess around with SMBASE and other SMM state variables in parallel without coordination. The same behaviour occurs with Atom D5xx. Change it so first APs are spun up and sent to sleep, then BSP initializes SMM, then every CPU, one after another. Only do this when SERIALIZE_SMM_INITIALIZATION is set. Set the flag for Atom CPUs. Change-Id: I1ae864e37546298ea222e81349c27cf774ed251f Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/cpu/intel/model_106cx/Kconfig | 1 + src/cpu/x86/Kconfig | 4 ++++ src/cpu/x86/lapic/lapic_cpu_init.c | 47 +++++++++++++++++++++++++++++++++++++- 3 files changed, 51 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 09acfd9..a005ba2 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -11,6 +11,7 @@ config CPU_INTEL_MODEL_106CX select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS + select SERIALIZED_SMM_INITIALIZATION if CPU_INTEL_MODEL_106CX diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 131cbf2..afec4de 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -96,6 +96,10 @@ config SMM_LAPIC_REMAP_MITIGATION default y if NORTHBRIDGE_INTEL_NEHALEM default n +config SERIALIZED_SMM_INITIALIZATION + bool + default n + config X86_AMD_FIXED_MTRRS bool default n diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index ef150a5..4bfe5fd 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -458,6 +458,41 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu) } +#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 +static void smm_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) +{ + device_t cpu; + int pre_count = atomic_read(&active_cpus); + + /* Loop through the cpus once to let them run through SMM relocator */ + + for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) { + if (cpu->path.type != DEVICE_PATH_APIC) { + continue; + } + + printk(BIOS_ERR, "considering CPU 0x%02x for SMM init\n", + cpu->path.apic.apic_id); + + if (cpu==bsp_cpu) + continue; + + if (!cpu->enabled) { + continue; + } + + if (!start_cpu(cpu)) { + /* Record the error in cpu? */ + printk(BIOS_ERR, "CPU 0x%02x would not start!\n", + cpu->path.apic.apic_id); + } + + /* FIXME: endless loop */ + while (atomic_read(&active_cpus) != pre_count) ; + } +} +#endif + static void wait_other_cpus_stop(struct bus *cpu_bus) { struct device *cpu; @@ -528,7 +563,8 @@ void initialize_cpus(struct bus *cpu_bus) #endif #if CONFIG_HAVE_SMI_HANDLER - smm_init(); + if (!IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION)) + smm_init(); #endif #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 @@ -547,4 +583,13 @@ void initialize_cpus(struct bus *cpu_bus) /* Now wait the rest of the cpus stop*/ wait_other_cpus_stop(cpu_bus); #endif + + if (IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION)) { + /* BSP only, all APs are sleeping */ + smm_init(); +#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 + last_cpu_index = 0; + smm_other_cpus(cpu_bus, info->cpu); +#endif + } }

1 0

Patch set updated for coreboot: mainboard/intel/d510mo: Add Intel D510MO mainboard
by Damien Zammit 28 Nov '15

28 Nov '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/10074 -gerrit commit 0875837665819abf21080bb84be8bc9b6395a462 Author: Damien Zammit <damien(a)zamaudio.com> Date: Mon May 4 10:41:21 2015 +1000 mainboard/intel/d510mo: Add Intel D510MO mainboard Board uses Pineview native raminit Board boots from grub to linux kernel VGA needs work, currently headless machine Change-Id: I8e459c6d40e0711fac8fb8cfbf31d9cb2aaab3aa Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/intel/d510mo/Kconfig | 47 +++++++ src/mainboard/intel/d510mo/Kconfig.name | 2 + src/mainboard/intel/d510mo/Makefile.inc | 1 + src/mainboard/intel/d510mo/acpi/ec.asl | 1 + src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl | 35 ++++++ .../intel/d510mo/acpi/pineview_pci_irqs.asl | 72 +++++++++++ src/mainboard/intel/d510mo/acpi/superio.asl | 1 + src/mainboard/intel/d510mo/acpi_tables.c | 21 ++++ src/mainboard/intel/d510mo/board_info.txt | 5 + src/mainboard/intel/d510mo/cstates.c | 7 ++ src/mainboard/intel/d510mo/devicetree.cb | 94 ++++++++++++++ src/mainboard/intel/d510mo/dsdt.asl | 38 ++++++ src/mainboard/intel/d510mo/hda_verb.c | 7 ++ src/mainboard/intel/d510mo/mainboard.c | 36 ++++++ src/mainboard/intel/d510mo/romstage.c | 136 +++++++++++++++++++++ 15 files changed, 503 insertions(+) diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig new file mode 100644 index 0000000..7981f92 --- /dev/null +++ b/src/mainboard/intel/d510mo/Kconfig @@ -0,0 +1,47 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_INTEL_D510MO + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_INTEL_SOCKET_FCBGA559 + select NORTHBRIDGE_INTEL_PINEVIEW + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_WINBOND_W83627THG + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_1024 + +config MAX_CPUS + int + default 4 + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config CBFS_SIZE + hex "Size of CBFS filesystem in ROM" + default 0x100000 + +config MAINBOARD_DIR + string + default intel/d510mo + +config MAINBOARD_PART_NUMBER + string + default "D510MO" + +endif # BOARD_INTEL_D510MO diff --git a/src/mainboard/intel/d510mo/Kconfig.name b/src/mainboard/intel/d510mo/Kconfig.name new file mode 100644 index 0000000..2df0dca --- /dev/null +++ b/src/mainboard/intel/d510mo/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_D510MO + bool "D510MO" diff --git a/src/mainboard/intel/d510mo/Makefile.inc b/src/mainboard/intel/d510mo/Makefile.inc new file mode 100644 index 0000000..f9621db --- /dev/null +++ b/src/mainboard/intel/d510mo/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += cstates.c diff --git a/src/mainboard/intel/d510mo/acpi/ec.asl b/src/mainboard/intel/d510mo/acpi/ec.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl b/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..debf4b1 --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 22}, + Package() { 0x0000ffff, 1, 0, 20}, + Package() { 0x0000ffff, 2, 0, 17}, + Package() { 0x0000ffff, 3, 0, 16}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + }) +} diff --git a/src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl b/src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl new file mode 100644 index 0000000..3fa6fdb --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for pineview */ +/* FIXME: EHCI controller not working yet */ + +/* PCI Interrupt Routing */ +Method(_PRT) +{ + If (PICM) { + Return (Package() { + /* Internal GFX */ + Package() { 0x0002ffff, 0, 0, 16 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, 0, 22 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, 0, 17 }, + Package() { 0x001cffff, 1, 0, 16 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, 0, 23 }, + Package() { 0x001dffff, 1, 0, 19 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 16 }, + Package() { 0x001dffff, 0, 0, 23 }, + /* PCI 0:1e.0 */ + Package() { 0x001effff, 0, 0, 22 }, + /* LPC/SATA/SMBUS 0:1f.2, 0:1f.3 */ + Package() { 0x001fffff, 1, 0, 19 }, + Package() { 0x001fffff, 1, 0, 19 }, + Package() { 0x001fffff, 1, 0, 19 }, + }) + } Else { + Return (Package() { + /* Internal GFX */ + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + /* PCI 0:1e.0 */ + Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + /* LPC/SATA/SMBUS 0:1f.2, 0:1f.3 */ + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} diff --git a/src/mainboard/intel/d510mo/acpi/superio.asl b/src/mainboard/intel/d510mo/acpi/superio.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi/superio.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/intel/d510mo/acpi_tables.c b/src/mainboard/intel/d510mo/acpi_tables.c new file mode 100644 index 0000000..92688bf --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi_tables.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <southbridge/intel/i82801gx/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ +} diff --git a/src/mainboard/intel/d510mo/board_info.txt b/src/mainboard/intel/d510mo/board_info.txt new file mode 100644 index 0000000..192798a --- /dev/null +++ b/src/mainboard/intel/d510mo/board_info.txt @@ -0,0 +1,5 @@ +Category: desktop +Board URL: http://www.intel.com/p/en_US/support/highlights/dsktpboards/d510mo +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/intel/d510mo/cstates.c b/src/mainboard/intel/d510mo/cstates.c new file mode 100644 index 0000000..2d543ff --- /dev/null +++ b/src/mainboard/intel/d510mo/cstates.c @@ -0,0 +1,7 @@ +#include <device/device.h> +#include <arch/x86/include/arch/acpigen.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb new file mode 100644 index 0000000..221cc54 --- /dev/null +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -0,0 +1,94 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/pineview # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_FCBGA559 # CPU + device lapic 0 on end # APIC + end + end + device domain 0 on # PCI domain + device pci 0.0 on end # Host Bridge + device pci 2.0 off end # Integrated graphics controller + chip southbridge/intel/i82801gx # Southbridge + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + register "ide_legacy_combined" = "0x1" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x0" + + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on end # PCIe 2 + device pci 1c.2 on end # PCIe 3 + device pci 1c.3 on end # PCIe 4 + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.3 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # ISA bridge + chip superio/winbond/w83627thg # Super I/O + device pnp 4e.0 off end # Floppy + device pnp 4e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 4e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + irq 0xf1 = 0 + end + device pnp 4e.5 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + irq 0xf0 = 0x80 + end + device pnp 4e.6 off end + device pnp 4e.7 off end + device pnp 4e.8 off end + device pnp 4e.9 off end + device pnp 4e.a off end # ACPI + device pnp 4e.b on # HWM + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 1f.1 off end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMbus + device pci 1f.4 off end + device pci 1f.5 off end + device pci 1f.6 off end + end + end +end diff --git a/src/mainboard/intel/d510mo/dsdt.asl b/src/mainboard/intel/d510mo/dsdt.asl new file mode 100644 index 0000000..c1f72f9 --- /dev/null +++ b/src/mainboard/intel/d510mo/dsdt.asl @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/pineview/acpi/pineview.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/intel/d510mo/hda_verb.c b/src/mainboard/intel/d510mo/hda_verb.c new file mode 100644 index 0000000..072a306 --- /dev/null +++ b/src/mainboard/intel/d510mo/hda_verb.c @@ -0,0 +1,7 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[0] = {}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/intel/d510mo/mainboard.c b/src/mainboard/intel/d510mo/mainboard.c new file mode 100644 index 0000000..3b0ef0f --- /dev/null +++ b/src/mainboard/intel/d510mo/mainboard.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <drivers/intel/gma/i915.h> +#include <pc80/mc146818rtc.h> +#include <device/pci.h> + +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void) +{ + return NULL; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = NULL; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c new file mode 100644 index 0000000..b0bd0c0 --- /dev/null +++ b/src/mainboard/intel/d510mo/romstage.c @@ -0,0 +1,136 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stdlib.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <console/console.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <northbridge/intel/pineview/raminit.h> +#include <northbridge/intel/pineview/pineview.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <superio/winbond/w83627thg/w83627thg.h> +#include <superio/winbond/common/winbond.h> +#include <lib.h> +#include <arch/stages.h> + +#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) +#define SUPERIO_DEV PNP_DEV(0x4e, 0) + +#include <cpu/intel/romstage.h> + +/* Early mainboard specific GPIO setup */ +static void mb_gpio_init(void) +{ + device_t dev; + + /* Southbridge GPIOs. */ + dev = PCI_DEV(0x0, 0x1f, 0x0); + + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); + pci_write_config8(dev, GPIO_CNTL, 0x10); + + outl(0x1ff9f7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe0e9e803, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xece9e842, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x00002000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000000fe, DEFAULT_GPIOBASE + 0x30); + outl(0x0000007e, DEFAULT_GPIOBASE + 0x34); + outl(0x000300f3, DEFAULT_GPIOBASE + 0x38); +} + +static void nm10_enable_lpc(void) +{ + /* Disable Serial IRQ */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0x00); + /* Decode range */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, + pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x80) | 0x0010); + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, + CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN); + + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x0291); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x007c); +} + +static void rcba_config(void) +{ + /* Set up virtual channel 0 */ + RCBA32(0x0014) = 0x80000001; + RCBA32(0x001c) = 0x03128010; + + /* Device 1f interrupt pin register */ + RCBA32(0x3100) = 0x00042210; + RCBA32(0x3108) = 0x10004321; + + RCBA32(0x3104) = 0x00002100; + + /* PCIe Interrupts */ + RCBA32(0x310c) = 0x00214321; + /* HD Audio Interrupt */ + RCBA32(0x3110) = 0x00000001; + + /* dev irq route register */ + RCBA16(0x3140) = 0x0132; + RCBA16(0x3142) = 0x0146; + RCBA16(0x3144) = 0x0237; + RCBA16(0x3146) = 0x3201; + RCBA16(0x3148) = 0x0146; + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + + RCBA32(0x3418) = 0x003000e2; + RCBA32(0x3418) |= 1; +} + +void main(unsigned long bist) +{ + const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 }; + + if (bist == 0) + enable_lapic(); + + /* Disable watchdog timer */ + RCBA32(0x3410) = RCBA32(0x3410) | 0x20; + + /* Set southbridge and Super I/O GPIOs. */ + mb_gpio_init(); + + nm10_enable_lpc(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + report_bist_failure(bist); + enable_smbus(); + + pineview_early_initialization(); + + post_code(0x30); + + printk(BIOS_DEBUG, "Start native raminit\n"); + sdram_initialize(0, spd_addrmap); + printk(BIOS_DEBUG, "Native raminit done\n"); + + post_code(0x31); + ram_check(0x200000,0x300000); + + rcba_config(); +}

1 0

Patch set updated for coreboot: x86/smm: Initialize SMM on some CPUs one-by-one
by Damien Zammit 28 Nov '15

28 Nov '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/6311 -gerrit commit 3e24bc7f74d8663a801ea69aa18de94ff04a3c31 Author: Damien Zammit <damien(a)zamaudio.com> Date: Sat Nov 28 21:27:05 2015 +1100 x86/smm: Initialize SMM on some CPUs one-by-one We currently race in SMM init on Atom 230 (and potentially other CPUs). At least on the 230, this leads to a hang on RSM, likely because both hyperthreads mess around with SMBASE and other SMM state variables in parallel without coordination. The same behaviour occurs with Atom D5xx. Change it so first APs are spun up and sent to sleep, then BSP initializes SMM, then every CPU, one after another. Only do this when SERIALIZE_SMM_INITIALIZATION is set. Set the flag for Atom CPUs. Change-Id: I1ae864e37546298ea222e81349c27cf774ed251f Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/cpu/intel/model_106cx/Kconfig | 1 + src/cpu/x86/Kconfig | 5 +++++ src/cpu/x86/lapic/lapic_cpu_init.c | 46 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 52 insertions(+) diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 09acfd9..a005ba2 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -11,6 +11,7 @@ config CPU_INTEL_MODEL_106CX select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS + select SERIALIZED_SMM_INITIALIZATION if CPU_INTEL_MODEL_106CX diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 131cbf2..1671b50 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -96,6 +96,11 @@ config SMM_LAPIC_REMAP_MITIGATION default y if NORTHBRIDGE_INTEL_NEHALEM default n +config SERIALIZED_SMM_INITIALIZATION + bool + default y if CPU_INTEL_MODEL_106CX + default n + config X86_AMD_FIXED_MTRRS bool default n diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index ef150a5..a881236 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -458,6 +458,41 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu) } +#if CONFIG_SERIALIZED_SMM_INITIALIZATION +static void smm_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) +{ + device_t cpu; + int pre_count = atomic_read(&active_cpus); + + /* Loop through the cpus once to let them run through SMM relocator */ + + for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) { + if (cpu->path.type != DEVICE_PATH_APIC) { + continue; + } + + printk(BIOS_ERR, "considering CPU 0x%02x for SMM init\n", + cpu->path.apic.apic_id); + + if (cpu==bsp_cpu) + continue; + + if (!cpu->enabled) { + continue; + } + + if (!start_cpu(cpu)) { + /* Record the error in cpu? */ + printk(BIOS_ERR, "CPU 0x%02x would not start!\n", + cpu->path.apic.apic_id); + } + + /* FIXME: endless loop */ + while (atomic_read(&active_cpus) != pre_count) ; + } +} +#endif + static void wait_other_cpus_stop(struct bus *cpu_bus) { struct device *cpu; @@ -528,8 +563,10 @@ void initialize_cpus(struct bus *cpu_bus) #endif #if CONFIG_HAVE_SMI_HANDLER +#if !CONFIG_SERIALIZED_SMM_INITIALIZATION smm_init(); #endif +#endif #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 /* start all aps at first, so we can init ECC all together */ @@ -547,4 +584,13 @@ void initialize_cpus(struct bus *cpu_bus) /* Now wait the rest of the cpus stop*/ wait_other_cpus_stop(cpu_bus); #endif + +#if CONFIG_SERIALIZED_SMM_INITIALIZATION + /* BSP only, all APs are sleeping */ + smm_init(); +#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 + last_cpu_index = 0; + smm_other_cpus(cpu_bus, info->cpu); +#endif +#endif }

1 0

Patch set updated for coreboot: mainboard/intel/d510mo: Add Intel D510MO mainboard
by Damien Zammit 28 Nov '15

28 Nov '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/10074 -gerrit commit da05cb5ece2171bb9785f172d9d6ec91303309e9 Author: Damien Zammit <damien(a)zamaudio.com> Date: Mon May 4 10:41:21 2015 +1000 mainboard/intel/d510mo: Add Intel D510MO mainboard Board uses Pineview native raminit Board boots from grub to linux kernel VGA needs work, currently headless machine Change-Id: I8e459c6d40e0711fac8fb8cfbf31d9cb2aaab3aa Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/intel/d510mo/Kconfig | 47 +++++++ src/mainboard/intel/d510mo/Kconfig.name | 2 + src/mainboard/intel/d510mo/Makefile.inc | 1 + src/mainboard/intel/d510mo/acpi/ec.asl | 1 + src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl | 35 ++++++ .../intel/d510mo/acpi/pineview_pci_irqs.asl | 72 +++++++++++ src/mainboard/intel/d510mo/acpi/superio.asl | 1 + src/mainboard/intel/d510mo/acpi_tables.c | 21 ++++ src/mainboard/intel/d510mo/board_info.txt | 5 + src/mainboard/intel/d510mo/cstates.c | 7 ++ src/mainboard/intel/d510mo/devicetree.cb | 94 ++++++++++++++ src/mainboard/intel/d510mo/dsdt.asl | 38 ++++++ src/mainboard/intel/d510mo/hda_verb.c | 7 ++ src/mainboard/intel/d510mo/mainboard.c | 36 ++++++ src/mainboard/intel/d510mo/romstage.c | 136 +++++++++++++++++++++ 15 files changed, 503 insertions(+) diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig new file mode 100644 index 0000000..7981f92 --- /dev/null +++ b/src/mainboard/intel/d510mo/Kconfig @@ -0,0 +1,47 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_INTEL_D510MO + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_INTEL_SOCKET_FCBGA559 + select NORTHBRIDGE_INTEL_PINEVIEW + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_WINBOND_W83627THG + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_1024 + +config MAX_CPUS + int + default 4 + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config CBFS_SIZE + hex "Size of CBFS filesystem in ROM" + default 0x100000 + +config MAINBOARD_DIR + string + default intel/d510mo + +config MAINBOARD_PART_NUMBER + string + default "D510MO" + +endif # BOARD_INTEL_D510MO diff --git a/src/mainboard/intel/d510mo/Kconfig.name b/src/mainboard/intel/d510mo/Kconfig.name new file mode 100644 index 0000000..2df0dca --- /dev/null +++ b/src/mainboard/intel/d510mo/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_D510MO + bool "D510MO" diff --git a/src/mainboard/intel/d510mo/Makefile.inc b/src/mainboard/intel/d510mo/Makefile.inc new file mode 100644 index 0000000..f9621db --- /dev/null +++ b/src/mainboard/intel/d510mo/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += cstates.c diff --git a/src/mainboard/intel/d510mo/acpi/ec.asl b/src/mainboard/intel/d510mo/acpi/ec.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl b/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..debf4b1 --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 22}, + Package() { 0x0000ffff, 1, 0, 20}, + Package() { 0x0000ffff, 2, 0, 17}, + Package() { 0x0000ffff, 3, 0, 16}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + }) +} diff --git a/src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl b/src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl new file mode 100644 index 0000000..3fa6fdb --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for pineview */ +/* FIXME: EHCI controller not working yet */ + +/* PCI Interrupt Routing */ +Method(_PRT) +{ + If (PICM) { + Return (Package() { + /* Internal GFX */ + Package() { 0x0002ffff, 0, 0, 16 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, 0, 22 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, 0, 17 }, + Package() { 0x001cffff, 1, 0, 16 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, 0, 23 }, + Package() { 0x001dffff, 1, 0, 19 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 16 }, + Package() { 0x001dffff, 0, 0, 23 }, + /* PCI 0:1e.0 */ + Package() { 0x001effff, 0, 0, 22 }, + /* LPC/SATA/SMBUS 0:1f.2, 0:1f.3 */ + Package() { 0x001fffff, 1, 0, 19 }, + Package() { 0x001fffff, 1, 0, 19 }, + Package() { 0x001fffff, 1, 0, 19 }, + }) + } Else { + Return (Package() { + /* Internal GFX */ + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + /* PCI 0:1e.0 */ + Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + /* LPC/SATA/SMBUS 0:1f.2, 0:1f.3 */ + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} diff --git a/src/mainboard/intel/d510mo/acpi/superio.asl b/src/mainboard/intel/d510mo/acpi/superio.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi/superio.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/intel/d510mo/acpi_tables.c b/src/mainboard/intel/d510mo/acpi_tables.c new file mode 100644 index 0000000..92688bf --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi_tables.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <southbridge/intel/i82801gx/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ +} diff --git a/src/mainboard/intel/d510mo/board_info.txt b/src/mainboard/intel/d510mo/board_info.txt new file mode 100644 index 0000000..192798a --- /dev/null +++ b/src/mainboard/intel/d510mo/board_info.txt @@ -0,0 +1,5 @@ +Category: desktop +Board URL: http://www.intel.com/p/en_US/support/highlights/dsktpboards/d510mo +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/intel/d510mo/cstates.c b/src/mainboard/intel/d510mo/cstates.c new file mode 100644 index 0000000..2d543ff --- /dev/null +++ b/src/mainboard/intel/d510mo/cstates.c @@ -0,0 +1,7 @@ +#include <device/device.h> +#include <arch/x86/include/arch/acpigen.h> + +int get_cst_entries(acpi_cstate_t **entries) +{ + return 0; +} diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb new file mode 100644 index 0000000..221cc54 --- /dev/null +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -0,0 +1,94 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/pineview # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_FCBGA559 # CPU + device lapic 0 on end # APIC + end + end + device domain 0 on # PCI domain + device pci 0.0 on end # Host Bridge + device pci 2.0 off end # Integrated graphics controller + chip southbridge/intel/i82801gx # Southbridge + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + register "ide_legacy_combined" = "0x1" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x0" + + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on end # PCIe 2 + device pci 1c.2 on end # PCIe 3 + device pci 1c.3 on end # PCIe 4 + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.3 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # ISA bridge + chip superio/winbond/w83627thg # Super I/O + device pnp 4e.0 off end # Floppy + device pnp 4e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 4e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + irq 0xf1 = 0 + end + device pnp 4e.5 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + irq 0xf0 = 0x80 + end + device pnp 4e.6 off end + device pnp 4e.7 off end + device pnp 4e.8 off end + device pnp 4e.9 off end + device pnp 4e.a off end # ACPI + device pnp 4e.b on # HWM + io 0x60 = 0x290 + irq 0x70 = 0 + end + end + end + device pci 1f.1 off end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMbus + device pci 1f.4 off end + device pci 1f.5 off end + device pci 1f.6 off end + end + end +end diff --git a/src/mainboard/intel/d510mo/dsdt.asl b/src/mainboard/intel/d510mo/dsdt.asl new file mode 100644 index 0000000..c1f72f9 --- /dev/null +++ b/src/mainboard/intel/d510mo/dsdt.asl @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/pineview/acpi/pineview.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/intel/d510mo/hda_verb.c b/src/mainboard/intel/d510mo/hda_verb.c new file mode 100644 index 0000000..072a306 --- /dev/null +++ b/src/mainboard/intel/d510mo/hda_verb.c @@ -0,0 +1,7 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[0] = {}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/intel/d510mo/mainboard.c b/src/mainboard/intel/d510mo/mainboard.c new file mode 100644 index 0000000..3b0ef0f --- /dev/null +++ b/src/mainboard/intel/d510mo/mainboard.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <drivers/intel/gma/i915.h> +#include <pc80/mc146818rtc.h> +#include <device/pci.h> + +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void) +{ + return NULL; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = NULL; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c new file mode 100644 index 0000000..b0bd0c0 --- /dev/null +++ b/src/mainboard/intel/d510mo/romstage.c @@ -0,0 +1,136 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stdlib.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <console/console.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <northbridge/intel/pineview/raminit.h> +#include <northbridge/intel/pineview/pineview.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <superio/winbond/w83627thg/w83627thg.h> +#include <superio/winbond/common/winbond.h> +#include <lib.h> +#include <arch/stages.h> + +#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) +#define SUPERIO_DEV PNP_DEV(0x4e, 0) + +#include <cpu/intel/romstage.h> + +/* Early mainboard specific GPIO setup */ +static void mb_gpio_init(void) +{ + device_t dev; + + /* Southbridge GPIOs. */ + dev = PCI_DEV(0x0, 0x1f, 0x0); + + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); + pci_write_config8(dev, GPIO_CNTL, 0x10); + + outl(0x1ff9f7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe0e9e803, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xece9e842, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x00002000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000000fe, DEFAULT_GPIOBASE + 0x30); + outl(0x0000007e, DEFAULT_GPIOBASE + 0x34); + outl(0x000300f3, DEFAULT_GPIOBASE + 0x38); +} + +static void nm10_enable_lpc(void) +{ + /* Disable Serial IRQ */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0x00); + /* Decode range */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, + pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x80) | 0x0010); + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, + CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN); + + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x0291); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x007c); +} + +static void rcba_config(void) +{ + /* Set up virtual channel 0 */ + RCBA32(0x0014) = 0x80000001; + RCBA32(0x001c) = 0x03128010; + + /* Device 1f interrupt pin register */ + RCBA32(0x3100) = 0x00042210; + RCBA32(0x3108) = 0x10004321; + + RCBA32(0x3104) = 0x00002100; + + /* PCIe Interrupts */ + RCBA32(0x310c) = 0x00214321; + /* HD Audio Interrupt */ + RCBA32(0x3110) = 0x00000001; + + /* dev irq route register */ + RCBA16(0x3140) = 0x0132; + RCBA16(0x3142) = 0x0146; + RCBA16(0x3144) = 0x0237; + RCBA16(0x3146) = 0x3201; + RCBA16(0x3148) = 0x0146; + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + + RCBA32(0x3418) = 0x003000e2; + RCBA32(0x3418) |= 1; +} + +void main(unsigned long bist) +{ + const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 }; + + if (bist == 0) + enable_lapic(); + + /* Disable watchdog timer */ + RCBA32(0x3410) = RCBA32(0x3410) | 0x20; + + /* Set southbridge and Super I/O GPIOs. */ + mb_gpio_init(); + + nm10_enable_lpc(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + report_bist_failure(bist); + enable_smbus(); + + pineview_early_initialization(); + + post_code(0x30); + + printk(BIOS_DEBUG, "Start native raminit\n"); + sdram_initialize(0, spd_addrmap); + printk(BIOS_DEBUG, "Native raminit done\n"); + + post_code(0x31); + ram_check(0x200000,0x300000); + + rcba_config(); +}

1 0

Patch set updated for coreboot: kconfig_lint: Fix check_is_enabled for 2 symbols on the same line
by Martin Roth 28 Nov '15

28 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12562 -gerrit commit 7d3f52d87e28c16a1e46b236e51a5a437ee105fc Author: Martin Roth <martinroth(a)google.com> Date: Fri Nov 27 18:51:19 2015 -0700 kconfig_lint: Fix check_is_enabled for 2 symbols on the same line The previous code would miss the first of two IS_ENABLED(CONFIG_symbol) sequences on a line. This patch saves the rest of the line and loops to check any other entries on the same line of text. Change-Id: If4e66d5b393cc5703a502887e18f0ac11adff012 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/kconfig_lint | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index 9bad31e..d88caa9 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -191,25 +191,31 @@ sub check_for_def { # this seems like a bad plan. Using it on strings is dead out. #------------------------------------------------------------------------------- sub check_is_enabled { - my @is_enabled_symbols = `grep -Grn 'IS_ENABLED\\s*(\\s*CONFIG_' -- "$root_dir"`; + my @is_enabled_symbols = @collected_symbols; #sort through symbols found by grep and store them in a hash for easy access while ( my $line = shift @is_enabled_symbols ) { - if ( $line =~ /^([^:]+):(\d+):.+IS_ENABLED\s*\(\s*CONFIG_(\w+)/ ) { + if ( $line =~ /^([^:]+):(\d+):(.+IS_ENABLED.*)/ ) { my $file = $1; my $lineno = $2; - my $symbol = $3; - - #make sure that - if (exists $symbols{$symbol}) { - if ($symbols{$symbol}{type} ne "bool") { - show_error("IS_ENABLED(CONFIG_$symbol) used in $file at line $lineno. IS_ENABLED is only valid for type 'bool', not '$symbols{$symbol}{type}'."); + $line = $3; + if ( $line !~ /(.*)IS_ENABLED\s*\(\s*CONFIG_(\w+)(.*)/ ){ + show_warning("# uninterpreted IS_ENABLED at $file:$lineno: $line"); + next; + } + while ( $line =~ /(.*)IS_ENABLED\s*\(\s*CONFIG_(\w+)(.*)/ ) { + my $symbol = $2; + $line = $1.$3; + + #make sure that + if (exists $symbols{$symbol}) { + if ($symbols{$symbol}{type} ne "bool") { + show_error("IS_ENABLED(CONFIG_$symbol) used at $file:$lineno. IS_ENABLED is only valid for type 'bool', not '$symbols{$symbol}{type}'."); + } + } else { + show_error("IS_ENABLED() used on unknown value CONFIG_$symbol at $file:$lineno."); } - } else { - show_error("IS_ENABLED() used on unknown value CONFIG_$symbol in $file at line $lineno."); } - } else { - show_error("# uninterpreted IS_ENABLED line: $line"); } } }

1 0

New patch to review for coreboot: ati/ragexl: Change #defines named CONFIG_ to CFG_
by Martin Roth 28 Nov '15

28 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12564 -gerrit commit 729f6d7746b46c59a92125708126fdad84583925 Author: Martin Roth <martinroth(a)google.com> Date: Fri Nov 27 19:36:05 2015 -0700 ati/ragexl: Change #defines named CONFIG_ to CFG_ The CONFIG_ prefix should be reserved for Kconfig symbols. Change-Id: I1d3141e0f5f9e1161bc7f88158af8a5d5780829c Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/drivers/ati/ragexl/mach64.h | 24 +++++++++--------- src/drivers/ati/ragexl/xlinit.c | 56 ++++++++++++++++++++--------------------- 2 files changed, 40 insertions(+), 40 deletions(-) diff --git a/src/drivers/ati/ragexl/mach64.h b/src/drivers/ati/ragexl/mach64.h index 3acbef4..354ae2b 100644 --- a/src/drivers/ati/ragexl/mach64.h +++ b/src/drivers/ati/ragexl/mach64.h @@ -101,7 +101,7 @@ #define CUR_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */ #define CUR2_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */ -#define CONFIG_PANEL_LG 0x0074 /* Dword offset 0_1D */ +#define CFG_PANEL_LG 0x0074 /* Dword offset 0_1D */ /* General I/O Control */ #define GP_IO 0x0078 /* Dword offset 0_1E */ @@ -120,8 +120,8 @@ #define CLOCK_SEL_CNTL 0x0090 /* Dword offset 0_24 */ /* Configuration */ -#define CONFIG_STAT1 0x0094 /* Dword offset 0_25 */ -#define CONFIG_STAT2 0x0098 /* Dword offset 0_26 */ +#define CFG_STAT1 0x0094 /* Dword offset 0_25 */ +#define CFG_STAT2 0x0098 /* Dword offset 0_26 */ /* Bus Control */ #define BUS_CNTL 0x00A0 /* Dword offset 0_28 */ @@ -158,9 +158,9 @@ #define POWER_MANAGEMENT_LG 0x00D8 /* Dword offset 0_36 (LG) */ /* Configuration */ -#define CONFIG_CNTL 0x00DC /* Dword offset 0_37 (CT, ET, VT) */ -#define CONFIG_CHIP_ID 0x00E0 /* Dword offset 0_38 */ -#define CONFIG_STAT0 0x00E4 /* Dword offset 0_39 */ +#define CFG_CNTL 0x00DC /* Dword offset 0_37 (CT, ET, VT) */ +#define CFG_CHIP_ID 0x00E0 /* Dword offset 0_38 */ +#define CFG_STAT0 0x00E4 /* Dword offset 0_39 */ /* Test and Debug */ #define CRC_SIG 0x00E8 /* Dword offset 0_3A */ @@ -726,17 +726,17 @@ #define VCLK2_POST 0x30 #define VCLK3_POST 0xC0 -/* CONFIG_CNTL register constants */ +/* CFG_CNTL register constants */ #define APERTURE_4M_ENABLE 1 #define APERTURE_8M_ENABLE 2 #define VGA_APERTURE_ENABLE 4 -/* CONFIG_STAT0 register constants (GX, CX) */ +/* CFG_STAT0 register constants (GX, CX) */ #define CFG_BUS_TYPE 0x00000007 #define CFG_MEM_TYPE 0x00000038 #define CFG_INIT_DAC_TYPE 0x00000e00 -/* CONFIG_STAT0 register constants (CT, ET, VT) */ +/* CFG_STAT0 register constants (CT, ET, VT) */ #define CFG_MEM_TYPE_xT 0x00000007 #define ISA 0 @@ -815,7 +815,7 @@ #define PCI_ATI_VENDOR_ID 0x1002 -/* CONFIG_CHIP_ID register constants */ +/* CFG_CHIP_ID register constants */ #define CFG_CHIP_TYPE 0x0000FFFF #define CFG_CHIP_CLASS 0x00FF0000 #define CFG_CHIP_REV 0xFF000000 @@ -824,7 +824,7 @@ #define CFG_CHIP_MINOR 0xC0000000 -/* Chip IDs read from CONFIG_CHIP_ID */ +/* Chip IDs read from CFG_CHIP_ID */ /* mach64GX family */ #define GX_CHIP_ID 0xD7 /* mach64GX (ATI888GX00) */ @@ -1113,7 +1113,7 @@ #define CRTC2_DISPLAY_DIS 0x00000400 /* LCD register indices */ -#define CONFIG_PANEL 0x00 +#define CFG_PANEL 0x00 #define LCD_GEN_CTRL 0x01 #define DSTN_CONTROL 0x02 #define HFB_PITCH_ADDR 0x03 diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c index 1929180..0996e7d 100644 --- a/src/drivers/ati/ragexl/xlinit.c +++ b/src/drivers/ati/ragexl/xlinit.c @@ -26,9 +26,9 @@ // fixed to export a framebuffer console through the coreboot // table (and possibly make it available for bootsplash use) // Hence do only remove this if you fix the code. -#define CONFIG_CONSOLE_BTEXT 0 +#define CFG_CONSOLE_BTEXT 0 -#if CONFIG_CONSOLE_BTEXT +#if CFG_CONSOLE_BTEXT #define PLL_CRTC_DECODE 0 #define SUPPORT_8_BPP_ABOVE 0 @@ -46,7 +46,7 @@ struct aty_cmap_regs { #include <console/btext.h> -#endif /*CONFIG_CONSOLE_BTEXT*/ +#endif /*CFG_CONSOLE_BTEXT*/ #include "mach64.h" @@ -210,7 +210,7 @@ static int atyfb_xl_init(struct fb_info_aty *info) union aty_pll pll; const struct xl_card_cfg_t * card = &card_cfg[xl_card]; - aty_st_8(CONFIG_STAT0, 0x85, info); + aty_st_8(CFG_STAT0, 0x85, info); mdelay(10); /* @@ -269,7 +269,7 @@ static int atyfb_xl_init(struct fb_info_aty *info) aty_st_le32(BUS_CNTL, card->bus_cntl | 0x08000000, info); aty_st_le32(CRTC_GEN_CNTL, 0x04000200, info); - aty_st_le16(CONFIG_STAT0, 0x0020, info); + aty_st_le16(CFG_STAT0, 0x0020, info); aty_st_le32(MEM_CNTL, 0x10151A33, info); aty_st_le32(EXT_MEM_CNTL, 0xE0000C01, info); aty_st_le16(CRTC_GEN_CNTL+2, 0x0000, info); @@ -292,7 +292,7 @@ static int atyfb_xl_init(struct fb_info_aty *info) aty_st_lcd(lcd_tbl[i].lcd_reg, lcd_tbl[i].val, info); } - aty_st_le16(CONFIG_STAT0, 0x00A4, info); + aty_st_le16(CFG_STAT0, 0x00A4, info); mdelay(10); aty_st_8(BUS_CNTL+1, 0xA0, info); @@ -330,7 +330,7 @@ static int atyfb_xl_init(struct fb_info_aty *info) aty_st_le32(MEM_CNTL, card->mem_cntl, info); aty_st_le32(EXT_MEM_CNTL, card->ext_mem_cntl, info); - aty_st_8(CONFIG_STAT0, 0xA0 | card->mem_type, info); + aty_st_8(CFG_STAT0, 0xA0 | card->mem_type, info); aty_st_pll(PLL_YCLK_CNTL, 0x01, info); mdelay(15); @@ -348,12 +348,12 @@ static int atyfb_xl_init(struct fb_info_aty *info) // disable extended register block aty_st_8(BUS_CNTL+3, 0x73, info); - aty_st_8(CONFIG_STAT0, 0x80 | card->mem_type, info); + aty_st_8(CFG_STAT0, 0x80 | card->mem_type, info); // disable display requests, disable CRTC aty_st_8(CRTC_GEN_CNTL+3, 0x04, info); // disable mapping registers in VGA aperture - aty_st_8(CONFIG_CNTL, aty_ld_8(CONFIG_CNTL, info) & ~0x04, info); + aty_st_8(CFG_CNTL, aty_ld_8(CFG_CNTL, info) & ~0x04, info); mdelay(50); // enable display requests, enable CRTC aty_st_8(CRTC_GEN_CNTL+3, 0x02, info); @@ -393,7 +393,7 @@ static char m64n_xl_33[] = "3D RAGE (XL PCI-33MHz)"; static char m64n_xl_66[] = "3D RAGE (XL PCI-66MHz)"; -#if CONFIG_CONSOLE_BTEXT +#if CFG_CONSOLE_BTEXT static void aty_set_crtc(const struct fb_info_aty *info, const struct crtc *crtc); static int aty_var_to_crtc(const struct fb_info_aty *info, @@ -441,7 +441,7 @@ struct fb_var_screeninfo default_var = { 0, FB_VMODE_NONINTERLACED }; -#endif /*CONFIG_CONSOLE_BTEXT*/ +#endif /*CFG_CONSOLE_BTEXT*/ static struct { u16 pci_id, chip_type; @@ -455,7 +455,7 @@ static struct { /* 3D RAGE XL PCI-33/BGA */ { 0x4752, 0x4752, 0x00, 0x00, m64n_xl_33, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 }, }; -#if CONFIG_CONSOLE_BTEXT +#if CFG_CONSOLE_BTEXT static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk) { int i, size; @@ -488,7 +488,7 @@ static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk) info->mem_refresh_rate = i; } -#endif /*CONFIG_CONSOLE_BTEXT */ +#endif /*CFG_CONSOLE_BTEXT */ static void ati_ragexl_init(struct device *dev) { u32 chip_id; @@ -496,13 +496,13 @@ static void ati_ragexl_init(struct device *dev) u16 type; u8 rev; const char *chipname = NULL; -#if CONFIG_CONSOLE_BTEXT +#if CFG_CONSOLE_BTEXT u32 i; const char *xtal; #endif int pll, mclk, xclk; -#if CONFIG_CONSOLE_BTEXT +#if CFG_CONSOLE_BTEXT #if 0 int gtb_memsize, k; @@ -517,7 +517,7 @@ static void ati_ragexl_init(struct device *dev) u8 pll_ref_div; #endif -#endif /*CONFIG_CONSOLE_BTEXT==1 */ +#endif /*CFG_CONSOLE_BTEXT==1 */ struct fb_info_aty *info; struct fb_info_aty info_t; @@ -532,9 +532,9 @@ static void ati_ragexl_init(struct device *dev) res = res->next; } -#if CONFIG_CONSOLE_BTEXT +#if CFG_CONSOLE_BTEXT info->frame_buffer = res->base; -#endif /* CONFIG_CONSOLE_BTEXT */ +#endif /* CFG_CONSOLE_BTEXT */ #if USE_AUX_REG==0 info->ati_regbase = res2mmio(res, 0x7ff000+0xc00, 0); @@ -548,7 +548,7 @@ static void ati_ragexl_init(struct device *dev) #endif -#if CONFIG_CONSOLE_BTEXT +#if CFG_CONSOLE_BTEXT info->aty_cmap_regs = (struct aty_cmap_regs *)(info->ati_regbase+0xc0); #endif @@ -556,7 +556,7 @@ static void ati_ragexl_init(struct device *dev) printk(BIOS_DEBUG, "ati_regbase = 0x%p, frame_buffer = 0x%08x\n", info->ati_regbase, info->frame_buffer); #endif - chip_id = aty_ld_le32(CONFIG_CHIP_ID, info); + chip_id = aty_ld_le32(CFG_CHIP_ID, info); type = chip_id & CFG_CHIP_TYPE; rev = (chip_id & CFG_CHIP_REV)>>24; for (j = 0; j < ARRAY_SIZE(aty_chips); j++) @@ -581,9 +581,9 @@ found: mclk = 63; } #endif -#if CONFIG_CONSOLE_BTEXT +#if CFG_CONSOLE_BTEXT aty_calc_mem_refresh(info, type, xclk); -#endif /* CONFIG_CONSOLE_BTEXT */ +#endif /* CFG_CONSOLE_BTEXT */ info->pll_per = 1000000/pll; info->mclk_per = 1000000/mclk; @@ -596,9 +596,9 @@ found: atyfb_xl_init(info); -#if CONFIG_CONSOLE_BTEXT +#if CFG_CONSOLE_BTEXT - info->ram_type = (aty_ld_le32(CONFIG_STAT0, info) & 0x07); + info->ram_type = (aty_ld_le32(CFG_STAT0, info) & 0x07); info->ref_clk_per = 1000000000000ULL/14318180; xtal = "14.31818"; @@ -672,7 +672,7 @@ found: #endif if (M64_HAS(MAGIC_VRAM_SIZE)) { - if (aty_ld_le32(CONFIG_STAT1, info) & 0x40000000) + if (aty_ld_le32(CFG_STAT1, info) & 0x40000000) info->total_vram += 0x400000; } #if 0 @@ -799,11 +799,11 @@ found: // test end #endif -#endif /* CONFIG_CONSOLE_BTEXT */ +#endif /* CFG_CONSOLE_BTEXT */ } -#if CONFIG_CONSOLE_BTEXT +#if CFG_CONSOLE_BTEXT static int atyfb_decode_var(const struct fb_var_screeninfo *var, struct atyfb_par *par, @@ -1501,7 +1501,7 @@ static void do_install_cmap(int con, struct fb_info_aty *info) fb_set_cmap(fb_default_cmap(size), 1, atyfb_setcolreg, info); } -#endif /*CONFIG_CONSOLE_BTEXT */ +#endif /*CFG_CONSOLE_BTEXT */ static struct device_operations ati_ragexl_graph_ops = { .read_resources = pci_dev_read_resources,

1 0

New patch to review for coreboot: bachmann/ot200: Remove DRIVERS_I2C_IDREG Kconfig symbol
by Martin Roth 28 Nov '15

28 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12563 -gerrit commit 81841fb37cce4871ae706161675c65ea785687ba Author: Martin Roth <martinroth(a)google.com> Date: Fri Nov 27 19:04:42 2015 -0700 bachmann/ot200: Remove DRIVERS_I2C_IDREG Kconfig symbol As far as I can tell the Kconfig symbol DRIVERS_I2C_IDREG never actually existed in the coreboot codebase. I didn't see anything that it might have been a typo of. Change-Id: Ib17de670e38e07ab4a4745143c42fa85da1754e1 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/bachmann/ot200/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/bachmann/ot200/Kconfig b/src/mainboard/bachmann/ot200/Kconfig index baef807..3ca0384 100644 --- a/src/mainboard/bachmann/ot200/Kconfig +++ b/src/mainboard/bachmann/ot200/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select BOARD_ROMSIZE_KB_2048 select POWER_BUTTON_DEFAULT_DISABLE - select DRIVERS_I2C_IDREG select PLL_MANUAL_CONFIG select CORE_GLIU_500_266 select HAVE_OPTION_TABLE

1 0

Patch set updated for coreboot: kconfig_lint: Fix check_is_enabled for 2 symbols on the same line
by Martin Roth 28 Nov '15

28 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12562 -gerrit commit f61f5dc32513573eba007a2cb77d5f91220e3166 Author: Martin Roth <martinroth(a)google.com> Date: Fri Nov 27 18:51:19 2015 -0700 kconfig_lint: Fix check_is_enabled for 2 symbols on the same line The previous code would miss the first of two IS_ENABLED(CONFIG_symbol) sequences on a line. This patch saves the rest of the line and loops to check any other entries on the same line of text. Change-Id: If4e66d5b393cc5703a502887e18f0ac11adff012 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/kconfig_lint | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index 9bad31e..c99a4c9 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -191,25 +191,31 @@ sub check_for_def { # this seems like a bad plan. Using it on strings is dead out. #------------------------------------------------------------------------------- sub check_is_enabled { - my @is_enabled_symbols = `grep -Grn 'IS_ENABLED\\s*(\\s*CONFIG_' -- "$root_dir"`; + my @is_enabled_symbols = @collected_symbols; #sort through symbols found by grep and store them in a hash for easy access while ( my $line = shift @is_enabled_symbols ) { - if ( $line =~ /^([^:]+):(\d+):.+IS_ENABLED\s*\(\s*CONFIG_(\w+)/ ) { + if ( $line =~ /^([^:]+):(\d+):(.+IS_ENABLED.*)/ ) { my $file = $1; my $lineno = $2; - my $symbol = $3; - - #make sure that - if (exists $symbols{$symbol}) { - if ($symbols{$symbol}{type} ne "bool") { - show_error("IS_ENABLED(CONFIG_$symbol) used in $file at line $lineno. IS_ENABLED is only valid for type 'bool', not '$symbols{$symbol}{type}'."); - } - } else { - show_error("IS_ENABLED() used on unknown value CONFIG_$symbol in $file at line $lineno."); + $line = $3; + if ( $line !~ /(.*)IS_ENABLED\s*\(\s*CONFIG_(\w+)(.*)/ ){ + show_warning("# uninterpreted IS_ENABLED at $file:$lineno: $line"); + next; } - } else { - show_error("# uninterpreted IS_ENABLED line: $line"); + while ( $line =~ /(.*)IS_ENABLED\s*\(\s*CONFIG_(\w+)(.*)/ ) { + my $symbol = $2; + $line = $1.$3; + + #make sure that + if (exists $symbols{$symbol}) { + if ($symbols{$symbol}{type} ne "bool") { + show_error("IS_ENABLED(CONFIG_$symbol) used at $file:$lineno. IS_ENABLED is only valid for type 'bool', not '$symbols{$symbol}{type}'."); + } + } else { + show_error("IS_ENABLED() used on unknown value CONFIG_$symbol at $file:$lineno."); + } + } } } }

1 0

New patch to review for coreboot: kconfig_line: Fix check_is_enabled for 2 symbols on the same line
by Martin Roth 28 Nov '15

28 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12562 -gerrit commit 372e46c4c4a838252c79e98bf7ed9aa973e6618f Author: Martin Roth <martinroth(a)google.com> Date: Fri Nov 27 18:51:19 2015 -0700 kconfig_line: Fix check_is_enabled for 2 symbols on the same line The previous code would miss the first of two IS_ENABLED(CONFIG_symbol) sequences on a line. This patch saves the rest of the line and loops to check any other entries on the same line of text. Change-Id: If4e66d5b393cc5703a502887e18f0ac11adff012 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/kconfig_lint | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index 9bad31e..c99a4c9 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -191,25 +191,31 @@ sub check_for_def { # this seems like a bad plan. Using it on strings is dead out. #------------------------------------------------------------------------------- sub check_is_enabled { - my @is_enabled_symbols = `grep -Grn 'IS_ENABLED\\s*(\\s*CONFIG_' -- "$root_dir"`; + my @is_enabled_symbols = @collected_symbols; #sort through symbols found by grep and store them in a hash for easy access while ( my $line = shift @is_enabled_symbols ) { - if ( $line =~ /^([^:]+):(\d+):.+IS_ENABLED\s*\(\s*CONFIG_(\w+)/ ) { + if ( $line =~ /^([^:]+):(\d+):(.+IS_ENABLED.*)/ ) { my $file = $1; my $lineno = $2; - my $symbol = $3; - - #make sure that - if (exists $symbols{$symbol}) { - if ($symbols{$symbol}{type} ne "bool") { - show_error("IS_ENABLED(CONFIG_$symbol) used in $file at line $lineno. IS_ENABLED is only valid for type 'bool', not '$symbols{$symbol}{type}'."); - } - } else { - show_error("IS_ENABLED() used on unknown value CONFIG_$symbol in $file at line $lineno."); + $line = $3; + if ( $line !~ /(.*)IS_ENABLED\s*\(\s*CONFIG_(\w+)(.*)/ ){ + show_warning("# uninterpreted IS_ENABLED at $file:$lineno: $line"); + next; } - } else { - show_error("# uninterpreted IS_ENABLED line: $line"); + while ( $line =~ /(.*)IS_ENABLED\s*\(\s*CONFIG_(\w+)(.*)/ ) { + my $symbol = $2; + $line = $1.$3; + + #make sure that + if (exists $symbols{$symbol}) { + if ($symbols{$symbol}{type} ne "bool") { + show_error("IS_ENABLED(CONFIG_$symbol) used at $file:$lineno. IS_ENABLED is only valid for type 'bool', not '$symbols{$symbol}{type}'."); + } + } else { + show_error("IS_ENABLED() used on unknown value CONFIG_$symbol at $file:$lineno."); + } + } } } }

1 0

← Newer
1
...
8
9
10
11
12
13
14
...
155
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2015