coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

1 participants
1544 discussions

New patch to review for coreboot: fsp_baytrail: Remove use of BAYTRAIL_SMM, which has been removed
by Martin Roth 27 Nov '15

27 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12553 -gerrit commit 3762ee0c055fee814058541c254a4cf54b6b0ffc Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 26 17:46:45 2015 -0700 fsp_baytrail: Remove use of BAYTRAIL_SMM, which has been removed The symbol BAYTRAIL_SMM is no longer valid (there's no config statment initializing the symbol), but it was still being selected and used in the code. Just set up to use SMM. Change-Id: I0fd4865a951734e728500e7baf593ff7eb556f73 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/soc/intel/fsp_baytrail/Kconfig | 1 - src/soc/intel/fsp_baytrail/acpi.c | 10 +--------- 2 files changed, 1 insertion(+), 10 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 2325d75..506e731 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -35,7 +35,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP select REG_SCRIPT select SMM_TSEG - select BAYTRAIL_SMM select SMP select SPI_FLASH select SSE2 diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 5a5b880..1eaebad 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -208,18 +208,10 @@ void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) /* System Management */ fadt->sci_int = acpi_sci_irq(); -#if IS_ENABLED(CONFIG_BAYTRAIL_SMM) + fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; fadt->acpi_disable = APM_CNT_ACPI_DISABLE; -#else - fadt->smi_cmd = 0x00; /* disable SMM */ - fadt->acpi_enable = 0x00; /* unused if SMI_CMD = 0 */ - fadt->acpi_disable = 0x00; /* unused if SMI_CMD = 0 */ - - /* Enable ACPI */ - outl(inl(pmbase + 4) | 0x01, pmbase + 4); -#endif /* Power Control */ fadt->s4bios_req = 0x00;

1 0

Patch merged into coreboot/master: util/kconfig: Remove utsname for mingw
by gerrit＠coreboot.org 26 Nov '15

26 Nov '15

the following patch was just integrated into master: commit d38b22f8ec547296e569964279362f13c1ee598c Author: zbao <fishbaozi(a)gmail.com> Date: Sat Sep 26 06:22:11 2015 -0400 util/kconfig: Remove utsname for mingw Mingw doesn't have that this function. Change-Id: I640ea61ff24fba812e3f10771dd7e468dcfc63dd Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/11724 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/11724 for details. -gerrit

1 0

New patch to review for coreboot: intel/fsp_rangeley: change non-existent config options to #defines
by Martin Roth 26 Nov '15

26 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12552 -gerrit commit 789bc8b4c5bcd5016f5ea06417affb86b7837425 Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 26 15:58:12 2015 -0700 intel/fsp_rangeley: change non-existent config options to #defines The Kconfig symbols ONFIG_ACPI_INCLUDE_PMIO and CONFIG_ACPI_INCLUDE_GPIO were never added to the coreboot codebase when the Rangeley code was brought in from Sage. These symbols disabled ACPI code that was unused because it caused dmesg warnings due to conflicts with drivers trying to claim the same addresses as the ACPI code. Because it could be used on some other platforms, it was left in instead of being completely removed. - Change the Kconfig symbol names to simple #defines in the mainboard code. - Add the #defines along with comments to the reference platform. - Hook everything together in dsdt.asl Change-Id: I1f62157c6e447ea9b7207699572930e4711fc3e0 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/intel/mohonpeak/acpi/mainboard.asl | 3 +++ src/mainboard/intel/mohonpeak/dsdt.asl | 4 ++++ src/southbridge/intel/fsp_rangeley/acpi/soc.asl | 4 ++-- 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/mohonpeak/acpi/mainboard.asl b/src/mainboard/intel/mohonpeak/acpi/mainboard.asl index c43d2db..aecc2b6 100644 --- a/src/mainboard/intel/mohonpeak/acpi/mainboard.asl +++ b/src/mainboard/intel/mohonpeak/acpi/mainboard.asl @@ -14,6 +14,9 @@ * GNU General Public License for more details. */ +// #define ACPI_INCLUDE_PMIO 1 /* uncomment to enable PMIO block in soc.asl */ +// #define ACPI_INCLUDE_GPIO 1 /* uncomment to enable GPIO block in soc.asl */ + Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) diff --git a/src/mainboard/intel/mohonpeak/dsdt.asl b/src/mainboard/intel/mohonpeak/dsdt.asl index dbb8b15..4e5b9ce 100644 --- a/src/mainboard/intel/mohonpeak/dsdt.asl +++ b/src/mainboard/intel/mohonpeak/dsdt.asl @@ -23,6 +23,10 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + + // Include mainboard configuration + #include <acpi/mainboard.asl> + // Include debug methods #include <arch/x86/acpi/debug.asl> diff --git a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl index 22edf50..696a81a 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi/soc.asl +++ b/src/southbridge/intel/fsp_rangeley/acpi/soc.asl @@ -30,7 +30,7 @@ Scope(\) TRP0, 8 // IO-Trap at 0x808 } -#if IS_ENABLED(CONFIG_ACPI_INCLUDE_PMIO) +#ifdef ACPI_INCLUDE_PMIO // PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l) OperationRegion(PMIO, SystemIO, DEFAULT_ABASE, 0x80) Field(PMIO, ByteAcc, NoLock, Preserve) @@ -77,7 +77,7 @@ Scope(\) } #endif -#if IS_ENABLED(CONFIG_ACPI_INCLUDE_GPIO) +#ifdef ACPI_INCLUDE_GPIO // GPIO IO mapped registers (0x1f.0 reg 0x48.l) OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c) Field(GPIO, ByteAcc, NoLock, Preserve)

1 0

Patch merged into coreboot/master: cbfstool: Add .SILENT: to Makefile
by gerrit＠coreboot.org 26 Nov '15

26 Nov '15

the following patch was just integrated into master: commit 30ff36249cd9e696f90050515f592991a20f331a Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Nov 21 17:53:32 2015 +0100 cbfstool: Add .SILENT: to Makefile This makes the make process look like the one inside of coreboot's build system. Change-Id: I48be2df39cad47644e16ce583b27c33a1da81fc3 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/12509 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/12509 for details. -gerrit

1 0

Patch merged into coreboot/master: amd/car: don't apply Fam10h/Fam12h Errata 343 fix to Fam0Fh
by gerrit＠coreboot.org 26 Nov '15

26 Nov '15

the following patch was just integrated into master: commit 20d9fb46926c7152c4bcb9546bd1ab5d6e261ca8 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Tue Nov 24 10:15:22 2015 -0600 amd/car: don't apply Fam10h/Fam12h Errata 343 fix to Fam0Fh Fixes early fault problem on Fam0Fh introduced in Change I8e01a4ab68b463efe02c27f589e0b4b719532eb5, commit 991f18475c951dcd728eb8550b10dd62938b1770. Change-Id: Id215d2822b78917939c28f7a922a94e02e5d15bf Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Reviewed-on: https://review.coreboot.org/12528 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> See https://review.coreboot.org/12528 for details. -gerrit

1 0

Patch set updated for coreboot: cpu/amd/family_10h-family_15h: Apply missing Family 15h errata fixes
by Timothy Pearson 26 Nov '15

26 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12065 -gerrit commit 9ff438de45125050032dfd8b60221cdfb252a6d5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Sep 3 17:43:52 2015 -0500 cpu/amd/family_10h-family_15h: Apply missing Family 15h errata fixes Change-Id: I132874fe5b5a8b9a87422e2f07bff03bc5863ca4 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/defaults.h | 12 ++++++++++++ src/northbridge/amd/amdfam10/misc_control.c | 6 ++++++ 2 files changed, 18 insertions(+) diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h index 7fd115c..f708d16 100644 --- a/src/cpu/amd/family_10h-family_15h/defaults.h +++ b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -162,6 +162,14 @@ static const struct { 0x0000000C, 0x00000000, 0x0000000C, 0x00000000}, /* Cx and Dx multiple-link processor */ + { OSVW_ID_Length, AMD_FAM15_ALL, AMD_PTYPE_ALL, + 0x00000005, 0x00000000, + 0x00000005, 0x00000000}, /* OSVW_ID_Length = 0x5 */ + + { OSVW_Status, AMD_FAM15_ALL, AMD_PTYPE_ALL, + 0x00000010, 0x00000000, + 0x00000010, 0x00000000}, /* OsvwId4 = 0x1 */ + { BU_CFG2, AMD_DR_Dx, AMD_PTYPE_ALL, 0x00000000, 1 << (50-32), 0x00000000, 1 << (50-32)}, /* D0 or Above, RdMmExtCfgQwEn*/ @@ -621,6 +629,10 @@ static const struct { { 3, 0x1b8, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, 0x00001000, 0x00001000 }, /* [12] = L3PrivReplEn */ + /* Errata 504 workaround */ + { 3, 0x1b8, AMD_FAM15_ALL, AMD_PTYPE_ALL, + 0x00040000, 0x00040000 }, /* [18] = 1b */ + /* IBS Control Register */ { 3, 0x1cc, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL, 0x00000100, 0x00000100 }, /* [8] = LvtOffsetVal */ diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 0b312b1..4c65bca 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -75,6 +75,7 @@ static void mcf3_read_resources(device_t dev) static void set_agp_aperture(device_t dev, uint32_t pci_id) { + uint32_t dword; struct resource *resource; resource = probe_resource(dev, 0x94); @@ -105,6 +106,11 @@ static void set_agp_aperture(device_t dev, uint32_t pci_id) /* Report the resource has been stored... */ report_resource_stored(pdev, resource, " <gart>"); + + /* Errata 540 workaround */ + dword = pci_read_config32(pdev, 0x90); + dword |= 0x1 << 6; /* DisGartTblWlkPrb = 0x1 */ + pci_write_config32(pdev, 0x90, dword); } } }

1 0

Patch set updated for coreboot: southbridge/amd/sr5650: Add MCFG ACPI table support
by Timothy Pearson 26 Nov '15

26 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12050 -gerrit commit e3ddc4847b0a6a54df3f985780a7877aecd47505 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Aug 14 15:20:42 2015 -0500 southbridge/amd/sr5650: Add MCFG ACPI table support Change-Id: I0c4ba74ddcc727cd92b848d5d3240e6f9f392101 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 22 +++--- src/southbridge/amd/rs780/rs780.c | 12 ++++ src/southbridge/amd/sb700/lpc.c | 6 -- src/southbridge/amd/sb800/lpc.c | 7 +- src/southbridge/amd/sr5650/Kconfig | 9 +++ src/southbridge/amd/sr5650/ht.c | 107 ++++++++++++++++++++++++++++- src/southbridge/amd/sr5650/sr5650.c | 18 +++++ 7 files changed, 156 insertions(+), 25 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 85cee13..3177a5f 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -740,16 +740,18 @@ static void amdfam10_domain_read_resources(device_t dev) pci_domain_read_resources(dev); -#if CONFIG_MMCONF_SUPPORT - struct resource *res = new_resource(dev, 0xc0010058); - res->base = CONFIG_MMCONF_BASE_ADDRESS; - res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; - res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ - ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); -#endif + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT) && !IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + struct resource *res = new_resource(dev, 0xc0010058); + res->base = CONFIG_MMCONF_BASE_ADDRESS; + res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; + res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + } + + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) { + /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ + ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); + } if (is_fam15h()) { enable_cc6 = 0; diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index c82a629..6eb4295 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -15,6 +15,7 @@ #include <console/console.h> #include <arch/io.h> +#include <arch/acpi.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -349,6 +350,17 @@ void rs780_enable(device_t dev) } } +#if !IS_ENABLED(CONFIG_AMD_SB_CIMX) +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* FIXME + * Leave table blank until proper contents + * are determined. + */ + return current; +} +#endif + struct chip_operations southbridge_amd_rs780_ops = { CHIP_NAME("ATI RS780") .enable_dev = rs780_enable, diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index a71fe1f..78933fa 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -30,12 +30,6 @@ #include <cpu/amd/powernow.h> #include "sb700.h" -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - static void lpc_init(device_t dev) { u8 byte; diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 756a0c4..18d4471 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,12 +26,6 @@ #include <arch/acpi.h> #include "sb800.h" -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - static void lpc_init(device_t dev) { u8 byte; diff --git a/src/southbridge/amd/sr5650/Kconfig b/src/southbridge/amd/sr5650/Kconfig index 29017c6..f2d12ff 100644 --- a/src/southbridge/amd/sr5650/Kconfig +++ b/src/southbridge/amd/sr5650/Kconfig @@ -15,3 +15,12 @@ config SOUTHBRIDGE_AMD_SR5650 bool + +if SOUTHBRIDGE_AMD_SR5650 +config EXT_CONF_SUPPORT + bool "Enable PCI-E MMCONFIG support" + default n + help + Select to enable PCI-E MMCONFIG support on the SR5650. + +endif diff --git a/src/southbridge/amd/sr5650/ht.c b/src/southbridge/amd/sr5650/ht.c index 6119985..e74d36b 100644 --- a/src/southbridge/amd/sr5650/ht.c +++ b/src/southbridge/amd/sr5650/ht.c @@ -20,7 +20,9 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <arch/ioapic.h> +#include <lib.h> #include "sr5650.h" +#include "cmn.h" /* Table 6-6 Recommended Interrupt Routing Configuration */ typedef struct _apic_device_info { @@ -154,11 +156,29 @@ static void pcie_init(struct device *dev) static void sr5690_read_resource(struct device *dev) { + struct resource *res; + + if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + printk(BIOS_DEBUG,"%s: %s\n", __func__, dev_path(dev)); + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); /* Hide BAR3 */ + } + pci_dev_read_resources(dev); /* rpr6.2.(1). Write the Base Address Register (BAR) */ - pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ - pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */ + pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */ + pci_get_resource(dev, 0xfc); /* APIC located in sr5690 */ + + if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + res = new_resource(dev, 0x1c); /* PCIe MCFG space */ + res->base = EXT_CONF_BASE_ADDRESS; + res->size = CONFIG_MMCONF_BUS_NUMBER * 1024 * 1024; /* Each bus needs 1M */ + res->align = log2(res->size); + res->gran = log2(res->size); + res->limit = 0xffffffffffffffffULL; /* 64-bit location allowed */ + res->flags = IORESOURCE_FIXED | IORESOURCE_MEM | IORESOURCE_PCI64 + | IORESOURCE_ASSIGNED | IORESOURCE_RESERVE | IORESOURCE_BRIDGE; + } compact_resources(dev); } @@ -166,7 +186,88 @@ static void sr5690_read_resource(struct device *dev) /* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */ static void sr5690_set_resources(struct device *dev) { - pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */ + + if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + uint32_t reg; + device_t amd_ht_cfg_dev; + device_t amd_addr_map_dev; + resource_t res_base; + resource_t res_end; + uint32_t base; + uint32_t limit; + struct resource *res; + + printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__); + + res = probe_resource(dev, 0x1c); + if (res) { + /* Find requisite AMD CPU devices */ + amd_ht_cfg_dev = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + amd_addr_map_dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + + if (!amd_ht_cfg_dev || !amd_addr_map_dev) { + printk(BIOS_WARNING, "%s: %s Unable to locate CPU control devices\n", __func__, dev_path(dev)); + } + else { + /* Set up MMCONFIG bus range */ + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 0 << 3); /* Make BAR3 visible */ + set_nbcfg_enable_bits(dev, 0x7c, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register */ + set_nbcfg_enable_bits(dev, 0x84, 7 << 16, 0 << 16); /* Program bus range = 255 busses */ + pci_write_config32(dev, 0x1c, res->base); + + /* Enable MMCONFIG decoding. */ + set_htiu_enable_bits(dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */ + set_nbcfg_enable_bits(dev, 0x7c, 1 << 30, 0 << 30); /* Disable writes to the BAR3 register */ + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); /* Hide BAR3 */ + + /* Set up nonposted resource in MMIO space */ + res_base = res->base; /* Get the base address */ + res_end = resource_end(res); /* Get the limit (rounded up) */ + printk(BIOS_DEBUG, "%s: %s[0x1c] base = %0llx limit = %0llx\n", __func__, dev_path(dev), res_base, res_end); + + /* Locate an unused MMIO resource */ + for (reg = 0xb8; reg >= 0x80; reg -= 8) { + base = pci_read_config32(amd_addr_map_dev, reg); + limit = pci_read_config32(amd_addr_map_dev, reg + 4); + if (!(base & 0x3)) + break; /* Unused resource found */ + } + + /* If an unused MMIO resource was available, set up the mapping */ + if (!(base & 0x3)) { + uint32_t sblk; + + /* Remember this resource has been stored. */ + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, " <mmconfig>"); + + /* Get SBLink value (HyperTransport I/O Hub Link ID). */ + sblk = (pci_read_config32(amd_ht_cfg_dev, 0x64) >> 8) & 0x3; + + /* Calculate the MMIO mapping base */ + base &= 0x000000f0; + base |= ((res_base >> 8) & 0xffffff00); + base |= 3; + + /* Calculate the MMIO mapping limit */ + limit &= 0x00000048; + limit |= ((res_end >> 8) & 0xffffff00); + limit |= (sblk << 4); + limit |= (1 << 7); + + /* Configure and enable MMIO mapping */ + printk(BIOS_INFO, "%s: %s <- index %x base %04x limit %04x\n", __func__, dev_path(amd_addr_map_dev), reg, base, limit); + pci_write_config32(amd_addr_map_dev, reg + 4, limit); + pci_write_config32(amd_addr_map_dev, reg, base); + } + else { + printk(BIOS_WARNING, "%s: %s No free MMIO resources available\n", __func__, dev_path(dev)); + } + } + } + } + pci_dev_set_resources(dev); } diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 07b4a02..54f0071 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -796,6 +796,24 @@ static void add_ivrs_device_entries(struct device *parent, struct device *dev, i free(root_level); } +unsigned long acpi_fill_mcfg(unsigned long current) +{ + struct resource *res; + resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; + + if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + /* Report MMCONF base */ + res = probe_resource(dev, 0x1c); + if (res) + mmconf_base = res->base; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); + } + + return current; +} + static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current) { uint8_t *p;

1 0

Patch set updated for coreboot: mainboard/asus/kgpe-d16: Limit HT speed to 2.6GHz
by Timothy Pearson 26 Nov '15

26 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12064 -gerrit commit 3158f09884d96a77e91d376db5b58a8d6c54f802 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Sep 3 17:39:51 2015 -0500 mainboard/asus/kgpe-d16: Limit HT speed to 2.6GHz The CPU <--> CPU HT wiring on this board has only been validated to 2.6GHz. While higher frequencies appear to function initially, and in fact function when only one CPU package is installed, dual CPU package systems will lock up after around 6 - 12 hours of uptime due to presumed HT link errors at the higher (>= 2.8GHz) HT clocks. If applications are not being used that stress the coherent fabric, then the uptime before hang may be much longer. Users attempting to overclock the HT links are advised to "burn in test" the HT links by running memtester locked to a node with no local memory installed. Change-Id: I8fae90c67aa0e8b103e9b8906dea50d1e92ea5a9 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/romstage.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index ccb85f4..df76ab4 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -322,6 +322,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; + /* Limit the maximum HT speed to 2.6GHz to prevent lockups + * due to HT CPU <--> CPU wiring not being validated to 3.2GHz + */ + sysinfo->ht_link_cfg.ht_speed_limit = 2600; + uint32_t bsp_apicid = 0, val; uint8_t byte; msr_t msr;

1 0

Patch set updated for coreboot: mainboard/asus/kgpe-d16: Enable GART by default
by Timothy Pearson 26 Nov '15

26 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12067 -gerrit commit 96c9b22e047f527f24a4aeacb6c67f045d726418 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Sep 3 19:27:40 2015 -0500 mainboard/asus/kgpe-d16: Enable GART by default Change-Id: I73eb2425bbdb7e329a544d55461877d1dee0d05b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/cmos.default | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index b5e9f07..a05b9c3 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -23,7 +23,7 @@ maximum_p_state_limit = 0xf probe_filter = Auto l3_cache_partitioning = Disable ieee1394_controller = Enable -gart = Disable +gart = Enable experimental_memory_speed_boost = Disable power_on_after_fail = On boot_option = Fallback

1 0

Patch set updated for coreboot: nb/amd/amdmct/mct_ddr3: Use StopOnError to decrease training time
by Timothy Pearson 26 Nov '15

26 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12066 -gerrit commit 67a46e2360e0e433a0b6b30b15398f136704df9f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Sep 3 18:59:53 2015 -0500 nb/amd/amdmct/mct_ddr3: Use StopOnError to decrease training time There is no need to continue testing a DCT configuration after data errors have already been detected; this just wastes time during boot. Change-Id: I979e27c32a3e0b101590fba0de3d7a25d6fc44d2 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 84 +++++++++++++++++++------- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 4 +- 2 files changed, 64 insertions(+), 24 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 6aba8da..4cc87de 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1117,7 +1117,7 @@ static void stop_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, } static void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t Receiver, uint8_t lane) + struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t Receiver, uint8_t lane, uint8_t stop_on_error) { uint32_t dword; uint32_t dev = pDCTstat->dev_dct; @@ -1129,24 +1129,35 @@ static void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, if (lane < 4) { Set_NB32_DCT(dev, dct, 0x274, ~(0xff << (lane * 8))); Set_NB32_DCT(dev, dct, 0x278, ~0x0); + dword = Get_NB32_DCT(dev, dct, 0x27c); + dword |= 0xff; /* EccMask = 0xff */ + Set_NB32_DCT(dev, dct, 0x27c, dword); } else if (lane < 8) { Set_NB32_DCT(dev, dct, 0x274, ~0x0); Set_NB32_DCT(dev, dct, 0x278, ~(0xff << (lane * 8))); + dword = Get_NB32_DCT(dev, dct, 0x27c); + dword |= 0xff; /* EccMask = 0xff */ + Set_NB32_DCT(dev, dct, 0x27c, dword); + } else if (lane == 8) { + Set_NB32_DCT(dev, dct, 0x274, ~0x0); + Set_NB32_DCT(dev, dct, 0x278, ~0x0); + dword = Get_NB32_DCT(dev, dct, 0x27c); + dword &= ~(0xff); /* EccMask = 0x0 */ + Set_NB32_DCT(dev, dct, 0x27c, dword); } else if (lane == 0xff) { Set_NB32_DCT(dev, dct, 0x274, ~0xffffffff); Set_NB32_DCT(dev, dct, 0x278, ~0xffffffff); + dword = Get_NB32_DCT(dev, dct, 0x27c); + dword &= ~(0xff); /* EccMask = 0x0 */ + Set_NB32_DCT(dev, dct, 0x27c, dword); } else { Set_NB32_DCT(dev, dct, 0x274, ~0x0); Set_NB32_DCT(dev, dct, 0x278, ~0x0); + dword = Get_NB32_DCT(dev, dct, 0x27c); + dword |= 0xff; /* EccMask = 0xff */ + Set_NB32_DCT(dev, dct, 0x27c, dword); } - dword = Get_NB32_DCT(dev, dct, 0x27c); - dword &= ~(0xff); /* EccMask = 0 */ - if (lane != 0xff) - if ((lane != 8) || (pDCTstat->DimmECCPresent == 0)) - dword |= 0xff; /* EccMask = 0xff */ - Set_NB32_DCT(dev, dct, 0x27c, dword); - dword = Get_NB32_DCT(dev, dct, 0x270); dword &= ~(0x7ffff); /* DataPrbsSeed = 55555 */ // dword |= (0x55555); @@ -1178,7 +1189,8 @@ static void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, dword = Get_NB32_DCT(dev, dct, 0x250); dword |= (0x1 << 3); /* ResetAllErr = 1 */ - dword &= ~(0x1 << 4); /* StopOnErr = 0 */ + dword &= ~(0x1 << 4); /* StopOnErr = stop_on_error */ + dword |= (stop_on_error & 0x1) << 4; dword &= ~(0x3 << 8); /* CmdTgt = 1 (Alternate between Target A and Target B) */ dword |= (0x1 << 8); dword &= ~(0x7 << 5); /* CmdType = 0 (Read) */ @@ -1198,7 +1210,7 @@ static void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, } static void write_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t Receiver, uint8_t lane) + struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t Receiver, uint8_t lane, uint8_t stop_on_error) { uint32_t dword; uint32_t dev = pDCTstat->dev_dct; @@ -1210,24 +1222,35 @@ static void write_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, if (lane < 4) { Set_NB32_DCT(dev, dct, 0x274, ~(0xff << (lane * 8))); Set_NB32_DCT(dev, dct, 0x278, ~0x0); + dword = Get_NB32_DCT(dev, dct, 0x27c); + dword |= 0xff; /* EccMask = 0xff */ + Set_NB32_DCT(dev, dct, 0x27c, dword); } else if (lane < 8) { Set_NB32_DCT(dev, dct, 0x274, ~0x0); Set_NB32_DCT(dev, dct, 0x278, ~(0xff << (lane * 8))); + dword = Get_NB32_DCT(dev, dct, 0x27c); + dword |= 0xff; /* EccMask = 0xff */ + Set_NB32_DCT(dev, dct, 0x27c, dword); + } else if (lane == 8) { + Set_NB32_DCT(dev, dct, 0x274, ~0x0); + Set_NB32_DCT(dev, dct, 0x278, ~0x0); + dword = Get_NB32_DCT(dev, dct, 0x27c); + dword &= ~(0xff); /* EccMask = 0x0 */ + Set_NB32_DCT(dev, dct, 0x27c, dword); } else if (lane == 0xff) { Set_NB32_DCT(dev, dct, 0x274, ~0xffffffff); Set_NB32_DCT(dev, dct, 0x278, ~0xffffffff); + dword = Get_NB32_DCT(dev, dct, 0x27c); + dword &= ~(0xff); /* EccMask = 0x0 */ + Set_NB32_DCT(dev, dct, 0x27c, dword); } else { Set_NB32_DCT(dev, dct, 0x274, ~0x0); Set_NB32_DCT(dev, dct, 0x278, ~0x0); + dword = Get_NB32_DCT(dev, dct, 0x27c); + dword |= 0xff; /* EccMask = 0xff */ + Set_NB32_DCT(dev, dct, 0x27c, dword); } - dword = Get_NB32_DCT(dev, dct, 0x27c); - dword &= ~(0xff); /* EccMask = 0 */ - if (lane != 0xff) - if ((lane != 8) || (pDCTstat->DimmECCPresent == 0)) - dword |= 0xff; /* EccMask = 0xff */ - Set_NB32_DCT(dev, dct, 0x27c, dword); - dword = Get_NB32_DCT(dev, dct, 0x270); dword &= ~(0x7ffff); /* DataPrbsSeed = 55555 */ // dword |= (0x55555); @@ -1259,7 +1282,8 @@ static void write_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, dword = Get_NB32_DCT(dev, dct, 0x250); dword |= (0x1 << 3); /* ResetAllErr = 1 */ - dword &= ~(0x1 << 4); /* StopOnErr = 0 */ + dword &= ~(0x1 << 4); /* StopOnErr = stop_on_error */ + dword |= (stop_on_error & 0x1) << 4; dword &= ~(0x3 << 8); /* CmdTgt = 1 (Alternate between Target A and Target B) */ dword |= (0x1 << 8); dword &= ~(0x7 << 5); /* CmdType = 1 (Write) */ @@ -1293,6 +1317,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, uint8_t dual_rank; uint8_t write_iter; uint8_t read_iter; + uint8_t check_antiphase; uint16_t initial_write_dqs_delay[MAX_BYTE_LANES]; uint16_t initial_read_dqs_delay[MAX_BYTE_LANES]; uint16_t initial_write_data_timing[MAX_BYTE_LANES]; @@ -1374,7 +1399,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, /* 2.10.5.8.4 (2 B) * Write the DRAM training pattern to the test address */ - write_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, dct, Receiver, lane); + write_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, dct, Receiver, lane, 0); /* Read current settings of other (previously trained) lanes */ read_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); @@ -1385,6 +1410,12 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, for (current_read_dqs_delay[lane] = 0; current_read_dqs_delay[lane] < 0x40; current_read_dqs_delay[lane] += 2) { print_debug_dqs("\t\t\t\t\tTrainDQSRdWrPos: 161 current_read_dqs_delay[lane] ", current_read_dqs_delay[lane], 6); + if ((current_read_dqs_delay[lane] >> 1) >= (32 - 16)) { + check_antiphase = 1; + } else { + check_antiphase = 0; + } + /* 2.10.5.8.4 (2 A i) * Commit the current Read DQS Timing Control settings to the hardware registers */ @@ -1393,7 +1424,16 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, /* 2.10.5.8.4 (2 A ii) * Read the DRAM training pattern from the test address */ - read_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, dct, Receiver, lane); + read_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, dct, Receiver, lane, ((check_antiphase == 0)?1:0)); + + if (check_antiphase == 0) { + /* Check for early abort before analyzing per-nibble status */ + dword = Get_NB32_DCT(dev, dct, 0x264) & 0x1ffffff; + if (dword != 0) { + dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][(current_read_dqs_delay[lane] >> 1) + 16] = 0; /* Fail */ + continue; + } + } /* 2.10.5.8.4 (2 A iii) * Record pass / fail status @@ -1403,7 +1443,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][(current_read_dqs_delay[lane] >> 1) + 16] = 0; /* Fail */ else dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][(current_read_dqs_delay[lane] >> 1) + 16] = 1; /* Pass */ - if ((current_read_dqs_delay[lane] >> 1) >= (32 - 16)) { + if (check_antiphase == 1) { /* Check antiphase results */ dword = Get_NB32_DCT(dev, dct, 0x26c) & 0x3ffff; if (dword & (0x3 << (lane * 2))) @@ -1626,7 +1666,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, uint16_t current_phy_phase_delay[MAX_BYTE_LANES]; uint8_t dqs_results_array[1024]; - uint16_t ren_step = 0x40; + uint16_t ren_step = 0x40; uint32_t index_reg = 0x98; uint32_t dev = pDCTstat->dev_dct; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index b36ecae..1c756ab 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -1610,14 +1610,14 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, /* 2.10.5.8.5.1.[2,3] * Write the DRAM training pattern to the test address */ - write_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, Channel, current_worst_case_total_delay_dimm << 1, 0xff); + write_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, Channel, current_worst_case_total_delay_dimm << 1, 0xff, 0); /* 2.10.5.8.5.1.4 * Incrementally test each MaxRdLatency candidate */ for (; pDCTstat->CH_MaxRdLat[Channel] < 0x3ff; pDCTstat->CH_MaxRdLat[Channel]++) { write_max_read_latency_to_registers(pMCTstat, pDCTstat, Channel, pDCTstat->CH_MaxRdLat[Channel]); - read_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, Channel, current_worst_case_total_delay_dimm << 1, 0xff); + read_dram_dqs_training_pattern_fam15(pMCTstat, pDCTstat, Channel, current_worst_case_total_delay_dimm << 1, 0xff, 0); dword = Get_NB32_DCT(dev, Channel, 0x268) & 0x3ffff; if (!dword) break;

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2015