New patch to review for coreboot: northbridge/intel/pineview: Add native raminit
by Damien Zammit 20 Nov '15
by Damien Zammit 20 Nov '15
20 Nov '15
Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12501
-gerrit
commit 4fa67a24a9fc2c3c70a27b44ab4782b680bd55a7
Author: Damien Zammit <damien(a)zamaudio.com>
Date: Fri Nov 20 17:17:51 2015 +1100
northbridge/intel/pineview: Add native raminit
Does native ram init for Intel Atom D5xx 8086:a000 northbridge
Tested on Intel D510MO mainboard, board boots linux kernel
- Works fully with both dimms populated (2x2GB), memtest passes 100%
- Almost boots with only one dimm in one of the slots
(suspect bad memory map with one dimm?)
- Reads garbage with only one dimm in other slot
Change-Id: Ibd22be2a959045e0a83aae2a3a0e877013f80711
Signed-off-by: Damien Zammit <damien(a)zamaudio.com>
---
src/northbridge/intel/pineview/Makefile.inc | 1 +
src/northbridge/intel/pineview/raminit.c | 2837 +++++++++++++++++++++++++++
src/northbridge/intel/pineview/raminit.h | 23 +
3 files changed, 2861 insertions(+)
diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc
index 7275d70..a4c08c8 100644
--- a/src/northbridge/intel/pineview/Makefile.inc
+++ b/src/northbridge/intel/pineview/Makefile.inc
@@ -22,6 +22,7 @@ ramstage-y += gma.c
ramstage-y += acpi.c
romstage-y += ram_calc.c
+romstage-y += raminit.c
romstage-y += early_init.c
endif
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
new file mode 100644
index 0000000..2249402
--- /dev/null
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -0,0 +1,2837 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+#include <delay.h>
+#include <halt.h>
+#include <lib.h>
+#include "pineview.h"
+#include "raminit.h"
+#include <pc80/mc146818rtc.h>
+#include <spd.h>
+#include <string.h>
+
+/* Debugging macros. */
+#if CONFIG_DEBUG_RAM_SETUP
+#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x)
+#else
+#define PRINTK_DEBUG(x...)
+#endif
+
+#define MAX_TCLK_667 0x30
+#define MAX_TCLK_800 0x25
+#define MAX_TAC_667 0x45
+#define MAX_TAC_800 0x40
+
+#define NOP_CMD (1 << 1)
+#define PRE_CHARGE_CMD (1 << 2)
+#define MRS_CMD ((1 << 2) | (1 << 1))
+#define EMRS_CMD (1 << 3)
+#define EMRS1_CMD (EMRS_CMD | (1 << 4))
+#define EMRS2_CMD (EMRS_CMD | (1 << 5))
+#define EMRS3_CMD (EMRS_CMD | (1 << 5) | (1 << 4))
+#define ZQCAL_CMD ((1 << 3) | (1 << 1))
+#define CBR_CMD ((1 << 3) | (1 << 2))
+#define NORMAL_OP_CMD ((1 << 3) | (1 << 2) | (1 << 1))
+
+#define UBDIMM 1
+#define SODIMM 2
+
+#define barrier() __asm__ __volatile__("": : :"memory")
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#if 0
+static void sdram_dump_mchbar_registers(void)
+{
+ int i;
+ PRINTK_DEBUG("Dumping MCHBAR Registers\n");
+
+ for (i=0; i<0xfff; i+=4) {
+ if (MCHBAR32(i) == 0)
+ continue;
+ PRINTK_DEBUG("0x%04x: 0x%08x\n", i, MCHBAR32(i));
+ }
+}
+#endif
+
+static void sdram_read_spds(sysinfo_t *s)
+{
+ u8 i, j, chan, swap;
+ swap = 0;
+ int status = 0;
+ s->dt0mode = 0;
+ FOR_EACH_DIMM(i) {
+ for (j = 0; j < 64; j++) {
+ status = spd_read_byte(s->spd_map[i], j);
+ if (status < 0) {
+ s->dimms[i].card_type = 0;
+ break;
+ }
+ s->dimms[i].spd_data[j] = (u8) status;
+ PRINTK_DEBUG("%02x ", (u8) status);
+ if (j % 16 == 15)
+ PRINTK_DEBUG("\n");
+ if (j == 62)
+ s->dimms[i].card_type = ((u8) status) & 0x1f;
+ }
+ PRINTK_DEBUG("\n");
+ }
+
+ s->spd_type = 0;
+ FOR_EACH_POPULATED_DIMM(s->dimms, i) {
+ switch (s->dimms[i].spd_data[2]) {
+ case 0x8:
+ s->spd_type = DDR2;
+ break;
+ case 0xb:
+ default:
+ die("DIMM type mismatch\n");
+ break;
+ }
+ }
+
+ int fail = 1;
+ FOR_EACH_POPULATED_DIMM(s->dimms, i) {
+ s->dimms[i].type = 0;
+ if (s->dimms[i].spd_data[20] == 0x2) {
+ s->dimms[i].type = UBDIMM;
+ } else if (s->dimms[i].spd_data[20] == 0x4) {
+ s->dimms[i].type = SODIMM;
+ }
+ s->dimms[i].sides = (s->dimms[i].spd_data[5] & 0x7) + 1;
+ s->dimms[i].banks = (s->dimms[i].spd_data[17] >> 2) - 1;
+ s->dimms[i].chip_capacity = s->dimms[i].banks;
+ s->dimms[i].rows = s->dimms[i].spd_data[3];// - 12;
+ s->dimms[i].cols = s->dimms[i].spd_data[4];// - 9;
+ s->dimms[i].cas_latencies = 0x78;
+ s->dimms[i].cas_latencies &= s->dimms[i].spd_data[18];
+ if (s->dimms[i].cas_latencies == 0)
+ s->dimms[i].cas_latencies = 7;
+ s->dimms[i].tAAmin = s->dimms[i].spd_data[26];
+ s->dimms[i].tCKmin = s->dimms[i].spd_data[25];
+ s->dimms[i].width = (s->dimms[i].spd_data[13] >> 3) - 1;
+ s->dimms[i].page_size = (s->dimms[i].width+1) * (1 << s->dimms[i].cols); // Bytes
+ s->dimms[i].tRAS = s->dimms[i].spd_data[30];
+ s->dimms[i].tRP = s->dimms[i].spd_data[27];
+ s->dimms[i].tRCD = s->dimms[i].spd_data[29];
+ s->dimms[i].tWR = s->dimms[i].spd_data[36];
+ s->dimms[i].ranks = s->dimms[i].sides; // XXX
+ s->dt0mode |= (s->dimms[i].spd_data[49] & 0x2) >> 1;
+
+#if CONFIG_DEBUG_RAM_SETUP
+ char ubso[2][3] = { {"UB"}, {"SO"} };
+#endif
+ PRINTK_DEBUG("%s-DIMM %d\n", &ubso[s->dimms[i].type][0], i);
+ PRINTK_DEBUG(" Sides : %d\n", s->dimms[i].sides);
+ PRINTK_DEBUG(" Banks : %d\n", s->dimms[i].banks);
+ PRINTK_DEBUG(" Ranks : %d\n", s->dimms[i].ranks);
+ PRINTK_DEBUG(" Rows : %d\n", s->dimms[i].rows);
+ PRINTK_DEBUG(" Cols : %d\n", s->dimms[i].cols);
+ PRINTK_DEBUG(" Page size : %d\n", s->dimms[i].page_size);
+ PRINTK_DEBUG(" Width : %d\n", (s->dimms[i].width+1)*8);
+ fail = 0;
+ }
+
+ if (fail) {
+ die("No memory dimms, halt\n");
+ }
+
+ // Ram Config: DIMMB-DIMMA
+ // 0 EMPTY-EMPTY
+ // 1 EMPTY-x16SS
+ // 2 EMPTY-x16DS
+ // 3 x16SS-x16SS
+ // 4 x16DS-x16DS
+ // 5 EMPTY- x8DS
+ // 6 x8DS - x8DS
+
+ FOR_EACH_POPULATED_CHANNEL(s->dimms, chan) {
+ if (s->dimms[chan>>1].sides == 0) {
+ // NC
+ if (s->dimms[(chan>>1) + 1].sides == 0) {
+ // NC/NC
+ s->dimm_config[chan] = 0;
+ } else if (s->dimms[(chan>>1) + 1].sides == 1) {
+ // NC/SS
+ if (s->dimms[(chan>>1) + 1].width == 0) {
+ // NC/8SS
+ s->dimm_config[chan] = 1;
+ } else {
+ // NC/16SS
+ s->dimm_config[chan] = 1;
+ }
+ } else {
+ // NC/DS
+ if (s->dimms[(chan>>1) + 1].width == 0) {
+ // NC/8DS
+ s->dimm_config[chan] = 5;
+ } else {
+ // NC/16DS
+ s->dimm_config[chan] = 2;
+ }
+ }
+ } else if (s->dimms[chan>>1].sides == 1) {
+ // SS
+ if (s->dimms[(chan>>1) + 1].sides == 0) {
+ // SS/NC
+ if (s->dimms[chan>>1].width == 0) {
+ // 8SS/NC
+ s->dimm_config[chan] = 1;
+ swap = 1;
+ } else {
+ // 16SS/NC
+ s->dimm_config[chan] = 1;
+ swap = 1;
+ }
+ } else if (s->dimms[(chan>>1) + 1].sides == 1) {
+ // SS/SS
+ if (s->dimms[chan>>1].width == 0) {
+ if (s->dimms[(chan>>1) + 1].width == 0) {
+ // 8SS/8SS
+ s->dimm_config[chan] = 3;
+ } else {
+ // 8SS/16SS
+ die("Mixed Not supported\n");
+ }
+ } else {
+ if (s->dimms[(chan>>1) + 1].width == 0) {
+ // 16SS/8SS
+ die("Mixed Not supported\n");
+ } else {
+ // 16SS/16SS
+ s->dimm_config[chan] = 3;
+ }
+ }
+ } else {
+ // SS/DS
+ if (s->dimms[chan>>1].width == 0) {
+ if (s->dimms[(chan>>1) + 1].width == 0) {
+ // 8SS/8DS
+ die("Mixed Not supported\n");
+ } else {
+ die("Mixed Not supported\n");
+ }
+ } else {
+ if (s->dimms[(chan>>1) + 1].width == 0) {
+ // 16SS/8DS
+ die("Mixed Not supported\n");
+ } else {
+ die("Mixed Not supported\n");
+ }
+ }
+ }
+ } else {
+ // DS
+ if (s->dimms[(chan>>1) + 1].sides == 0) {
+ // DS/NC
+ if (s->dimms[chan>>1].width == 0) {
+ // 8DS/NC
+ s->dimm_config[chan] = 5;
+ swap = 1;
+ } else {
+ s->dimm_config[chan] = 4;
+ swap = 1;
+ }
+ } else if (s->dimms[(chan>>1) + 1].sides == 1) {
+ // DS/SS
+ if (s->dimms[chan>>1].width == 0) {
+ if (s->dimms[(chan>>1) + 1].width == 0) {
+ // 8DS/8SS
+ die("Mixed Not supported\n");
+ } else {
+ // 8DS/16SS
+ die("Mixed Not supported\n");
+ }
+ } else {
+ if (s->dimms[(chan>>1) + 1].width == 0) {
+ die("Mixed Not supported\n");
+ } else {
+ // 16DS/16DS
+ s->dimm_config[chan] = 4;
+ }
+ }
+ } else {
+ // DS/DS
+ if (s->dimms[chan>>1].width == 0 && s->dimms[(chan>>1)+1].width == 0) {
+ // 8DS/8DS
+ s->dimm_config[chan] = 6;
+ }
+ }
+ }
+ PRINTK_DEBUG(" Config[CH%d] : %d\n", chan, s->dimm_config[chan]);
+ }
+/*
+ if (swap) {
+ // Swap dimm info on ch 0
+ dimminfo_t tmp;
+ memcpy(&tmp, &s->dimms[0], sizeof(dimminfo_t));
+ memcpy(&s->dimms[0], &s->dimms[1], sizeof(dimminfo_t));
+ memcpy(&s->dimms[1], &tmp, sizeof(dimminfo_t));
+ }
+*/
+}
+
+#if CONFIG_DEBUG_RAM_SETUP
+static u32 fsb2mhz(u32 speed)
+{
+ return (speed * 133) + 667;
+}
+
+static u32 ddr2mhz(u32 speed)
+{
+ u32 mhz;
+ mhz = (speed == 0) ? 667 :
+ (speed == 1) ? 800 :
+ 0;
+ return mhz;
+}
+#endif
+
+static u8 lsbpos(u8 val) //Forward
+{
+ u8 i;
+ for (i = 0; (i < 8) && ((val & (1 << i)) == 0); i++);
+ return i;
+}
+
+static u8 msbpos(u8 val) //Reverse
+{
+ u8 i;
+ for (i = 7; (i >= 0) && ((val & (1 << i)) == 0); i--);
+ return i;
+}
+
+static void sdram_detect_smallest_params(struct sys_info *s)
+{
+ u16 mult[6] = {
+ 3000, // 667
+ 2500, // 800
+ };
+
+ u8 i;
+ u32 tmp;
+ u32 maxtras = 0;
+ u32 maxtrp = 0;
+ u32 maxtrcd = 0;
+ u32 maxtwr = 0;
+ u32 maxtrfc = 0;
+ u32 maxtwtr = 0;
+ u32 maxtrrd = 0;
+ u32 maxtrtp = 0;
+
+ FOR_EACH_POPULATED_DIMM(s->dimms, i) {
+ maxtras = max(maxtras, s->dimms[i].spd_data[30] * 1000);
+ maxtrp = max(maxtrp, (s->dimms[i].spd_data[27] * 1000) >> 2);
+ maxtrcd = max(maxtrcd, (s->dimms[i].spd_data[29] * 1000) >> 2);
+ maxtwr = max(maxtwr, (s->dimms[i].spd_data[36] * 1000) >> 2);
+ maxtrfc = max(maxtrfc, s->dimms[i].spd_data[42] * 1000 +
+ (s->dimms[i].spd_data[40] & 0xf));
+ maxtwtr = max(maxtwtr, (s->dimms[i].spd_data[37] * 1000) >> 2);
+ maxtrrd = max(maxtrrd, (s->dimms[i].spd_data[28] * 1000) >> 2);
+ maxtrtp = max(maxtrtp, (s->dimms[i].spd_data[38] * 1000) >> 2);
+ }
+ for (i = 9; i < 24; i++) { // 16
+ tmp = mult[s->selected_timings.mem_clock] * i;
+ if (tmp >= maxtras) {
+ s->selected_timings.tRAS = i;
+ break;
+ }
+ }
+ for (i = 3; i < 10; i++) {
+ tmp = mult[s->selected_timings.mem_clock] * i;
+ if (tmp >= maxtrp) {
+ s->selected_timings.tRP = i;
+ break;
+ }
+ }
+ for (i = 3; i < 10; i++) {
+ tmp = mult[s->selected_timings.mem_clock] * i;
+ if (tmp >= maxtrcd) {
+ s->selected_timings.tRCD = i;
+ break;
+ }
+ }
+ for (i = 3; i < 15; i++) {
+ tmp = mult[s->selected_timings.mem_clock] * i;
+ if (tmp >= maxtwr) {
+ s->selected_timings.tWR = i;
+ break;
+ }
+ }
+ for (i = 15; i < 78; i++) {
+ tmp = mult[s->selected_timings.mem_clock] * i;
+ if (tmp >= maxtrfc) {
+ s->selected_timings.tRFC = ((i + 16) & 0xfe) - 15;
+ break;
+ }
+ }
+ for (i = 4; i < 15; i++) {
+ tmp = mult[s->selected_timings.mem_clock] * i;
+ if (tmp >= maxtwtr) {
+ s->selected_timings.tWTR = i;
+ break;
+ }
+ }
+ for (i = 2; i < 15; i++) {
+ tmp = mult[s->selected_timings.mem_clock] * i;
+ if (tmp >= maxtrrd) {
+ s->selected_timings.tRRD = i;
+ break;
+ }
+ }
+ for (i = 4; i < 15; i++) {
+ tmp = mult[s->selected_timings.mem_clock] * i;
+ if (tmp >= maxtrtp) {
+ s->selected_timings.tRTP = i;
+ break;
+ }
+ }
+
+ PRINTK_DEBUG("Selected timings:\n");
+ PRINTK_DEBUG(" FSB: %dMHz\n", fsb2mhz(s->selected_timings.fsb_clock));
+ PRINTK_DEBUG(" DDR: %dMHz\n", ddr2mhz(s->selected_timings.mem_clock));
+
+ PRINTK_DEBUG(" CAS: %d\n", s->selected_timings.CAS);
+ PRINTK_DEBUG(" tRAS: %d\n", s->selected_timings.tRAS);
+ PRINTK_DEBUG(" tRP: %d\n", s->selected_timings.tRP);
+ PRINTK_DEBUG(" tRCD: %d\n", s->selected_timings.tRCD);
+ PRINTK_DEBUG(" tWR: %d\n", s->selected_timings.tWR);
+ PRINTK_DEBUG(" tRFC: %d\n", s->selected_timings.tRFC);
+ PRINTK_DEBUG(" tWTR: %d\n", s->selected_timings.tWTR);
+ PRINTK_DEBUG(" tRRD: %d\n", s->selected_timings.tRRD);
+ PRINTK_DEBUG(" tRTP: %d\n", s->selected_timings.tRTP);
+}
+
+static void sdram_detect_ram_speed(struct sys_info *s)
+{
+ u8 cas, reg8;
+ u32 reg32;
+ u32 freq = 0;
+ u32 fsb = 0;
+ u8 i;
+ u8 commoncas = 0;
+ u8 highcas = 0;
+ u8 lowcas = 0;
+
+ // Core frequency
+ fsb = (pci_read_config8(PCI_DEV(0,0,0), 0xe3) & 0x70) >> 4;
+ if (fsb) {
+ fsb = 5 - fsb;
+ } else {
+ fsb = FSB_CLOCK_800MHz;
+ }
+
+ // DDR frequency
+ freq = (pci_read_config8(PCI_DEV(0,0,0), 0xe3) & 0x80) >> 7;
+ freq |= (pci_read_config8(PCI_DEV(0,0,0), 0xe4) & 0x3) << 1;
+ if (freq) {
+ freq = 6 - freq;
+ } else {
+ freq = MEM_CLOCK_800MHz;
+ }
+
+ // Detect a common CAS latency
+ commoncas = 0xff;
+ FOR_EACH_POPULATED_DIMM(s->dimms, i) {
+ commoncas &= s->dimms[i].spd_data[18];
+ }
+ if (commoncas == 0) {
+ die("No common CAS among dimms\n");
+ }
+
+ // Start with fastest common CAS
+ cas = 0;
+ highcas = msbpos(commoncas);
+ lowcas = max(lsbpos(commoncas), 5);
+
+ while (cas == 0 && highcas >= lowcas) {
+ FOR_EACH_POPULATED_DIMM(s->dimms, i) {
+ switch (freq) {
+ case MEM_CLOCK_800MHz:
+ if ((s->dimms[i].spd_data[9] > 0x25) ||
+ (s->dimms[i].spd_data[10] > 0x40)) {
+ // CAS too fast, lower it
+ highcas--;
+ break;
+ } else {
+ cas = highcas;
+ }
+ break;
+ case MEM_CLOCK_667MHz:
+ default:
+ if ((s->dimms[i].spd_data[9] > 0x30) ||
+ (s->dimms[i].spd_data[10] > 0x45)) {
+ // CAS too fast, lower it
+ highcas--;
+ break;
+ } else {
+ cas = highcas;
+ }
+ break;
+ }
+ }
+ }
+ if (highcas < lowcas) {
+ // Timings not supported by MCH, lower the frequency
+ if(freq == MEM_CLOCK_800MHz) {
+ freq--;
+ PRINTK_DEBUG("Run DDR clock speed reduced due to timings\n");
+ } else {
+ die("Timings not supported by MCH\n");
+ }
+ cas = 0;
+ highcas = msbpos(commoncas);
+ lowcas = lsbpos(commoncas);
+ while (cas == 0 && highcas >= lowcas) {
+ FOR_EACH_POPULATED_DIMM(s->dimms, i) {
+ switch (freq) {
+ case MEM_CLOCK_800MHz:
+ if ((s->dimms[i].spd_data[9] > 0x25) ||
+ (s->dimms[i].spd_data[10] > 0x40)) {
+ // CAS too fast, lower it
+ highcas--;
+ break;
+ } else {
+ cas = highcas;
+ }
+ break;
+ case MEM_CLOCK_667MHz:
+ default:
+ if ((s->dimms[i].spd_data[9] > 0x30) ||
+ (s->dimms[i].spd_data[10] > 0x45)) {
+ // CAS too fast, lower it
+ highcas--;
+ break;
+ } else {
+ cas = highcas;
+ }
+ break;
+ }
+ }
+ }
+ if (cas == 0) {
+ die("Unsupported dimms\n");
+ }
+ }
+
+ s->selected_timings.CAS = cas;
+ s->selected_timings.mem_clock = freq;
+ s->selected_timings.fsb_clock = fsb;
+
+ PRINTK_DEBUG("Drive Memory at %dMHz with CAS = %d clocks\n", ddr2mhz(s->selected_timings.mem_clock), s->selected_timings.CAS);
+
+ // Set memory frequency
+ MCHBAR32(0xf14) = MCHBAR32(0xf14) | 0x1;
+ reg32 = (MCHBAR32(0xc00) & (~0x70)) | (1 << 10);
+ if (s->selected_timings.mem_clock == MEM_CLOCK_800MHz) {
+ reg8 = 3;
+ } else {
+ reg8 = 2;
+ }
+ reg32 |= reg8 << 4;
+ MCHBAR32(0xc00) = reg32;
+ s->selected_timings.mem_clock = ((MCHBAR32(0xc00) >> 4) & 0x7) - 2;
+ if (s->selected_timings.mem_clock == MEM_CLOCK_800MHz) {
+ PRINTK_DEBUG("MCH validated at 800MHz\n");
+ s->nodll = 0;
+ s->maxpi = 63;
+ s->pioffset = 0;
+ } else if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) {
+ PRINTK_DEBUG("MCH validated at 667MHz\n");
+ s->nodll = 1;
+ s->maxpi = 15;
+ s->pioffset = 1;
+ } else {
+ PRINTK_DEBUG("MCH set to unknown (%02x)\n",
+ (uint8_t) s->selected_timings.mem_clock & 0xff);
+ }
+}
+
+#define HPET_BASE 0xfed00000
+#define HPET32(x) *((volatile u32 *)(HPET_BASE + x))
+#if 1
+static void enable_hpet(void)
+{
+ u32 reg32;
+ reg32 = RCBA32(0x3404);
+ reg32 &= ~0x3;
+ reg32 |= (1 << 7);
+ RCBA32(0x3404) = reg32;
+ HPET32(0x10) = HPET32(0x10) | 1;
+}
+#endif
+
+static void sdram_clk_crossing(sysinfo_t *s)
+{
+ u8 i, j;
+ u32 clkcross[2][2][4] = {
+ {
+ {0xFFFFFFFF, 0x05030305, 0x0000FFFF, 0x00000000}, //667 667
+ {0x1F1F1F1F, 0x2A1F1FA5, 0x00000000, 0x05000002}, //667 800
+ },
+ {
+ {0x1F1F1F1F, 0x0D07070B, 0x00000000, 0x00000000}, //800 667
+ {0xFFFFFFFF, 0x05030305, 0x0000FFFF, 0x00000000}, //800 800
+ }
+ };
+ i = s->selected_timings.mem_clock;
+ j = s->selected_timings.fsb_clock;
+
+ MCHBAR32(0xc04) = clkcross[j][i][0];
+ MCHBAR32(0xc50) = clkcross[j][i][1];
+ MCHBAR32(0xc54) = clkcross[j][i][2];
+ MCHBAR32(0xc28) = 0;
+ MCHBAR32(0xc2c) = clkcross[j][i][3];
+ MCHBAR32(0xc08) = MCHBAR32(0xc08) | (1 << 7);
+
+ if ((j == 0) && (i == 1)) {
+ MCHBAR8(0x6d4) = 0;
+ MCHBAR32(0x700) = 0;
+ MCHBAR32(0x704) = 0;
+ }
+
+ u32 clkcross2[2][2][8] = {
+ {
+ { 0, 0x08010204, 0, 0x08010204, 0, 0, 0, 0x04080102}, // 667 667
+ { 0x04080000, 0x10010002, 0x10000000, 0x20010208, 0, 0x00000004, 0x02040000, 0x08100102}, // 667 800
+ },
+ {
+ { 0x10000000, 0x20010208, 0x04080000, 0x10010002, 0, 0, 0x08000000, 0x10200204}, // 800 667
+ { 0x00000000, 0x08010204, 0, 0x08010204, 0, 0, 0, 0x04080102}, // 800 800
+ }
+ };
+
+ MCHBAR32(0x6d8) = clkcross2[j][i][0];
+ MCHBAR32(0x6e0) = clkcross2[j][i][0];
+ MCHBAR32(0x6e8) = clkcross2[j][i][0];
+ MCHBAR32(0x6d8+4) = clkcross2[j][i][1];
+ MCHBAR32(0x6e0+4) = clkcross2[j][i][1];
+ MCHBAR32(0x6e8+4) = clkcross2[j][i][1];
+ MCHBAR32(0x6f0) = clkcross2[j][i][2];
+ MCHBAR32(0x6f4) = clkcross2[j][i][3];
+ MCHBAR32(0x6f8) = clkcross2[j][i][4];
+ MCHBAR32(0x6fc) = clkcross2[j][i][5];
+ MCHBAR32(0x708) = clkcross2[j][i][6];
+ MCHBAR32(0x70c) = clkcross2[j][i][7];
+}
+
+static void sdram_clkmode(struct sys_info *s)
+{
+ u8 reg8;
+ u16 reg16;
+
+ MCHBAR16(0x1b6) = MCHBAR16(0x1b6) & ~(1 << 8);
+ MCHBAR8(0x1b6) = MCHBAR8(0x1b6) & ~0x3f;
+
+ if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) {
+ reg8 = 0;
+ reg16 = 1;
+ } else {
+ reg8 = 1;
+ reg16 = (1 << 8) | (1 << 5);
+ }
+ MCHBAR16(0x1c0) = (MCHBAR16(0x1c0) & ~(0x033f)) | reg16;
+
+ MCHBAR32(0x220) = 0x58001117;
+ MCHBAR32(0x248) = (MCHBAR32(0x248) | (1 << 23));
+
+ const u32 table1[2][4] = {
+ {0x00000000, 0x00030100, 0x0C240201, 0x00000000}, // 667
+ {0x00000000, 0x00030100, 0x0C240201, 0x10450302} // 800
+ };
+
+ MCHBAR32(0x224) = table1[reg8][s->selected_timings.CAS - 3];
+}
+
+static void sdram_timings(struct sys_info *s)
+{
+ u8 i, j, ch, r, ta1, ta2, ta3, ta4, trp, bank, page, flag;
+ u8 reg8, wl;
+ u16 reg16;
+ u32 reg32, reg2;
+ u8 pagetab[2][2] = {{0xe, 0x12}, {0x10, 0x14}};
+
+ // Only consider DDR2
+ wl = s->selected_timings.CAS - 1;
+ ta1 = ta2 = 6;
+ ta3 = s->selected_timings.CAS;
+ ta4 = 8;
+ s->selected_timings.tRFC = (s->selected_timings.tRFC + 1) & 0xfe;
+ trp = 0;
+ bank = 1;
+ page = 0;
+
+ MCHBAR8(0x240) = ((wl - 3) << 4) | (s->selected_timings.CAS - 3);
+
+ FOR_EACH_POPULATED_RANK(s->dimms, ch, r) {
+ i = ch << 1;
+ if (s->dimms[i].banks == 1) {
+ trp = 1;
+ bank = 0;
+ }
+ if (s->dimms[i].page_size == 2048) {
+ page = 1;
+ }
+ }
+ PRINTK_DEBUG("trp=%d bank=%d page=%d\n",trp, bank, page);
+
+ if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) {
+ flag = 0;
+ } else {
+ flag = 1;
+ }
+
+ MCHBAR8(0x26f) = MCHBAR8(0x26f) | 0x3;
+ MCHBAR16(0x250) = ((wl + 4 + s->selected_timings.tWR) << 6) |
+ ((2 + MAX(s->selected_timings.tRTP, 2)) << 2) | 1;
+ reg32 = (bank << 21) | (s->selected_timings.tRRD << 17) |
+ (s->selected_timings.tRP << 13) |
+ ((s->selected_timings.tRP + trp) << 9) |
+ s->selected_timings.tRFC;
+ if (bank == 0) {
+ reg32 |= (pagetab[flag][page] << 22);
+ }
+ MCHBAR16(0x252) = (u16) reg32;
+ MCHBAR16(0x254) = (u16) (reg32 >> 16);
+
+ reg16 = (MCHBAR16(0x254) & 0xfc0) >> 6;
+ MCHBAR16(0x62c) = (MCHBAR16(0x62c) & ~0x1f80) | (reg16 << 7);
+
+ reg16 = (s->selected_timings.tRCD << 12) | (4 << 8) | (ta2 << 4) | ta4;
+ MCHBAR16(0x256) = reg16;
+
+ reg32 = (s->selected_timings.tRCD << 17) |
+ ((wl + 4 + s->selected_timings.tWTR) << 12) |
+ (ta3 << 8) | (4 << 4) | ta1;
+ MCHBAR32(0x258) = reg32;
+
+ reg16 = ((s->selected_timings.tRP + trp) << 9) |
+ s->selected_timings.tRFC;
+ MCHBAR8(0x25b) = (u8) reg16;
+ MCHBAR8(0x25c) = (u8) (reg16 >> 8);
+
+ MCHBAR16(0x260) = (MCHBAR16(0x260) & ~0x3fe) | (100 << 1);
+ MCHBAR8(0x25d) = (MCHBAR8(0x25d) & ~0x3f) | s->selected_timings.tRAS;
+ MCHBAR16(0x244) = 0x2310;
+
+ MCHBAR8(0x246) = (MCHBAR8(0x246) & ~0x1f) | 1;
+
+ if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) {
+ reg32 = 3000;
+ } else {
+ reg32 = 2500;
+ }
+ if (s->selected_timings.fsb_clock == FSB_CLOCK_667MHz) {
+ reg2 = 6000;
+ } else {
+ reg2 = 5000;
+ }
+ reg16 = (u16)((((s->selected_timings.CAS + 7)*(reg32)) / reg2) << 8);
+ MCHBAR16(0x248) = (MCHBAR16(0x248) & ~0x1f00) | reg16;
+
+ flag = 0;
+ if (wl > 2) {
+ flag = 1;
+ }
+ reg16 = (u8) (wl - 1 - flag);
+ reg16 |= reg16 << 4;
+ reg16 |= flag << 8;
+ MCHBAR16(0x24d) = (MCHBAR16(0x24d) & ~0x1ff) | reg16;
+
+ MCHBAR16(0x25e) = 0x1585;
+ MCHBAR8(0x265) = MCHBAR8(0x265) & ~0x1f;
+ MCHBAR16(0x265) = (MCHBAR16(0x265) & ~0x3f00) |
+ ((s->selected_timings.CAS + 9) << 8);
+
+ if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) {
+ reg16 = 0x514;
+ reg32 = 0xa28;
+ } else {
+ reg16 = 0x618;
+ reg32 = 0xc30;
+ }
+ MCHBAR32(0x268) = (MCHBAR32(0x268) & ~0xfffff00) |
+ (0x3f << 22) | (reg32 << 8);
+ MCHBAR8(0x26c) = 0x00;
+ MCHBAR16(0x2b8) = (MCHBAR16(0x2b8) & 0xc000) | reg16;
+ MCHBAR8(0x274) = MCHBAR8(0x274) | 1;
+
+ MCHBAR32(0x248) = (MCHBAR32(0x248) & ~0x7f000000) | (0xb << 25);
+ i = s->selected_timings.mem_clock;
+ j = s->selected_timings.fsb_clock;
+ if (i > j) {
+ MCHBAR32(0x248) = MCHBAR32(0x248) | (1 << 24);
+ }
+
+ MCHBAR8(0x24c) = MCHBAR8(0x24c) & ~0x3;
+ MCHBAR16(0x24d) = (MCHBAR16(0x24d) & ~0x7c00) | ((wl + 10) << 10);
+ MCHBAR32(0x260) = (MCHBAR32(0x260) & ~0x70e0000) | (3 << 24) | (3 << 17);
+ reg16 = 0x15 << 6;
+ reg16 |= 0x1f;
+ reg16 |= (0x6 << 12);
+ MCHBAR16(0x26d) = (MCHBAR16(0x26d) & ~0x7fff) | reg16;
+
+ reg32 = (0x6 << 27) | (1 << 25);
+ MCHBAR32(0x268) = (MCHBAR32(0x268) & ~0x30000000) | ((u32)(reg32 << 8));
+ MCHBAR8(0x26c) = (MCHBAR8(0x26c) & ~0xfa) | ((u8)(reg32 >> 24));
+ MCHBAR8(0x271) = MCHBAR8(0x271) & ~(1 << 7);
+ MCHBAR8(0x274) = MCHBAR8(0x274) & ~0x6;
+ reg32 = (u32) ((6 << 30) | (4 << 25) | (1 << 20) | (8 << 15) |
+ (6 << 10) | (4 << 5) | 1);
+ MCHBAR32(0x278) = reg32;
+
+ MCHBAR16(0x27c) = (MCHBAR16(0x27c) & ~0x1ff) | (8 << 3) | (6 >> 2);
+ MCHBAR16(0x125) = MCHBAR16(0x125) | 0x1c00 | (0x1f << 5);
+ MCHBAR8(0x127) = (MCHBAR8(0x127) & ~0xff) | 0x40;
+ MCHBAR8(0x128) = (MCHBAR8(0x128) & ~0x7) | 0x5;
+ MCHBAR8(0x129) = MCHBAR8(0x129) | 0x1f;
+ reg8 = 3 << 6;
+ reg8 |= (s->dt0mode << 4);
+ reg8 |= 0x0c;
+ MCHBAR8(0x12f) = (MCHBAR8(0x12f) & ~0xdf) | reg8;
+ MCHBAR8(0x18c) = MCHBAR8(0x18c) & ~0x2;
+ MCHBAR8(0x228) = (MCHBAR8(0x228) & ~0x7) | 0x2;
+ MCHBAR16(0x241) = (MCHBAR16(0x241) & ~0x3fc) | (4 << 2);
+ reg32 = (2 << 29) | (1 << 28) | (1 << 23);
+ MCHBAR32(0x120) = (MCHBAR32(0x120) & ~0xffb00000) | reg32;
+
+ reg8 = (u8) ((MCHBAR16(0x252) & 0xe000) >> 13);
+ reg8 |= (u8) ((MCHBAR16(0x254) & 1) << 3);
+ MCHBAR8(0x12d) = (MCHBAR8(0x12d) & ~0xf0) | (reg8 << 4);
+ reg8 = (u8) ((MCHBAR32(0x258) & 0xf0000) >> 17);
+ MCHBAR8(0x12d) = (MCHBAR8(0x12d) & ~0xf) | reg8;
+ MCHBAR8(0x12e) = MCHBAR8(0x12e) & ~0xfc;
+ MCHBAR8(0x12e) = MCHBAR8(0x12e) & ~0x3;
+ MCHBAR8(0x12f) = MCHBAR8(0x12f) & ~0x3;
+ MCHBAR8(0x241) = MCHBAR8(0x241) | 1;
+ MCHBAR16(0x1b6) = MCHBAR16(0x1b6) | (1 << 9);
+ for (i = 0; i < 8; i++) {
+ MCHBAR32(0x540 + i*4) = (MCHBAR32(0x540 + i*4) & ~0x3f3f3f3f) |
+ 0x0c0c0c0c;
+ }
+ MCHBAR32(0x248) = (MCHBAR32(0x248) & ~0xf0000) |
+ ((s->selected_timings.CAS + 1) << 16);
+ for (i = 0; i < 8; i++) {
+ MCHBAR8(0x560 + i*4) = MCHBAR8(0x560 + i*4) & ~0x3f;
+ MCHBAR16(0x58c) = MCHBAR16(0x58c) & ((u16) (~(3 << (i*2))));
+ MCHBAR16(0x588) = MCHBAR16(0x588) & ((u16) (~(3 << (i*2))));
+ MCHBAR16(0x5fa) = MCHBAR16(0x5fa) & ((u16) (~(3 << (i*2))));
+ }
+ MCHBAR8(0x5f0) = MCHBAR8(0x5f0) & ~0x1;
+ MCHBAR8(0x5f0) = MCHBAR8(0x5f0) | 0x2;
+ MCHBAR8(0x5f0) = MCHBAR8(0x5f0) | 0x4;
+ MCHBAR32(0x2c0) = MCHBAR32(0x2c0) | 0xc0400;
+ MCHBAR32(0x594) = MCHBAR32(0x594) | (1 << 31);
+}
+
+static void sdram_p_clkset0(struct pllparam *pll, u8 f, u8 i)
+{
+ MCHBAR16(0x5a0) = (MCHBAR16(0x5a0) & ~0xc440) |
+ (pll->clkdelay[f][i] << 14) |
+ (pll->dben[f][i] << 10) |
+ (pll->dbsel[f][i] << 6);
+ MCHBAR8(0x581) = (MCHBAR8(0x581) & ~0x3f) | pll->pi[f][i];
+}
+
+static void sdram_p_clkset1(struct pllparam *pll, u8 f, u8 i)
+{
+ MCHBAR16(0x5a0) = (MCHBAR16(0x5a0) & ~0x30880) |
+ (pll->clkdelay[f][i] << 16) |
+ (pll->dben[f][i] << 11) |
+ (pll->dbsel[f][i] << 7);
+ MCHBAR8(0x582) = (MCHBAR8(0x582) & ~0x3f) | pll->pi[f][i];
+}
+
+static void sdram_p_cmd(struct pllparam *pll, u8 f, u8 i)
+{
+ u8 reg8;
+ reg8 = pll->dbsel[f][i] << 5;
+ reg8 |= pll->dben[f][i] << 6;
+ MCHBAR8(0x594) = (MCHBAR8(0x594) & ~0x60) | reg8;
+
+ reg8 = pll->clkdelay[f][i] << 4;
+ MCHBAR8(0x598) = (MCHBAR8(0x598) & ~0x30) | reg8;
+
+ reg8 = pll->pi[f][i];
+ MCHBAR8(0x580) = (MCHBAR8(0x580) & ~0x3f) | reg8;
+ MCHBAR8(0x583) = (MCHBAR8(0x583) & ~0x3f) | reg8;
+}
+
+static void sdram_p_ctrl(struct pllparam *pll, u8 f, u8 i)
+{
+ u8 reg8;
+ u32 reg32;
+ reg32 = ((u32) pll->dbsel[f][i]) << 20;
+ reg32 |= ((u32) pll->dben[f][i]) << 21;
+ reg32 |= ((u32) pll->dbsel[f][i]) << 22;
+ reg32 |= ((u32) pll->dben[f][i]) << 23;
+ reg32 |= ((u32) pll->clkdelay[f][i]) << 24;
+ reg32 |= ((u32) pll->clkdelay[f][i]) << 27;
+ MCHBAR32(0x59c) = (MCHBAR32(0x59c) & ~0x1bf0000) | reg32;
+
+ reg8 = pll->pi[f][i];
+ MCHBAR8(0x584) = (MCHBAR8(0x584) & ~0x3f) | reg8;
+ MCHBAR8(0x585) = (MCHBAR8(0x585) & ~0x3f) | reg8;
+
+ reg32 = ((u32) pll->dbsel[f][i]) << 12;
+ reg32 |= ((u32) pll->dben[f][i]) << 13;
+ reg32 |= ((u32) pll->dbsel[f][i]) << 8;
+ reg32 |= ((u32) pll->dben[f][i]) << 9;
+ reg32 |= ((u32) pll->clkdelay[f][i]) << 14;
+ reg32 |= ((u32) pll->clkdelay[f][i]) << 10;
+ MCHBAR32(0x598) = (MCHBAR32(0x598) & ~0xff00) | reg32;
+
+ reg8 = pll->pi[f][i];
+ MCHBAR8(0x586) = (MCHBAR8(0x586) & ~0x3f) | reg8;
+ MCHBAR8(0x587) = (MCHBAR8(0x587) & ~0x3f) | reg8;
+}
+
+static void sdram_p_dqs(struct pllparam *pll, u8 f, u8 clk)
+{
+ u8 rank, dqs, reg8, j;
+ u32 reg32;
+
+ j = clk - 40;
+ reg8 = 0;
+ reg32 = 0;
+ rank = j % 4;
+ dqs = j / 4;
+
+ reg32 |= ((u32) pll->dben[f][clk]) << (dqs + 9);
+ reg32 |= ((u32) pll->dbsel[f][clk]) << dqs;
+ MCHBAR32(0x5b4+rank*4) = (MCHBAR32(0x5b4+rank*4) &
+ ~( (1 << (dqs+9))|(1 << dqs) )) | reg32;
+
+ reg32 = ((u32) pll->clkdelay[f][clk]) << ((dqs*2) + 16);
+ MCHBAR32(0x5c8+rank*4) = (MCHBAR32(0x5c8+rank*4) &
+ ~( (1 << (dqs*2 + 17))|(1 << (dqs*2 + 16)) )) | reg32;
+
+ reg8 = pll->pi[f][clk];
+ MCHBAR8(0x520+j) = (MCHBAR8(0x520+j) & ~0x3f) | reg8;
+}
+
+
+static void sdram_p_dq(struct pllparam *pll, u8 f, u8 clk)
+{
+ u8 rank, dq, reg8, j;
+ u32 reg32;
+
+ j = clk - 8;
+ reg8 = 0;
+ reg32 = 0;
+ rank = j % 4;
+ dq = j / 4;
+
+ reg32 |= ((u32) pll->dben[f][clk]) << (dq + 9);
+ reg32 |= ((u32) pll->dbsel[f][clk]) << dq;
+ MCHBAR32(0x5a4+rank*4) = (MCHBAR32(0x5a4+rank*4) &
+ ~( (1 << (dq+9))|(1 << dq) )) | reg32;
+
+ reg32 = ((u32) pll->clkdelay[f][clk]) << (dq*2);
+ MCHBAR32(0x5c8+rank*4) = (MCHBAR32(0x5c8+rank*4) &
+ ~( (1 << (dq*2 + 1))|(1 << (dq*2)) )) | reg32;
+
+ reg8 = pll->pi[f][clk];
+ MCHBAR8(0x500+j) = (MCHBAR8(0x500+j) & ~0x3f) | reg8;
+}
+
+static void sdram_calibratepll(struct sys_info *s, u8 pidelay)
+{
+ struct pllparam pll = {
+ .pi = {
+ { // 667
+ 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
+ 7, 7, 7, 7, 4, 4, 4, 4, 4, 4, 4, 4,
+ 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5,
+ 7, 7, 7, 7, 3, 3, 3, 3, 3, 3, 3, 3,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 1, 1, 1, 1, 3, 3, 3, 3
+ },
+ { // 800
+ 53, 53, 10, 10, 5, 5, 5, 5, 27, 27, 27, 27,
+ 34, 34, 34, 34, 34, 34, 34, 34, 39, 39, 39, 39,
+ 47, 47, 47, 47, 44, 44, 44, 44, 47, 47, 47, 47,
+ 47, 47, 47, 47, 59, 59, 59, 59, 2, 2, 2, 2,
+ 2, 2, 2, 2, 7, 7, 7, 7, 15, 15, 15, 15,
+ 12, 12, 12, 12, 15, 15, 15, 15, 15, 15, 15, 15
+ }},
+
+ .dben = {
+ { // 667
+ 0,0,1,1,1,1,1,1,1,1,1,1,
+ 1,1,1,1,0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,0,0,0,0,
+ 1,1,1,1,0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,0,0,0,0
+ },
+ { // 800
+ 1,1,1,1,1,1,1,1,0,0,0,0,
+ 0,0,0,0,0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,0,0,0,0,
+ 0,0,0,0,1,1,1,1,1,1,1,1,
+ 1,1,1,1,1,1,1,1,0,0,0,0,
+ 1,1,1,1,0,0,0,0,0,0,0,0
+ }},
+
+ .dbsel = {
+ { // 667
+ 0,0,1,1,1,1,1,1,1,1,1,1,
+ 1,1,1,1,0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,0,0,0,0,
+ 1,1,1,1,0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,0,0,0,0
+ },
+ { // 800
+ 0,0,1,1,1,1,1,1,0,0,0,0,
+ 0,0,0,0,0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,1,1,1,1,
+ 1,1,1,1,1,1,1,1,0,0,0,0,
+ 1,1,1,1,0,0,0,0,0,0,0,0
+ }},
+
+ .clkdelay = {
+ { // 667
+ 0,0,1,1,0,0,0,0,1,1,1,1,
+ 1,1,1,1,1,1,1,1,1,1,1,1,
+ 1,1,1,1,1,1,1,1,1,1,1,1,
+ 1,1,1,1,0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,0,0,0,0
+ },
+ { // 800
+ 0,0,0,0,0,0,0,0,1,1,1,1,
+ 1,1,1,1,1,1,1,1,1,1,1,1,
+ 1,1,1,1,1,1,1,1,1,1,1,1,
+ 1,1,1,1,0,0,0,0,1,1,1,1,
+ 1,1,1,1,1,1,1,1,1,1,1,1,
+ 1,1,1,1,1,1,1,1,1,1,1,1
+ }}
+ };
+
+ u8 i, f;
+ if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) {
+ f = 0;
+ } else {
+ f = 1;
+ }
+ for (i = 0; i < 72; i++) {
+ pll.pi[f][i] += pidelay;
+ }
+
+ MCHBAR8(0x1a4) = MCHBAR8(0x1a4) & ~(1 << 7);
+ MCHBAR16(0x190) = (MCHBAR16(0x190) & (u16) ~(0x3fff)) | 0x1fff;
+
+ sdram_p_clkset0(&pll, f, 0);
+ sdram_p_clkset1(&pll, f, 1);
+ sdram_p_cmd(&pll, f, 2);
+ sdram_p_ctrl(&pll, f, 4);
+ for (i = 0; i < 32; i++) {
+ sdram_p_dqs(&pll, f, i+40);
+ }
+ for (i = 0; i < 32; i++) {
+ sdram_p_dq(&pll, f, i+8);
+ }
+}
+
+static void sdram_calibratehwpll(struct sys_info *s)
+{
+ u8 reg8;
+
+ s->async = 0;
+ reg8 = 0;
+ MCHBAR16(0x180) = MCHBAR16(0x180) | (1 << 15);
+ MCHBAR8(0x180) = MCHBAR8(0x180) & ~(1 << 7);
+ MCHBAR8(0x180) = MCHBAR8(0x180) | (1 << 3);
+ MCHBAR8(0x180) = MCHBAR8(0x180) | (1 << 2);
+
+ MCHBAR8(0x180) = MCHBAR8(0x180) | (1 << 7);
+ while ((MCHBAR8(0x180) & (1 << 2)) == 0);
+
+ reg8 = (MCHBAR8(0x180) & (1 << 3)) >> 3;
+ if (reg8 != 0) {
+ s->async = 1;
+ }
+}
+
+static void sdram_dlltiming(struct sys_info *s)
+{
+ u8 reg8, i, pipost;
+ u16 reg16;
+ u32 reg32;
+
+ if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) {
+ reg32 = 0x8014227;
+ } else {
+ reg32 = 0x14221;
+ }
+ MCHBAR32(0x19c) = (MCHBAR32(0x19c) & ~0xfffffff) | reg32;
+ MCHBAR32(0x19c) = MCHBAR32(0x19c) | (1 << 23);
+ MCHBAR32(0x19c) = MCHBAR32(0x19c) | (1 << 15);
+ MCHBAR32(0x19c) = MCHBAR32(0x19c) & ~(1 << 15);
+
+ if (s->nodll) {
+ MCHBAR16(0x198) = MCHBAR16(0x198) | (1 << 0);
+ MCHBAR16(0x198) = MCHBAR16(0x198) | (1 << 2);
+ MCHBAR16(0x198) = MCHBAR16(0x198) | (1 << 4);
+ MCHBAR16(0x198) = MCHBAR16(0x198) | (1 << 8);
+ MCHBAR16(0x198) = MCHBAR16(0x198) | (1 << 10);
+ MCHBAR16(0x198) = MCHBAR16(0x198) | (1 << 12);
+ MCHBAR16(0x198) = MCHBAR16(0x198) | (1 << 14);
+ } else {
+ MCHBAR16(0x198) = MCHBAR16(0x198) & ~(1 << 0);
+ MCHBAR16(0x198) = MCHBAR16(0x198) & ~(1 << 2);
+ MCHBAR16(0x198) = MCHBAR16(0x198) & ~(1 << 4);
+ MCHBAR16(0x198) = MCHBAR16(0x198) & ~(1 << 8);
+ MCHBAR16(0x198) = MCHBAR16(0x198) & ~(1 << 10);
+ MCHBAR16(0x198) = MCHBAR16(0x198) & ~(1 << 12);
+ MCHBAR16(0x198) = MCHBAR16(0x198) & ~(1 << 14);
+ }
+
+ if (s->nodll) {
+ MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x3f) | 0x7;
+ } else {
+ MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x3f);
+ }
+
+ sdram_calibratepll(s, 0); // XXX check
+
+ MCHBAR16(0x5f0) = MCHBAR16(0x5f0) | (1 << 11);
+ MCHBAR16(0x5f0) = MCHBAR16(0x5f0) | (1 << 12);
+
+ for (i = 0; i < 8; i++) {
+ MCHBAR16(0x5f0) = MCHBAR16(0x5f0) | ((1 << 10) >> i);
+ }
+ MCHBAR8(0x2c14) = MCHBAR8(0x2c14) | 1;
+ MCHBAR16(0x182) = 0x5005;
+ MCHBAR16(0x18a) = (MCHBAR16(0x18a) & ~0x1f1f) | 0x51a;
+ MCHBAR16(0x2c00) = (MCHBAR16(0x2c00) & ~0xbf3f) | 0x9010;
+
+ if (s->nodll) {
+ MCHBAR8(0x18e) = (MCHBAR8(0x18e) & ~0x7f) | 0x6b;
+ } else {
+ MCHBAR8(0x18e) = (MCHBAR8(0x18e) & ~0x7f) | 0x55;
+ sdram_calibratehwpll(s);
+ }
+ pipost = 0x34;
+
+ MCHBAR32(0x248) = MCHBAR32(0x248) & ~(1 << 22);
+ MCHBAR8(0x5d9) = MCHBAR8(0x5d9) & ~0x2;
+ MCHBAR8(0x189) = MCHBAR8(0x189) | 0xc0;
+ MCHBAR8(0x189) = MCHBAR8(0x189) & ~(1 << 5);
+ MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xc0) | (1 << 6);
+ MCHBAR8(0x188) = (MCHBAR8(0x188) & ~0x3f) | 0x1a;
+ MCHBAR8(0x188) = MCHBAR8(0x188) | 1;
+
+ MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 1;
+ MCHBAR32(0x1a0) = 0x551803;
+ if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0)) {
+ reg8 = 0x3c;
+ } else if (ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) {
+ reg8 = 0x27;
+ } else if (BOTH_DIMMS_ARE_POPULATED(s->dimms, 0)) {
+ reg8 = 0x24;
+ } else {
+ // None
+ reg8 = 0x3f;
+ }
+ reg8 = 0x00; //switch all clocks on anyway
+
+ MCHBAR32(0x5a0) = (MCHBAR32(0x5a0) & ~0x3f000000) | (reg8 << 24);
+ MCHBAR8(0x594) = MCHBAR8(0x594) & ~1;
+ reg16 = 0;
+ if (!RANK_IS_POPULATED(s->dimms, 0, 0)) {
+ reg16 |= (1 << 8) | (1 << 4) | (1 << 0);
+ }
+ if (!RANK_IS_POPULATED(s->dimms, 0, 1)) {
+ reg16 |= (1 << 9) | (1 << 5) | (1 << 1);
+ }
+ if (!RANK_IS_POPULATED(s->dimms, 0, 2)) {
+ reg16 |= (1 << 10) | (1 << 6) | (1 << 2);
+ }
+ if (!RANK_IS_POPULATED(s->dimms, 0, 3)) {
+ reg16 |= (1 << 11) | (1 << 7) | (1 << 3);
+ }
+ MCHBAR16(0x59c) = MCHBAR16(0x59c) | reg16;
+}
+
+static void sdram_rcomp(struct sys_info *s)
+{
+ u8 i, j, reg8, f, rcompp, rcompn, srup, srun;
+ u16 reg16;
+ u32 reg32, rcomp1, rcomp2;
+
+ u8 rcompupdate[7] = { 0, 0, 0, 1, 1, 0, 0 };
+ u8 rcompslew = 0xa;
+ u8 rcompstr[7] = { 0x66, 0, 0xaa, 0x55, 0x55, 0x77, 0x77 };
+ u16 rcompscomp[7] = { 0xa22a, 0, 0xe22e, 0xe22e, 0xe22e, 0xa22a, 0xa22a };
+ u8 rcompdelay[7] = { 1, 0, 0, 0, 0, 1, 1 };
+ u16 rcompctl[7] = { 0x31c, 0, 0x374, 0x3a2, 0x3d0, 0x3fe, 0x42c };
+ u16 rcompf[7] = { 0x1114, 0, 0x0505, 0x0909, 0x0909, 0x0a0a, 0x0a0a };
+
+ // NC-NC x16SS x16DS x16SS2 x16DS2 x8DS, x8DS2
+ u8 rcompstr2[7] = { 0x00, 0x55, 0x55, 0xaa, 0xaa , 0x55, 0xaa};
+ u16 rcompscomp2[7] = { 0x0000, 0xe22e, 0xe22e, 0xe22e, 0x8228 , 0xe22e, 0x8228 };
+ u8 rcompdelay2[7] = { 0, 0, 0, 0, 2 , 0, 2};
+
+ u8 rcomplut[64][12] = {
+ { 9, 9,11,11, 2, 2, 5,5, 6, 6,5, 5},
+ { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5},
+ { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5},
+ { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5},
+ { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5},
+ { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5},
+ { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5},
+ { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5},
+ { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5},
+ { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5},
+ { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5},
+ { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5},
+ { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5},
+ { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5},
+ { 9, 9,11, 11, 2, 2, 5,5, 6, 6,5, 5},
+ { 10,9,12, 11, 2, 2, 5,5, 6, 6,5, 5},
+ { 10,9,12, 11, 2, 2, 6,5, 7, 6,6, 5},
+ { 10,10,12, 12, 2, 2, 6,5, 7, 6,6, 5},
+ { 10,10,12, 12, 2, 2, 6,6, 7, 7,6, 6},
+ { 10,10,12, 12, 3, 2, 6,6, 7, 7,6, 6},
+ { 10,10,12, 12, 3, 2, 6,6, 7, 7,6, 6},
+ { 10,10,12, 12, 3, 2, 6,6, 7, 7,6, 6},
+ { 10,10,12, 12, 3, 3, 6,6, 7, 7,6, 6},
+ { 10,10,12, 12, 3, 3, 6,6, 7, 7,6, 6},
+ { 10,10,12, 12, 3, 3, 6,6, 7, 7,6, 6},
+ { 10,10,12, 12, 3, 3, 6,6, 7, 7,6, 6},
+ { 10,10,12, 12, 3, 3, 6,6, 7, 7,6, 6},
+ { 11,10,12, 12, 3, 3, 6,6, 7, 7,6, 6},
+ { 11,10,14, 13, 3, 3, 6,6, 7, 7,6, 6},
+ { 12,10,14, 13, 3, 3, 6,6, 7, 7,6, 6},
+ { 12,12,14, 13, 3, 3, 7,6, 7, 7,7, 6},
+ { 13,12,16, 15, 3, 3, 7,6, 8, 7,7, 6},
+ { 13,14,16, 15, 4, 3, 7,7, 8, 8,7, 7},
+ { 14,14,16, 17, 4, 3, 7,7, 8, 8,7, 7},
+ { 14,16,18, 17, 4, 4, 8,7, 8, 8,8, 7},
+ { 15,16,18, 19, 4, 4, 8,7, 9, 8,8, 7},
+ { 15,18,18, 19, 4, 4, 8,8, 9, 9,8, 8},
+ { 16,18,20, 21, 4, 4, 8,8, 9, 9,8, 8},
+ { 16,19,20, 21, 5, 4, 9,8, 10, 9,9, 8},
+ { 16,19,20, 23, 5, 5, 9,9, 10, 10,9, 9},
+ { 17,19,22, 23, 5, 5, 9,9, 10, 10,9, 9},
+ { 17,20,22, 25, 5, 5, 9,9, 10, 10,9, 9},
+ { 17,20,22, 25, 5, 5, 9,9, 10, 10,9, 9},
+ { 18,20,22, 25, 5, 5, 9,9, 10, 10,9, 9},
+ { 18,21,24, 25, 5, 5, 9,9, 11, 10,9, 9},
+ { 19,21,24, 27, 5, 5, 9, 9, 11, 11,9, 9},
+ { 19,22,24, 27, 5, 5, 10,9, 11, 11,10, 9},
+ { 20,22,24, 27, 6, 5, 10,10, 11, 11,10, 10},
+ { 20,23,26, 27, 6, 6, 10,10, 12, 12,10, 10},
+ { 20,23,26, 29, 6, 6, 10,10, 12, 12,10, 10},
+ { 21,24,26, 29, 6, 6, 10,10, 12, 12,10, 10},
+ { 21,24,26, 29, 6, 6, 11,10, 12, 13,11, 10},
+ { 22,25,28, 29, 6, 6, 11,11, 13, 13,11, 11},
+ { 22,25,28, 31, 6, 6, 11,11, 13, 13,11, 11},
+ { 22,26,28, 31, 6, 6, 11,11, 13, 14,11, 11},
+ { 23,26,30, 31, 7, 6, 12,11, 14, 14,12, 11},
+ { 23,27,30, 33, 7, 7, 12,12, 14, 14,12, 12},
+ { 23,27,30, 33, 7, 7, 12,12, 14, 15,12, 12},
+ { 24,28,32, 33, 7, 7, 12,12, 15, 15,12, 12},
+ { 24,28,32, 33, 7, 7, 12,12, 15, 16,12, 12},
+ { 24,29,32, 35, 7, 7, 12,12, 15, 16,12, 12},
+ { 25,29,32, 35, 7, 7, 12,12, 15, 17,12, 12},
+ { 25,30,32, 35, 7, 7, 12,12, 15, 17,12, 12},
+ { 25,30,32, 35, 7, 7, 12,12, 15, 17,12, 12},
+ };
+
+ srup = 0;
+ srun = 0;
+
+ if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) {
+ f = 0;
+ rcomp1 = 0x00050431;
+ } else {
+ f = 1;
+ rcomp1 = 0x00050542;
+ }
+ if (s->selected_timings.fsb_clock == FSB_CLOCK_667MHz) {
+ rcomp2 = 0x14C42827;
+ } else {
+ rcomp2 = 0x19042827;
+ }
+
+ for (i = 0; i < 7; i++) {
+ if (i == 1)
+ continue;
+ reg8 = rcompupdate[i];
+ MCHBAR8(rcompctl[i]) = (MCHBAR8(rcompctl[i]) & ~0x1) | reg8;
+ MCHBAR8(rcompctl[i]) = MCHBAR8(rcompctl[i]) & ~0x2;
+ reg16 = (u16) rcompslew;
+ MCHBAR16(rcompctl[i]) = (MCHBAR16(rcompctl[i]) & ~0xf000) |
+ (reg16 << 12);
+ MCHBAR8(rcompctl[i]+4) = rcompstr[i];
+ MCHBAR16(rcompctl[i]+0xe) = rcompscomp[i];
+ MCHBAR8(rcompctl[i]+0x14) = (MCHBAR8(rcompctl[i]+0x14) & ~0x3) |
+ rcompdelay[i];
+ if (i == 2) {
+ reg16 = (u16) rcompslew;
+ MCHBAR16(rcompctl[i]) = (MCHBAR16(rcompctl[i]) &
+ ~0xf000) | (reg16 << 12);
+ MCHBAR8(rcompctl[i]+4) = rcompstr2[s->dimm_config[0]];
+ MCHBAR16(rcompctl[i]+0xe) = rcompscomp2[s->dimm_config[0]];
+ MCHBAR8(rcompctl[i]+0x14) = (MCHBAR8(rcompctl[i]+0x14) &
+ ~0x3) | rcompdelay2[s->dimm_config[0]];
+ }
+
+ MCHBAR16(rcompctl[i]+0x16) = MCHBAR16(rcompctl[i]+0x16) & ~0x7f7f;
+ MCHBAR16(rcompctl[i]+0x18) = MCHBAR16(rcompctl[i]+0x18) & ~0x3f3f;
+ MCHBAR16(rcompctl[i]+0x1a) = MCHBAR16(rcompctl[i]+0x1a) & ~0x3f3f;
+ MCHBAR16(rcompctl[i]+0x1c) = MCHBAR16(rcompctl[i]+0x1c) & ~0x3f3f;
+ MCHBAR16(rcompctl[i]+0x1e) = MCHBAR16(rcompctl[i]+0x1e) & ~0x3f3f;
+ }
+
+ MCHBAR8(0x45a) = (MCHBAR8(0x45a) & ~0x3f) | 0x36;
+ MCHBAR8(0x462) = (MCHBAR8(0x462) & ~0x3f) | 0x36;
+
+ for (i = 0; i < 7; i++) {
+ if (i == 1)
+ continue;
+ MCHBAR8(rcompctl[i]) = MCHBAR8(rcompctl[i]) & ~0x60;
+ MCHBAR16(rcompctl[i]+2) = MCHBAR16(rcompctl[i]+2) & ~0x706;
+ MCHBAR16(rcompctl[i]+0xa) = MCHBAR16(rcompctl[i]+0xa) & ~0x7f7f;
+ MCHBAR16(rcompctl[i]+0x12) = MCHBAR16(rcompctl[i]+0x12) & ~0x3f3f;
+ MCHBAR16(rcompctl[i]+0x24) = MCHBAR16(rcompctl[i]+0x24) & ~0x1f1f;
+ MCHBAR8(rcompctl[i]+0x26) = MCHBAR8(rcompctl[i]+0x26) & ~0x1f;
+ }
+
+ MCHBAR16(0x45a) = MCHBAR16(0x45a) & ~0xffc0;
+ MCHBAR16(0x45c) = MCHBAR16(0x45c) & ~0xf;
+ MCHBAR16(0x462) = MCHBAR16(0x462) & ~0xffc0;
+ MCHBAR16(0x464) = MCHBAR16(0x464) & ~0xf;
+
+ for (i = 0; i < 7; i++) {
+ if (i == 1)
+ continue;
+ MCHBAR16(rcompctl[i]+0x10) = rcompf[i];
+ MCHBAR16(rcompctl[i]+0x20) = 0x1219;
+ MCHBAR16(rcompctl[i]+0x22) = 0x000C;
+ }
+
+ MCHBAR32(0x164) = (MCHBAR32(0x164) & ~0x1f1f1f) | 0x0c1219;
+ MCHBAR16(0x4b0) = (MCHBAR16(0x4b0) & ~0x1f00) | 0x1200;
+ MCHBAR8(0x4b0) = (MCHBAR8(0x4b0) & ~0x1f) | 0x12;
+ MCHBAR32(0x138) = 0x007C9007;
+ MCHBAR32(0x16c) = rcomp1;
+ MCHBAR16(0x17a) = 0x1f7f;
+ MCHBAR32(0x134) = rcomp2;
+ MCHBAR16(0x170) = (MCHBAR16(0x170) & ~0xf) | 1;
+ MCHBAR16(0x178) = 0x134;
+ MCHBAR32(0x130) = 0x4C293600;
+ MCHBAR8(0x133) = (MCHBAR8(0x133) & ~0x44) | (1 << 6) | (1 << 2);
+ MCHBAR16(0x4b0) = MCHBAR16(0x4b0) & ~(1 << 13);
+ MCHBAR8(0x4b0) = MCHBAR8(0x4b0) & ~(1 << 5);
+
+ for (i = 0; i < 7; i++) {
+ if (i == 1)
+ continue;
+ MCHBAR8(rcompctl[i]+2) = MCHBAR8(rcompctl[i]) & ~0x71;
+ }
+
+ if ((MCHBAR32(0x130) & (1 << 30)) == 0) {
+ MCHBAR8(0x130) = MCHBAR8(0x130) | 0x1;
+ while ((MCHBAR8(0x130) & 0x1) != 0);
+
+ reg32 = MCHBAR32(0x13c);
+ rcompp = (u8) ((reg32 & ~(1 << 31)) >> 24);
+ rcompn = (u8) ((reg32 & ~(0xff800000)) >> 16);
+
+ for (i = 0; i < 7; i++) {
+ if (i == 1)
+ continue;
+ srup = (MCHBAR8(rcompctl[i]+1) & 0xc0) >> 6;
+ srun = (MCHBAR8(rcompctl[i]+1) & 0x30) >> 4;
+ reg16 = (u16)(rcompp - (1 << (srup + 1))) << 8;
+ MCHBAR16(rcompctl[i]+0x16) = (MCHBAR16(rcompctl[i]+0x16)
+ & ~0x7f00) | reg16;
+ reg16 = (u16)(rcompn - (1 << (srun + 1)));
+ MCHBAR8(rcompctl[i]+0x16) = (MCHBAR8(rcompctl[i]+0x16) &
+ ~0x7f) | (u8)reg16;
+ }
+
+ reg8 = rcompp - (1 << (srup + 1));
+ for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) {
+ MCHBAR8(rcompctl[0]+0x18+i) =
+ (MCHBAR8(rcompctl[0]+0x18+i) & ~0x3f) |
+ rcomplut[j][0];
+ }
+
+ for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) {
+ if (s->dimm_config[0] < 3 || s->dimm_config[0] == 5) {
+ MCHBAR8(rcompctl[2]+0x18+i) =
+ (MCHBAR8(rcompctl[2]+0x18+i) & ~0x3f) |
+ rcomplut[j][10];
+ }
+ }
+
+ for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) {
+ MCHBAR8(rcompctl[3]+0x18+i) =
+ (MCHBAR8(rcompctl[3]+0x18+i) & ~0x3f) |
+ rcomplut[j][6];
+ MCHBAR8(rcompctl[4]+0x18+i) =
+ (MCHBAR8(rcompctl[4]+0x18+i) & ~0x3f) |
+ rcomplut[j][6];
+ }
+
+ for (i = 0, j = reg8; i < 4; i++, j += (1 << srup)) {
+ MCHBAR8(rcompctl[5]+0x18+i) =
+ (MCHBAR8(rcompctl[5]+0x18+i) & ~0x3f) |
+ rcomplut[j][8];
+ MCHBAR8(rcompctl[6]+0x18+i) =
+ (MCHBAR8(rcompctl[6]+0x18+i) & ~0x3f) |
+ rcomplut[j][8];
+ }
+
+ reg8 = rcompn - (1 << (srun + 1));
+ for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) {
+ MCHBAR8(rcompctl[0]+0x1c+i) =
+ (MCHBAR8(rcompctl[0]+0x1c+i) & ~0x3f) |
+ rcomplut[j][1];
+ }
+
+ for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) {
+ if (s->dimm_config[0] < 3 || s->dimm_config[0] == 5) {
+ MCHBAR8(rcompctl[2]+0x1c+i) =
+ (MCHBAR8(rcompctl[2]+0x1c+i) & ~0x3f) |
+ rcomplut[j][11];
+ }
+ }
+
+ for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) {
+ MCHBAR8(rcompctl[3]+0x1c+i) =
+ (MCHBAR8(rcompctl[3]+0x1c+i) & ~0x3f) |
+ rcomplut[j][7];
+ MCHBAR8(rcompctl[4]+0x1c+i) =
+ (MCHBAR8(rcompctl[4]+0x1c+i) & ~0x3f) |
+ rcomplut[j][7];
+ }
+
+ for (i = 0, j = reg8; i < 4; i++, j += (1 << srun)) {
+ MCHBAR8(rcompctl[5]+0x1c+i) =
+ (MCHBAR8(rcompctl[5]+0x1c+i) & ~0x3f) |
+ rcomplut[j][9];
+ MCHBAR8(rcompctl[6]+0x1c+i) =
+ (MCHBAR8(rcompctl[6]+0x1c+i) & ~0x3f) |
+ rcomplut[j][9];
+ }
+ }
+ MCHBAR8(0x130) = MCHBAR8(0x130) | 1;
+}
+
+static void sdram_odt(struct sys_info *s)
+{
+ u8 rankindex = 0;
+
+ u16 odt294[16] = {
+ 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0044, 0x1111, 0x0000, 0x1111,
+ 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0044, 0x1111, 0x0000, 0x1111
+ };
+ u16 odt298[16] = {
+ 0x0000, 0x0011, 0x0000, 0x0011,
+ 0x0000, 0x4444, 0x0000, 0x4444,
+ 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x4444, 0x0000, 0x4444
+ };
+
+ switch (s->dimms[0].ranks) {
+ case 0:
+ if (s->dimms[1].ranks == 0) {
+ rankindex = 0;
+ } else if (s->dimms[1].ranks == 1) {
+ rankindex = 4;
+ } else if (s->dimms[1].ranks == 2) {
+ rankindex = 12;
+ }
+ break;
+ case 1:
+ if (s->dimms[1].ranks == 0) {
+ rankindex = 1;
+ } else if (s->dimms[1].ranks == 1) {
+ rankindex = 5;
+ } else if (s->dimms[1].ranks == 2) {
+ rankindex = 13;
+ }
+ break;
+ case 2:
+ if (s->dimms[1].ranks == 0) {
+ rankindex = 3;
+ } else if (s->dimms[1].ranks == 1) {
+ rankindex = 7;
+ } else if (s->dimms[1].ranks == 2) {
+ rankindex = 15;
+ }
+ break;
+ }
+
+ MCHBAR16(0x298) = odt298[rankindex];
+ MCHBAR16(0x294) = odt294[rankindex];
+}
+
+static void sdram_mmap(struct sys_info *s)
+{
+ u32 w260[7] = {0, 0x400001, 0xc00001, 0x500000, 0xf00000, 0xc00001, 0xf00000};
+ u32 w208[7] = {0, 0x10000, 0x1010000, 0x10001, 0x1010101, 0x1010000, 0x1010101};
+ u32 w200[7] = {0, 0, 0, 0x20002, 0x40002, 0, 0x40002};
+ u32 w204[7] = {0, 0x20002, 0x40002, 0x40004, 0x80006, 0x40002, 0x80006};
+
+ u16 tolud[7] = {0x800, 0x800, 0x1000, 0x1000, 0x2000, 0x1000, 0x2000};
+ u16 tom[7] = {0x2, 0x2, 0x4, 0x4, 0x8, 0x4, 0x8};
+ u16 touud[7] = {0x80, 0x80, 0x100, 0x100, 0x200, 0x100, 0x200};
+ u32 gbsm[7] = {0x8000000, 0x8000000, 0x10000000, 0x8000000, 0x20000000, 0x10000000, 0x20000000};
+ u32 bgsm[7] = {0x8000000, 0x8000000, 0x10000000, 0x8000000, 0x20000000, 0x10000000, 0x20000000};
+ u32 tsegmb[7] = {0x8000000, 0x8000000, 0x10000000, 0x8000000, 0x20000000, 0x10000000, 0x20000000};
+
+ if ((s->dimm_config[0] < 3) && RANK_IS_POPULATED(s->dimms, 0, 0)) {
+ if (s->dimms[0].sides > 1) {
+ // 2R/NC
+ MCHBAR32(0x260) = (MCHBAR32(0x260) & ~0x1) | 0x300001;
+ MCHBAR32(0x208) = 0x101;
+ MCHBAR32(0x200) = 0x40002;
+ MCHBAR32(0x204) = w204[s->dimm_config[0]];
+ } else {
+ // 1R/NC
+ MCHBAR32(0x260) = (MCHBAR32(0x260) & ~0x1) | 0x100001;
+ MCHBAR32(0x208) = 0x1;
+ MCHBAR32(0x200) = 0x20002;
+ MCHBAR32(0x204) = w204[s->dimm_config[0]];
+ }
+ } else if ((s->dimm_config[0] == 5) && RANK_IS_POPULATED(s->dimms, 0, 0)) {
+
+ MCHBAR32(0x260) = (MCHBAR32(0x260) & ~0x1) | 0x300001;
+ MCHBAR32(0x208) = 0x101;
+ MCHBAR32(0x200) = 0x40002;
+ MCHBAR32(0x204) = 0x40004;
+ } else {
+ MCHBAR32(0x260) = (MCHBAR32(0x260) & ~0x1) | w260[s->dimm_config[0]];
+ MCHBAR32(0x208) = w208[s->dimm_config[0]];
+ MCHBAR32(0x200) = w200[s->dimm_config[0]];
+ MCHBAR32(0x204) = w204[s->dimm_config[0]];
+ }
+ pci_write_config16(PCI_DEV(0, 0, 0), 0xb0, tolud[s->dimm_config[0]]);
+ pci_write_config16(PCI_DEV(0, 0, 0), 0xa0, tom[s->dimm_config[0]]);
+ pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud[s->dimm_config[0]]);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gbsm[s->dimm_config[0]]);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, bgsm[s->dimm_config[0]]);
+ pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegmb[s->dimm_config[0]]);
+}
+
+#if 1
+static void hpet_udelay(u32 del)
+{
+ u32 start, finish, now;
+
+ del *= 15; /* now in usec */
+
+ start = HPET32(0xf0);
+ finish = start + del;
+ while (1) {
+ now = HPET32(0xf0);
+ if (finish > start) {
+ if (now >= finish)
+ break;
+ } else {
+ if ((now < start) && (now >= finish)) {
+ break;
+ }
+ }
+ }
+}
+#endif
+
+static u8 sdram_checkrcompoverride(void)
+{
+ u32 xcomp;
+ u8 aa, bb, a, b, c, d;
+
+ xcomp = MCHBAR32(0x13c);
+ a = (u8)((xcomp & 0x7f000000) >> 24);
+ b = (u8)((xcomp & 0x7f0000) >> 16);
+ c = (u8)((xcomp & 0x3f00) >> 8);
+ d = (u8)(xcomp & 0x3f);
+
+ if (a > b) {
+ aa = a - b;
+ } else {
+ aa = b - a;
+ }
+ if (c > d) {
+ bb = c - d;
+ } else {
+ bb = d - c;
+ }
+ if ((aa > 18) || (bb > 7) ||
+ (a <= 5) || (b <= 5) || (c <= 5) || (d <= 5) ||
+ (a >= 0x7a) || (b >= 0x7a) || (c >= 0x3a) || (d >= 0x3a)) {
+ MCHBAR32(0x140) = 0x9718a729;
+ return 1;
+ }
+ return 0;
+}
+
+static void sdram_rcompupdate(struct sys_info *s)
+{
+ u8 i, ok;
+ u32 reg32a, reg32b;
+
+ ok = 0;
+ MCHBAR8(0x170) = MCHBAR8(0x170) & ~(1 << 3);
+ MCHBAR8(0x130) = MCHBAR8(0x130) & ~(1 << 7);
+ for (i = 0; i < 3; i++) {
+ MCHBAR8(0x130) = MCHBAR8(0x130) | 1;
+ hpet_udelay(1000);
+ while ((MCHBAR8(0x130) & 0x1) != 0);
+ ok |= sdram_checkrcompoverride();
+ }
+ if (!ok) {
+ reg32a = MCHBAR32(0x13c);
+ reg32b = (reg32a >> 16) & 0x0000ffff;
+ reg32a = ((reg32a << 16) & 0xffff0000) | reg32b;
+ reg32a |= (1 << 31) | (1 << 15);
+ MCHBAR32(0x140) = reg32a;
+ }
+ MCHBAR8(0x130) = MCHBAR8(0x130) | 1;
+ hpet_udelay(1000);
+ while ((MCHBAR8(0x130) & 0x1) != 0);
+}
+
+static void __attribute__((noinline))
+sdram_jedec(struct sys_info *s, u8 rank, u8 jmode, u16 jval)
+{
+ u32 reg32;
+
+ reg32 = jval << 3;
+ reg32 |= rank * 0x8000000;
+ MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | jmode;
+ read32((void *)reg32);
+ barrier();
+ hpet_udelay(1); // 1us
+}
+
+static void sdram_zqcl(struct sys_info *s)
+{
+ if (s->boot_path == BOOT_PATH_RESUME) {
+ MCHBAR32(0x260) = MCHBAR32(0x260) | (1 << 27);
+ MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0xe) | NORMAL_OP_CMD;
+ MCHBAR8(0x271) = MCHBAR8(0x271) & ~0x30;
+ MCHBAR32(0x268) = (MCHBAR32(0x268) & ~((1 << 30) | (1 << 31))) |
+ (1 << 30) | (1 << 31);
+ }
+}
+
+static void sdram_jedecinit(struct sys_info *s)
+{
+ u8 r, i, ch;
+ u16 reg16, mrs, rttnom;
+ struct jedeclist {
+ char debug[15];
+ u8 cmd;
+ u16 val;
+ };
+
+ struct jedeclist jedec[12] = {
+ { " NOP ", NOP_CMD, 0 },
+ { " PRE CHARGE ", PRE_CHARGE_CMD, 0 },
+ { " EMRS2 ", EMRS2_CMD, 0 },
+ { " EMRS3 ", EMRS3_CMD, 0 },
+ { " EMRS1 ", EMRS1_CMD, 0 },
+ { " DLL RESET ", MRS_CMD, (1 << 8) },
+ { " PRE CHARGE ", PRE_CHARGE_CMD, 0 },
+ { " AUTOREFRESH", CBR_CMD, 0 },
+ { " AUTOREFRESH", CBR_CMD, 0 },
+ { " INITIALISE ", MRS_CMD, 0 },
+ { " EMRS1 OCD ", EMRS1_CMD, (1 << 9) | (1 << 8) | (1 << 7) },
+ { " EMRS1 EXIT ", EMRS1_CMD, 0 }
+ };
+
+ mrs = (s->selected_timings.CAS << 4) |
+ ((s->selected_timings.tWR - 1) << 9) | (1 << 3) | (1 << 1) | 1;
+ rttnom = (1 << 2);
+ if (RANK_IS_POPULATED(s->dimms, 0, 0) && RANK_IS_POPULATED(s->dimms, 0, 2)) {
+ rttnom |= (1 << 6);
+ }
+
+ hpet_udelay(200); // 200us
+ reg16 = 0;
+ FOR_EACH_POPULATED_RANK(s->dimms, ch, r) {
+ for (i = 0; i < 12; i++) {
+ PRINTK_DEBUG("Rank:%d Jedec:%14s...", r, jedec[i].debug);
+ reg16 = jedec[i].val;
+ switch (jedec[i].cmd) {
+ case EMRS1_CMD:
+ reg16 |= rttnom;
+ break;
+ case MRS_CMD:
+ reg16 |= mrs;
+ break;
+ default:
+ break;
+ }
+ sdram_jedec(s, r, jedec[i].cmd, reg16);
+ PRINTK_DEBUG("done\n");
+ }
+ }
+}
+
+static void sdram_misc(struct sys_info *s)
+{
+ u32 reg32;
+
+ reg32 = 0;
+ reg32 |= (0x4 << 13);
+ reg32 |= (0x6 << 8);
+ MCHBAR32(0x274) = (MCHBAR32(0x274) & ~0x3ff00) | reg32;
+ MCHBAR8(0x274) = MCHBAR8(0x274) & ~(1 << 7);
+ MCHBAR8(0x26c) = MCHBAR8(0x26c) | 1;
+ if (s->boot_path != BOOT_PATH_RESUME) {
+ MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0xe) | NORMAL_OP_CMD;
+ MCHBAR8(0x271) = MCHBAR8(0x271) & ~0x30;
+ } else {
+ sdram_zqcl(s);
+ }
+}
+
+static void sdram_checkreset(void)
+{
+ u8 pmcon2, pmcon3, reset;
+
+ pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
+ pmcon3 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+ pmcon3 &= ~0x2;
+ if (pmcon2 & 0x80) {
+ pmcon2 &= ~0x80;
+ reset = 1;
+ } else {
+ pmcon2 |= 0x80;
+ reset = 0;
+ }
+ if (pmcon2 & 0x4) {
+ pmcon2 |= 0x4;
+ pmcon3 = (pmcon3 & ~0x30) | 0x30;
+ pmcon3 |= (1 << 3);
+ }
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, pmcon3);
+ if (reset) {
+ printk(BIOS_DEBUG, "Power cycle reset...\n");
+ outb(0xe, 0xcf9);
+ }
+}
+
+static void sdram_dradrb(struct sys_info *s)
+{
+ u8 i, reg8, ch, r;
+ u32 reg32, ind, c0dra, c0drb, dra;
+ u16 addr;
+ i = 0;
+ u8 dratab[2][2][2][4] =
+ {{
+ {
+ {0xff, 0xff, 0xff, 0xff},
+ {0xff, 0x00, 0x02, 0xff}
+ },
+ {
+ {0xff, 0x01, 0xff, 0xff},
+ {0xff, 0x03, 0xff, 0x06}
+ }
+ },
+ {
+ {
+ {0xff, 0xff, 0xff, 0xff},
+ {0xff, 0x04, 0x06, 0x08}
+ },
+ {
+ {0xff, 0xff, 0xff, 0xff},
+ {0x05, 0x07, 0x09, 0xff}
+ }
+ }};
+
+ u8 dradrb[10][6] = {
+ //Row Col Bank Width DRB
+ {0x01, 0x01, 0x00, 0x08, 0, 0x04},
+ {0x01, 0x00, 0x00, 0x10, 0, 0x02},
+ {0x02, 0x01, 0x00, 0x08, 1, 0x08},
+ {0x01, 0x01, 0x00, 0x10, 1, 0x04},
+ {0x01, 0x01, 0x01, 0x08, 1, 0x08},
+ {0x00, 0x01, 0x01, 0x10, 1, 0x04},
+ {0x02, 0x01, 0x01, 0x08, 2, 0x10},
+ {0x01, 0x01, 0x01, 0x10, 2, 0x08},
+ {0x03, 0x01, 0x01, 0x08, 3, 0x20},
+ {0x02, 0x01, 0x01, 0x10, 3, 0x10},
+ };
+
+ reg32 = 0;
+ FOR_EACH_POPULATED_RANK(s->dimms, ch, r) {
+ i = r / 2;
+ PRINTK_DEBUG("RANK %d PRESENT\n", r);
+ dra = dratab[s->dimms[i].banks]
+ [s->dimms[i].width]
+ [s->dimms[i].cols - 9]
+ [s->dimms[i].rows - 12];
+
+ if (s->dimms[i].banks == 1) {
+ dra |= (1 << 7);
+ }
+ reg32 |= (dra << (r*8));
+ }
+ MCHBAR32(0x208) = reg32;
+ c0dra = reg32;
+ PRINTK_DEBUG("C0DRA = 0x%08x\n", c0dra);
+
+ reg32 = 0;
+ FOR_EACH_POPULATED_RANK(s->dimms, ch, r) {
+ reg32 |= (1 << r);
+ }
+ reg8 = (u8)(reg32 << 4) & 0xf0;
+ MCHBAR8(0x262) = (MCHBAR8(0x262) & ~0xf0) | reg8;
+ if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) ||
+ ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) {
+ MCHBAR8(0x260) = MCHBAR8(0x260) | 1;
+ }
+
+ addr = 0x200;
+ c0drb = 0;
+ FOR_EACH_RANK(ch, r) {
+ IF_RANK_POPULATED(s->dimms, ch, r) {
+ ind = (c0dra >> (8*r)) & 0x7f;
+ c0drb = (u16)(c0drb + dradrb[ind][5]);
+ s->channel_capacity[0] += dradrb[ind][5] << 6;
+ }
+ MCHBAR16(addr) = c0drb;
+ addr += 2;
+ }
+ printk(BIOS_DEBUG, "Total memory = %dMB\n", s->channel_capacity[0]);
+}
+
+static u8 sampledqs(u32 dqshighaddr, u32 strobeaddr, u8 highlow, u8 count)
+{
+ volatile u32 strobedata;
+ u8 dqsmatches = 1;
+ while (count--) {
+ MCHBAR8(0x5d8) = MCHBAR8(0x5d8) & ~0x2;
+ hpet_udelay(1);
+ MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x2;
+ hpet_udelay(1);
+ barrier();
+ strobedata = read32((void*)strobeaddr);
+ barrier();
+ hpet_udelay(1);
+
+ if (((MCHBAR8(dqshighaddr) & 0x40) >> 6) != highlow) {
+ dqsmatches = 0;
+ }
+ }
+
+ return dqsmatches;
+}
+
+static void rcvenclock(u8 *coarse, u8 *medium, u8 bytelane)
+{
+ if (*medium < 3) {
+ (*medium)++;
+ MCHBAR16(0x58c) = (MCHBAR16(0x58c) & (u16)(~(0x3 << (bytelane*2))))
+ | (*medium << (bytelane*2));
+ } else {
+ *medium = 0;
+ (*coarse)++;
+ MCHBAR32(0x248) = (MCHBAR32(0x248) & ~0xf0000) | (*coarse << 16);
+ MCHBAR16(0x58c) = (MCHBAR16(0x58c) & (u16)(~0x3 << (bytelane*2)))
+ | (*medium << (bytelane*2));
+ }
+}
+
+static void sdram_rcven(struct sys_info *s)
+{
+ u8 curcoarse, savecoarse;
+ u8 curmedium, savemedium;
+ u8 pi, savepi;
+ u8 bytelane;
+ u8 bytelanecoarse[8] = { 0 };
+ u8 minbytelanecoarse = 0xff;
+ u8 bytelaneoffset;
+ u8 maxbytelane = 8;
+ u32 strobeaddr = (RANK_IS_POPULATED(s->dimms, 0, 0)) ? 0 : 2*128*1024*1024;
+ u32 dqshighaddr;
+
+ MCHBAR8(0x5d8) = MCHBAR8(0x5d8) & ~0xc;
+ MCHBAR8(0x5dc) = MCHBAR8(0x5dc) & ~0x80;
+
+ PRINTK_DEBUG("rcven 0\n");
+ for (bytelane = 0; bytelane < maxbytelane; bytelane++) {
+ PRINTK_DEBUG("rcven bytelane %d\n", bytelane);
+//trylaneagain:
+ dqshighaddr = 0x561 + (bytelane << 2);
+
+ curcoarse = s->selected_timings.CAS + 1;
+ pi = 0;
+ curmedium = 0;
+
+ MCHBAR32(0x248) = (MCHBAR32(0x248) & ~0xf0000) | (curcoarse << 16);
+ MCHBAR16(0x58c) = (MCHBAR16(0x58c) & (u16)(~(0x3 << (bytelane*2))))
+ | (curmedium << (bytelane*2));
+ MCHBAR8(0x560+bytelane*4) = MCHBAR8(0x560+bytelane*4) & ~0x3f;
+
+ savecoarse = curcoarse;
+ savemedium = curmedium;
+ savepi = pi;
+
+ PRINTK_DEBUG("rcven 0.1\n");
+
+ //MCHBAR16(0x588) = (MCHBAR16(0x588) & (u16)~(0x3 << (bytelane*2))) | (1 << (bytelane*2)); // XXX comment out
+
+ while (sampledqs(dqshighaddr, strobeaddr, 0, 3) == 0) {
+ //printk(BIOS_DEBUG, "coarse=%d medium=%d\n", curcoarse, curmedium);
+ rcvenclock(&curcoarse, &curmedium, bytelane);
+ if (curcoarse > 0xf) {
+ PRINTK_DEBUG("Error: coarse > 0xf\n");
+ //goto trylaneagain;
+ break;
+ }
+ }
+ PRINTK_DEBUG("rcven 0.2\n");
+
+ savecoarse = curcoarse;
+ savemedium = curmedium;
+ rcvenclock(&curcoarse, &curmedium, bytelane);
+
+ while (sampledqs(dqshighaddr, strobeaddr, 1, 3) == 0) {
+ savecoarse = curcoarse;
+ savemedium = curmedium;
+ rcvenclock(&curcoarse, &curmedium, bytelane);
+ if (curcoarse > 0xf) {
+ PRINTK_DEBUG("Error: coarse > 0xf\n");
+ //goto trylaneagain;
+ break;
+ }
+ }
+
+ PRINTK_DEBUG("rcven 0.3\n");
+ curcoarse = savecoarse;
+ curmedium = savemedium;
+ MCHBAR32(0x248) = (MCHBAR32(0x248) & ~0xf0000) | (curcoarse << 16);
+ MCHBAR16(0x58c) = (MCHBAR16(0x58c) & (u16)(~(0x3 << bytelane*2)))
+ | (curmedium << (bytelane*2));
+
+ while (sampledqs(dqshighaddr, strobeaddr, 1, 3) == 0) {
+ savepi = pi;
+ pi++;
+ if (pi > s->maxpi) {
+ //if (s->nodll) {
+ pi = savepi = s->maxpi;
+ break;
+ //}
+ }
+ MCHBAR8(0x560 + bytelane*4) = (MCHBAR8(0x560 + bytelane*4)
+ & ~0x3f) | (pi << s->pioffset);
+ }
+ PRINTK_DEBUG("rcven 0.4\n");
+
+ pi = savepi;
+ MCHBAR8(0x560 + bytelane*4) = (MCHBAR8(0x560 + bytelane*4) & ~0x3f)
+ | (pi << s->pioffset);
+ rcvenclock(&curcoarse, &curmedium, bytelane);
+ if (sampledqs(dqshighaddr, strobeaddr, 1, 1) == 0) {
+ PRINTK_DEBUG("Error: DQS not high\n");
+ //goto trylaneagain;
+ }
+ PRINTK_DEBUG("rcven 0.5\n");
+ while (sampledqs(dqshighaddr, strobeaddr, 0, 3) == 0) {
+ curcoarse--;
+ MCHBAR32(0x248) = (MCHBAR32(0x248) & ~0xf0000)
+ | (curcoarse << 16);
+ if (curcoarse == 0) {
+ PRINTK_DEBUG("Error: DQS didnt hit 0\n");
+ break;
+ }
+ }
+
+ PRINTK_DEBUG("rcven 0.6\n");
+ rcvenclock(&curcoarse, &curmedium, bytelane);
+ s->pi[bytelane] = pi;
+ bytelanecoarse[bytelane] = curcoarse;
+ }
+
+ PRINTK_DEBUG("rcven 1\n");
+
+ bytelane = maxbytelane;
+ do {
+ bytelane--;
+ if (minbytelanecoarse > bytelanecoarse[bytelane]) {
+ minbytelanecoarse = bytelanecoarse[bytelane];
+ }
+ } while (bytelane != 0);
+
+ bytelane = maxbytelane;
+ do {
+ bytelane--;
+ bytelaneoffset = bytelanecoarse[bytelane] - minbytelanecoarse;
+ MCHBAR16(0x5fa) = (MCHBAR16(0x5fa) & (u16)(~(0x3 << (bytelane*2))))
+ | (bytelaneoffset << (bytelane*2));
+ } while (bytelane != 0);
+
+ MCHBAR32(0x248) = (MCHBAR32(0x248) & ~0xf0000) | (minbytelanecoarse << 16);
+
+ s->coarsectrl = minbytelanecoarse;
+ s->coarsedelay = MCHBAR16(0x5fa);
+ s->mediumphase = MCHBAR16(0x58c);
+ s->readptrdelay = MCHBAR16(0x588);
+
+ PRINTK_DEBUG("rcven 2\n");
+ MCHBAR8(0x5d8) = MCHBAR8(0x5d8) & ~0xe;
+ MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x2;
+ MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x4;
+ MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x8;
+
+ MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80;
+ MCHBAR8(0x5dc) = MCHBAR8(0x5dc) & ~0x80;
+ MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80;
+ PRINTK_DEBUG("rcven 3\n");
+}
+
+static void sdram_mmap_regs(struct sys_info *s)
+{
+ bool reclaim;
+ u32 tsegsize;
+ u32 mmiosize;
+ u32 tom, tolud, touud, reclaimbase, reclaimlimit;
+ u32 gfxbase, gfxsize, gttbase, gttsize, tsegbase;
+ u16 ggc;
+ u16 ggc_to_uma[10] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256 };
+ u8 ggc_to_gtt[4] = { 0, 1, 0, 0 };
+
+ reclaimbase = 0;
+ reclaimlimit = 0;
+ ggc = pci_read_config16(PCI_DEV(0,0,0), GGC);
+ gfxsize = ggc_to_uma[(ggc & 0xf0) >> 4];
+ gttsize = ggc_to_gtt[(ggc & 0xc00) >> 8];
+ tom = s->channel_capacity[0];
+
+ tsegsize = 0x1; // 1MB
+ mmiosize = 0x400; // 1GB
+
+ reclaim = false;
+ tolud = MIN(0x1000 - mmiosize, tom);
+ if ((tom - tolud) > 0x40) {
+ // reclaim = true;
+ }
+ if (reclaim) {
+ tolud = tolud & ~0x3f;
+ tom = tom & ~0x3f;
+ reclaimbase = MAX(0x1000, tom);
+ reclaimlimit = reclaimbase + (MIN(0x1000, tom) - tolud) - 0x40;
+ }
+ touud = tom;
+ if (reclaim) {
+ touud = reclaimlimit + 0x40;
+ }
+
+ gfxbase = tolud - gfxsize;
+ gttbase = gfxbase - gttsize;
+ tsegbase = gttbase - tsegsize;
+
+ /* Program the regs */
+ pci_write_config16(PCI_DEV(0,0,0), 0xb0, (u16)(tolud << 4));
+ pci_write_config16(PCI_DEV(0,0,0), 0xa0, (u16)(tom >> 6));
+ if (reclaim) {
+ pci_write_config16(PCI_DEV(0,0,0), 0x98, (u16)(reclaimbase >> 6));
+ pci_write_config16(PCI_DEV(0,0,0), 0x9a, (u16)(reclaimlimit >> 6));
+ }
+ pci_write_config16(PCI_DEV(0,0,0), 0xa2, (u16)(touud));
+ pci_write_config32(PCI_DEV(0,0,0), 0xa4, gfxbase << 20);
+ pci_write_config32(PCI_DEV(0,0,0), 0xa8, gttbase << 20);
+ pci_write_config32(PCI_DEV(0,0,0), 0xac, tsegbase << 20);
+}
+
+static void sdram_enhancedmode(struct sys_info *s)
+{
+ u8 reg8, ch, r, j, i;
+ u32 mask32, reg32;
+ MCHBAR8(0x246) = MCHBAR8(0x246) | 1;
+ MCHBAR8(0x269 + 3) = MCHBAR8(0x269 + 3) | 1;
+ mask32 = (0x1f << 15) | (0x1f << 10) | (0x1f << 5) | 0x1f;
+ reg32 = (0x1e << 15) | (0x10 << 10) | (0x1e << 5) | 0x10;
+ MCHBAR32(0x120) = (MCHBAR32(0x120) & ~mask32) | reg32;
+ MCHBAR8(0x288 + 1) = 0x2;
+ MCHBAR16(0x288 + 2) = 0x0804;
+ MCHBAR16(0x288 + 4) = 0x2010;
+ MCHBAR8(0x288 + 6) = 0x40;
+ MCHBAR16(0x288 + 8) = 0x091c;
+ MCHBAR8(0x288 + 10) = 0xf2;
+ MCHBAR8(0x241) = MCHBAR8(0x241) | 1;
+ MCHBAR8(0x243) = MCHBAR8(0x243) | 1;
+ MCHBAR16(0x272) = MCHBAR16(0x272) | 0x100;
+
+ reg8 = pci_read_config8(PCI_DEV(0,0,0), 0xf0);
+ pci_write_config8(PCI_DEV(0,0,0), 0xf0, reg8 | 1);
+ MCHBAR32(0xfa0) = 0x00000002;
+ MCHBAR32(0xfa4) = 0x20310002;
+ MCHBAR32(0x24) = 0x02020302;
+ MCHBAR32(0x30) = 0x001f1806;
+ MCHBAR32(0x34) = 0x01102800;
+ MCHBAR32(0x38) = 0x07000000;
+ MCHBAR32(0x3c) = 0x01014010;
+ MCHBAR32(0x40) = 0x0f038000;
+ reg8 = pci_read_config8(PCI_DEV(0,0,0), 0xf0);
+ pci_write_config8(PCI_DEV(0,0,0), 0xf0, reg8 & ~1);
+
+ u32 nranks, curranksize, maxranksize, maxdra, dra;
+ u8 rankmismatch, dramismatch;
+ u8 drbtab[10] = { 0x4, 0x2, 0x8, 0x4, 0x8, 0x4, 0x10, 0x8, 0x20, 0x10 };
+
+ nranks = 0;
+ curranksize = 0;
+ maxranksize = 0;
+ maxdra = 0;
+ rankmismatch = 0;
+ dramismatch = 0;
+ FOR_EACH_POPULATED_RANK(s->dimms, ch, r) {
+ nranks++;
+ dra = (u8) ((MCHBAR32(0x208) >> (8*r)) & 0x7f);
+ curranksize = drbtab[dra];
+ if (maxranksize == 0) {
+ maxranksize = curranksize;
+ maxdra = dra;
+ }
+ if (curranksize != maxranksize) {
+ rankmismatch = 1;
+ }
+ if (dra != maxdra) {
+ dramismatch = 1;
+ }
+ }
+
+ reg8 = 0;
+ switch (nranks) {
+ case 4:
+ if (rankmismatch) {
+ reg8 = 0x64;
+ } else {
+ reg8 = 0xa4;
+ }
+ break;
+ case 1:
+ case 3:
+ reg8 = 0x64;
+ break;
+ case 2:
+ if (rankmismatch) {
+ reg8 = 0x64;
+ } else {
+ reg8 = 0x24;
+ }
+ break;
+ default:
+ die("Invalid number of ranks found, halt\n");
+ break;
+ }
+ MCHBAR8(0x111) = (MCHBAR8(0x111) & ~0xfc) | (reg8 & 0xfc);
+ MCHBAR32(0xd0) = MCHBAR32(0xd0) & ~0x80000000;
+
+ MCHBAR32(0x28) = 0xf;
+ MCHBAR8(0x2c4) = MCHBAR8(0x2c4) | 1;
+
+ MCHBAR32(0x3c) = MCHBAR32(0x3c) & ~0xe000000;
+ MCHBAR32(0x40) = (MCHBAR32(0x40) & ~0xc0000) | 0x40000;
+ u32 clkcx[2][2][3] = {
+ {
+ {0, 0x0c080302, 0x08010204}, // 667
+ {0x02040000, 0x08100102, 0}
+ },
+ {
+ {0x18000000, 0x3021060c, 0x20010208},
+ {0, 0x0c090306, 0} // 800
+ }
+ };
+ j = s->selected_timings.fsb_clock;
+ i = s->selected_timings.mem_clock;
+
+ MCHBAR32(0x708) = clkcx[j][i][0];
+ MCHBAR32(0x70c) = clkcx[j][i][1];
+ MCHBAR32(0x6dc) = clkcx[j][i][2];
+ MCHBAR8(0x40) = MCHBAR8(0x40) & ~0x2;
+}
+
+static void sdram_periodic_rcomp(void)
+{
+ MCHBAR8(0x130) = MCHBAR8(0x130) & ~0x2;
+ while ((MCHBAR32(0x130) & 0x80000000) > 0) {
+ ;
+ }
+ MCHBAR16(0x1b4) = (MCHBAR16(0x1b4) & ~0x3000);
+
+ MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80;
+ MCHBAR16(0x170) = (MCHBAR16(0x170) & ~0xf) | 0x9;
+
+ MCHBAR8(0x130) = MCHBAR8(0x130) | 0x82;
+}
+
+#if 0
+static u8 dynamic_pattern(size_t memloc, u8 inv)
+{
+ u8 a, b, t, aorb, left, total;
+
+ a = 0xff;
+ a &= ~((u8)((1 << ((memloc >> 13) & 0xf)) >> 1));
+ b = ~a;
+
+ if (memloc & 0x100) {
+ t = a;
+ a = b;
+ b = t;
+ }
+
+ left = (u8)((memloc >> 11) & 0x3) + 1;
+ total = left + (u8)((memloc >> 9) & 0x3) + 1;
+ aorb = a;
+ if ((((memloc & 0xff) >> 3) % total) >= left) {
+ aorb = b;
+ }
+
+ if (inv) {
+ return ~aorb;
+ } else {
+ return aorb;
+ }
+}
+
+static void write_pattern(size_t addr)
+{
+ volatile u8 mem8;
+ u16 count;
+ size_t tmpaddr;
+
+ for (count = 0; count < 1024; count++) {
+ tmpaddr = addr + count;
+ mem8 = dynamic_pattern(tmpaddr, 1) & 0xff;
+ write8((u8*)tmpaddr, mem8);
+ //barrier();
+ }
+}
+
+static void wpcache_flush(u32 cacheaddr)
+{
+ u32 flush;
+ for (flush = cacheaddr; flush < (cacheaddr + 0x2000); flush+=64) {
+ asm (
+ "movl %0, %%eax"
+ :
+ :"r"(flush)
+ :
+ );
+ asm (
+ "clflush (%eax)"
+ );
+ }
+}
+
+static void wpcache_enable(u32 cacheaddr)
+{
+ asm (
+ "movl %0, %%eax;"
+ :
+ :"r"(cacheaddr)
+ :
+ );
+ asm (
+ "orl 0x5, %eax\n\t"
+ "xorl %edx, %edx\n\t"
+ "movl $0x206, %ecx\n\t"
+ "wrmsr\n\t"
+ "movl $((~(0x2000 - 1)) | 0x800), %eax\n\t"
+ "movl $0x0f, %edx\n\t"
+ "movl $0x206, %ecx\n\t"
+ "wrmsr"
+ );
+}
+
+static void wpcache_disable(void)
+{
+ asm (
+ "xorl %eax, %eax\n\t"
+ "xorl %edx, %edx\n\t"
+ "movl $0x206, %ecx\n\t"
+ "wrmsr\n\t"
+ "movl $0x206, %ecx\n\t"
+ "wrmsr"
+ );
+}
+
+static u8 is_readaligned(size_t addr, u8 vref)
+{
+ u8 status = 1;
+ volatile u8 mem8;
+ u32 datacnt;
+ u16 retry;
+ u32 memloc;
+ u32 cacheloc;
+ u8 tmpdata;
+
+ MCHBAR8(0x1b6) = (MCHBAR8(0x1b6) & ~0x3f) | vref;
+ for (retry = 0; retry < 3; retry++) {
+ cacheloc = addr;
+ for (datacnt = 0; datacnt < 1024; datacnt++) {
+ memloc = addr + datacnt;
+
+ if (cacheloc <= memloc) {
+ wpcache_enable(cacheloc);
+ wpcache_flush(cacheloc);
+ cacheloc += 0x2000;
+ }
+
+ mem8 = read8((void*)memloc);
+ barrier();
+ tmpdata = dynamic_pattern(memloc, 1);
+ status = 1;
+ if (mem8 != tmpdata) {
+ status = 0;
+ wpcache_disable();
+ return status;
+ }
+ }
+ }
+ wpcache_disable();
+ return status;
+}
+
+static void sdram_vrefmargin(struct sys_info *s)
+{
+ u8 i, rank, temp, vrefplus, vrefminus, vrefval;
+ size_t strobeaddr;
+ u8 vrefplusval[4] = { 0x7, 0xe, 0x15, 0x1c };
+ u8 vrefminusval[4] = { 0x27, 0x2e, 0x35, 0x3c };
+
+ vrefminus = vrefplus = 0;
+
+ MCHBAR16(0x1b6) = MCHBAR16(0x1b6) & ~0x100;
+
+ if (RANK_IS_POPULATED(s->dimms, 0, 0)) {
+ rank = 0;
+ } else {
+ rank = 2;
+ }
+ strobeaddr = rank*128*1024*1024;
+ write_pattern(strobeaddr);
+
+ temp = 0;
+ for (i = 0; i < 4; i++) {
+ temp = is_readaligned(strobeaddr, vrefplusval[i]);
+ if (temp) {
+ vrefplus += temp;
+ } else {
+ break;
+ }
+ }
+
+ temp = 0;
+ for (i = 0; i < 4; i++) {
+ temp = is_readaligned(strobeaddr, vrefminusval[i]);
+ if (temp) {
+ vrefminus += temp;
+ } else {
+ break;
+ }
+ }
+
+ if ((vrefplus == 0) && (vrefminus == 0)) {
+ PRINTK_DEBUG("Error: vref not aligned\n");
+ }
+ u8 vreflut[5][5] = { {0x00, 0x03, 0x04, 0x05, 0x05},
+ {0x23, 0x00, 0x03, 0x04, 0x05},
+ {0x24, 0x23, 0x00, 0x03, 0x04},
+ {0x25, 0x24, 0x23, 0x00, 0x03},
+ {0x25, 0x25, 0x24, 0x23, 0x00}};
+ vrefval = vreflut[vrefminus][vrefplus];
+
+ MCHBAR8(0x1b6) = (MCHBAR8(0x1b6) & ~0x3f) | vrefval;
+}
+#endif
+
+static void sdram_new_trd(struct sys_info *s)
+{
+ u8 pidelay, i, j, k, cc, trd_perphase[5];
+ u8 bypass, freqgb, trd, reg8, txfifo, cas;
+ u32 reg32, datadelay, tio, rcvendelay, maxrcvendelay;
+ u16 tmclk, thclk, buffertocore, postcalib;
+ u8 txfifo_lut[8] = { 0, 7, 6, 5, 2, 1, 4, 3 };
+ u16 trd_adjust[2][2][5] = {
+ {
+ {3000, 3000, 0,0,0},
+ {1000,2000,3000,1500,2500}
+ },
+ {
+ {2000,1000,3000,0,0},
+ {2500, 2500, 0,0,0}
+ }};
+
+ freqgb = 110;
+ buffertocore = 5000;
+ cas = s->selected_timings.CAS;
+ postcalib = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 1250 : 500;
+ tmclk = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 3000 : 2500;
+ tmclk = tmclk * 100 / freqgb;
+ thclk = (s->selected_timings.fsb_clock == FSB_CLOCK_667MHz) ? 6000 : 5000;
+ switch (s->selected_timings.mem_clock) {
+ case MEM_CLOCK_667MHz:
+ if (s->selected_timings.fsb_clock == FSB_CLOCK_667MHz) {
+ cc = 2;
+ } else {
+ cc = 3;
+ }
+ break;
+ default:
+ case MEM_CLOCK_800MHz:
+ if (s->selected_timings.fsb_clock == FSB_CLOCK_667MHz) {
+ cc = 5;
+ } else {
+ cc = 2;
+ }
+ break;
+ }
+ tio = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 2700 : 3240;
+ maxrcvendelay = 0;
+ pidelay = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 24 : 20;
+
+ for (i = 0; i < 8; i++) {
+ rcvendelay = ((u32)((s->coarsedelay >> (i << 1)) & 0x3) * (u32)(tmclk));
+ rcvendelay += ((u32)((s->readptrdelay >> (i << 1)) & 0x3) * (u32)(tmclk) / 2);
+ rcvendelay += ((u32)((s->mediumphase >> (i << 1)) & 0x3) * (u32)(tmclk) / 4);
+ rcvendelay += (u32)(pidelay * s->pi[i]);
+ maxrcvendelay = MAX(maxrcvendelay, rcvendelay);
+ }
+
+ if ((MCHBAR8(0xc54+3) == 0xff) && (MCHBAR8(0xc08) & 0x80)) {
+ bypass = 1;
+ } else {
+ bypass = 0;
+ }
+
+ txfifo = 0;
+ reg8 = (MCHBAR8(0x188) & 0xe) >> 1;
+ txfifo = txfifo_lut[reg8] & 0x7;
+
+ datadelay = tmclk * (2*txfifo + 4*s->coarsectrl + 4*(bypass-1) + 13) / 4
+ + tio + maxrcvendelay + pidelay + buffertocore + postcalib;
+ if (s->async) {
+ datadelay += tmclk / 2;
+ }
+
+ j = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 0 : 1;
+ k = (s->selected_timings.fsb_clock == FSB_CLOCK_667MHz) ? 0 : 1;
+
+ if (j == 0 && k == 0) {
+ datadelay -= 3084;
+ }
+
+ trd = 0;
+ for (i = 0; i < cc; i++) {
+ reg32 = datadelay - (trd_adjust[k][j][i] * 100 / freqgb);
+ trd_perphase[i] = (u8)(reg32 / thclk) - 2;
+ trd_perphase[i] += 1;
+ if (trd_perphase[i] > trd) {
+ trd = trd_perphase[i];
+ }
+ }
+
+ MCHBAR16(0x248) = (MCHBAR16(0x248) & ~0x1f00) | (trd << 8);
+}
+
+static void sdram_powersettings(struct sys_info *s)
+{
+ u8 j;
+ u32 reg32;
+
+ /* Thermal sensor */
+ MCHBAR8(0x3808) = 0x9b;
+ MCHBAR32(0x380c) = (MCHBAR32(0x380c) & ~0x00ffffff) | 0x1d00;
+ MCHBAR8(0x3814) = 0x08;
+ MCHBAR8(0x3824) = 0x00;
+ MCHBAR8(0x3809) = (MCHBAR8(0x3809) & ~0xf) | 0x4;
+ MCHBAR8(0x3814) = (MCHBAR8(0x3814) & ~1) | 1;
+ MCHBAR8(0x3812) = (MCHBAR8(0x3812) & ~0x80) | 0x80;
+
+ /* Clock gating */
+ MCHBAR32(0xf18) = MCHBAR32(0xf18) & ~0x00040001;
+ MCHBAR8(0xfac+3) = MCHBAR8(0xfac+3) & ~0x80;
+ MCHBAR8(0xff8+3) = MCHBAR8(0xff8+3) & ~0x80;
+ MCHBAR16(0xff0) = MCHBAR16(0xff0) & ~0x1fff;
+ MCHBAR32(0xfb0) = MCHBAR32(0xfb0) & ~0x0001ffff;
+ MCHBAR16(0x48) = (MCHBAR16(0x48) & ~0x03ff) & 0x6;
+ MCHBAR32(0x20) = (MCHBAR32(0x20) & ~0xffffffff) | 0x20;
+ MCHBAR8(0xd14) = MCHBAR8(0xd14) & ~1;
+ MCHBAR8(0x239) = s->selected_timings.CAS - 1 + 0x15;
+ MCHBAR16(0x2d1) = (MCHBAR16(0x2d1) & ~0x07fc) | 0x40;
+ MCHBAR16(0x6d1) = (MCHBAR16(0x6d1) & ~0x0fff) | 0xd00;
+ MCHBAR16(0x210) = MCHBAR16(0x210) & ~0x0d80;
+ MCHBAR16(0xf6c+2) = 0xffff;
+
+ /* Sequencing */
+ MCHBAR32(0x14) = (MCHBAR32(0x14) & ~0x1fffffff) | 0x1f643fff;
+ MCHBAR32(0x18) = (MCHBAR32(0x18) & ~0xffffff7f) | 0x02010000;
+ MCHBAR16(0x1c) = (MCHBAR16(0x1c) & ~0x7000) | (0x3 << 12);
+
+ /* Power */
+ MCHBAR32(0x1104) = (MCHBAR32(0x1104) & ~0xffff0003) | 0x10100000;
+ MCHBAR32(0x1108) = (MCHBAR32(0x1108) & ~0x0001bff7) | 0x00000078;
+ if (s->selected_timings.fsb_clock == FSB_CLOCK_667MHz) {
+ MCHBAR16(0x110c) = (MCHBAR16(0x110c) & ~0x03ff) | 0xc8;
+ } else {
+ MCHBAR16(0x110c) = (MCHBAR16(0x110c) & ~0x03ff) | 0x100;
+ }
+ j = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 0 : 1;
+
+ MCHBAR32(0x1110) = (MCHBAR32(0x1110) & ~0x1fff37f) | 0x10810700;
+ MCHBAR8(0x1114) = (MCHBAR8(0x1114) & ~0x07) | 1;
+ MCHBAR8(0x1124) = MCHBAR8(0x1124) & ~0x02;
+
+ u16 ddr2lut[2][4][2] = {{
+ {0x0000, 0x0000},
+ {0x019A, 0x0039},
+ {0x0099, 0x1049},
+ {0x0000, 0x0000}
+ },
+ {
+ {0x0000, 0x0000},
+ {0x019A, 0x0039},
+ {0x0099, 0x1049},
+ {0x0099, 0x2159}
+ }};
+
+ MCHBAR16(0x23c) = 0x7a89;
+ MCHBAR8(0x117) = 0xaa;
+ MCHBAR16(0x118) = ddr2lut[j][s->selected_timings.CAS - 3][1];
+ MCHBAR16(0x115) = (MCHBAR16(0x115) & ~0x7fff) | ddr2lut[j]
+ [s->selected_timings.CAS - 3][0];
+ MCHBAR16(0x210) = (MCHBAR16(0x210) & ~0xf000) | 0xf000;
+ MCHBAR8(0x2c02) = (MCHBAR8(0x2c02) & ~0x77) | (4 << 4 | 4);
+ if (s->nodll) {
+ reg32 = 0x30000000;
+ } else {
+ reg32 = 0;
+ }
+ MCHBAR32(0x2c0) = (MCHBAR32(0x2c0) & ~0x0f000000) | 0x20000000 | reg32;
+ MCHBAR32(0x2d1) = (MCHBAR32(0x2d1) & ~0x00f00000) | 0x00f00000;
+ MCHBAR32(0x6d0) = (MCHBAR32(0x6d0) & ~0x001ff000) | (0xbf << 20);
+ MCHBAR16(0x610) = (MCHBAR16(0x610) & ~0x1f7f) | (0xb << 8) | (7 << 4) | 0xb;
+ MCHBAR16(0x612) = 0x3264;
+ MCHBAR16(0x614) = (MCHBAR16(0x614) & ~0x3f3f) | (0x14 << 8) | 0xa;
+
+ MCHBAR32(0x6c0) = MCHBAR32(0x6c0) | 0x80002000;
+}
+
+static void sdram_programddr(void)
+{
+ MCHBAR16(0x6d1) = (MCHBAR16(0x6d1) & ~0x03ff) | 0x100;
+ MCHBAR16(0x210) = (MCHBAR16(0x210) & ~0x003f) | 0x10;
+ MCHBAR16(0x2d1) = (MCHBAR16(0x2d1) & ~0x7000) | 0x2000;
+ MCHBAR8(0x180) = MCHBAR8(0x180) & ~0xe;
+ MCHBAR8(0x18c) = MCHBAR8(0x18c) & ~0xc;
+ MCHBAR8(0x561) = MCHBAR8(0x561) & ~0xe;
+ MCHBAR8(0x565) = MCHBAR8(0x565) & ~0xe;
+ MCHBAR8(0x569) = MCHBAR8(0x569) & ~0xe;
+ MCHBAR8(0x56d) = MCHBAR8(0x56d) & ~0xe;
+ MCHBAR8(0x571) = MCHBAR8(0x571) & ~0xe;
+ MCHBAR8(0x575) = MCHBAR8(0x575) & ~0xe;
+ MCHBAR8(0x579) = MCHBAR8(0x579) & ~0xe;
+ MCHBAR8(0x57d) = MCHBAR8(0x57d) & ~0xe;
+ MCHBAR8(0x18c) = MCHBAR8(0x18c) & ~0x2;
+ MCHBAR16(0x1b4) = MCHBAR16(0x1b4) & ~0x400;
+ MCHBAR16(0x210) = MCHBAR16(0x210) & ~0xdc0;
+ MCHBAR8(0x239) = MCHBAR8(0x239) & ~0x80;
+ MCHBAR32(0x2c0) = MCHBAR32(0x2c0) & ~(1 << 22);
+ MCHBAR16(0x2d1) = MCHBAR16(0x2d1) & ~0x80fc;
+ MCHBAR16(0x6d1) = MCHBAR16(0x6d1) & ~0xc00;
+ MCHBAR8(0x180) = MCHBAR8(0x180) & ~0xd;
+ MCHBAR8(0x561) = MCHBAR8(0x561) & ~1;
+ MCHBAR8(0x565) = MCHBAR8(0x565) & ~1;
+ MCHBAR8(0x569) = MCHBAR8(0x569) & ~1;
+ MCHBAR8(0x56d) = MCHBAR8(0x56d) & ~1;
+ MCHBAR8(0x571) = MCHBAR8(0x571) & ~1;
+ MCHBAR8(0x575) = MCHBAR8(0x575) & ~1;
+ MCHBAR8(0x579) = MCHBAR8(0x579) & ~1;
+ MCHBAR8(0x57d) = MCHBAR8(0x57d) & ~1;
+ MCHBAR32(0x248) = (MCHBAR32(0x248) & ~0x700000) | (0x3 << 20);
+ MCHBAR32(0x2c0) = MCHBAR32(0x2c0) & ~0x100000;
+ MCHBAR8(0x592) = MCHBAR8(0x592) | 0x1e;
+ MCHBAR8(0x2c15) = MCHBAR8(0x2c15) | 0x3;
+ MCHBAR32(0x62c) = (MCHBAR32(0x62c) & ~0xc000000) | 0x4000000;
+ MCHBAR16(0x248) = MCHBAR16(0x248) | 0x6000;
+ MCHBAR32(0x260) = MCHBAR32(0x260) | 0x10000;
+ MCHBAR8(0x2c0) = MCHBAR8(0x2c0) | 0x10;
+ MCHBAR32(0x2d0) = MCHBAR32(0x2d0) | (0xf << 24);
+ MCHBAR8(0x189) = MCHBAR8(0x189) | 0x7;
+ MCHBAR8(0x592) = MCHBAR8(0x592) | 0xc0;
+ MCHBAR8(0x124) = MCHBAR8(0x124) | 0x7;
+ MCHBAR16(0x12a) = (MCHBAR16(0x12a) & ~0xffff) | 0x0080;
+ MCHBAR8(0x12c) = (MCHBAR8(0x12c) & ~0xff) | 0x10;
+ MCHBAR16(0x2c0) = MCHBAR16(0x2c0) | 0x1e0;
+ MCHBAR8(0x189) = MCHBAR8(0x189) | 0x18;
+ MCHBAR8(0x193) = MCHBAR8(0x193) | 0xd;
+ MCHBAR16(0x212) = MCHBAR16(0x212) | 0xa3f;
+ MCHBAR8(0x248) = MCHBAR8(0x248) | 0x3;
+ MCHBAR8(0x268) = (MCHBAR8(0x268) & ~0xff) | 0x4a;
+ MCHBAR8(0x2c4) = MCHBAR8(0x2c4) & ~0x60;
+ MCHBAR16(0x592) = MCHBAR16(0x592) | 0x321;
+}
+
+static void sdram_programdqdqs(struct sys_info *s)
+{
+ u16 mdclk, tpi, refclk, dqdqs_out, dqdqs_outdelay, dqdqs_delay;
+ u32 coretomcp, txdelay, tmaxunmask, tmaxpi;
+ u8 repeat, halfclk, feature, reg8, push;
+ u16 cwb, pimdclk;
+ u32 reg32;
+ u8 txfifotab[8] = { 0, 7, 6, 5, 2, 1, 4, 3 };
+
+ tpi = 3000;
+ dqdqs_out = 4382;
+ dqdqs_outdelay = 5083;
+ dqdqs_delay = 4692;
+ coretomcp = 0;
+ txdelay = 0;
+ halfclk = 0;
+ tmaxunmask = 0;
+ tmaxpi = 0;
+ repeat = 2;
+ feature = 0;
+ cwb = 0;
+ pimdclk = 0;
+ reg32 = 0;
+ push = 0;
+ reg8 = 0;
+
+ mdclk = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 3000 : 2500;
+ refclk = 3000 - mdclk;
+
+ coretomcp = ((MCHBAR8(0x246) >> 2) & 0x3) + 1;
+ coretomcp *= mdclk;
+
+ reg8 = (MCHBAR8(0x188) & 0xe) >> 1;
+
+ while (repeat) {
+ txdelay = mdclk * (
+ ((MCHBAR16(0x220) >> 8) & 0x7) +
+ (MCHBAR8(0x24d) & 0xf) +
+ (MCHBAR8(0x24e) & 0x1)
+ ) +
+ txfifotab[reg8]*(mdclk/2) +
+ coretomcp +
+ refclk +
+ cwb;
+ halfclk = (MCHBAR8(0x5d9) >> 1) & 0x1;
+ if (halfclk) {
+ txdelay -= mdclk / 2;
+ reg32 = dqdqs_outdelay + coretomcp - mdclk / 2;
+ } else {
+ reg32 = dqdqs_outdelay + coretomcp;
+ }
+
+ tmaxunmask = txdelay - mdclk - dqdqs_out;
+ tmaxpi = tmaxunmask - tpi;
+
+ if ((tmaxunmask >= reg32) && tmaxpi >= dqdqs_delay) {
+ if (repeat == 2) {
+ MCHBAR32(0x2c0) = MCHBAR32(0x2c0) & ~(1 << 23);
+ }
+ feature = 1;
+ repeat = 0;
+ } else {
+ repeat--;
+ MCHBAR32(0x2c0) = MCHBAR32(0x2c0) | (1 << 23);
+ cwb = 2 * mdclk;
+ }
+ }
+
+ if (!feature) {
+ MCHBAR8(0x2d1) = MCHBAR8(0x2d1) & ~0x3;
+ return;
+ }
+ MCHBAR8(0x2d1) = MCHBAR8(0x2d1) | 0x3;
+ MCHBAR16(0x210) = (MCHBAR16(0x210) & ~0xf000) | (pimdclk << 12);
+ MCHBAR8(0x2c02) = (MCHBAR8(0x2c02) & ~0x77) | (push << 4) | push;
+ MCHBAR32(0x2c0) = (MCHBAR32(0x2c0) & ~0xf000000) | 0x3000000;
+}
+
+/**
+ * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3
+ */
+void sdram_initialize(int boot_path, const u8 *spd_addresses)
+{
+ struct sys_info sysinfo;
+ u8 reg8;
+
+ PRINTK_DEBUG("Setting up RAM controller.\n");
+
+ memset(&sysinfo, 0, sizeof(sysinfo));
+
+ sysinfo.boot_path = boot_path;
+ sysinfo.spd_map[0] = spd_addresses[0];
+ sysinfo.spd_map[1] = spd_addresses[1];
+ sysinfo.spd_map[2] = spd_addresses[2];
+ sysinfo.spd_map[3] = spd_addresses[3];
+
+ sdram_read_spds(&sysinfo);
+
+ /* Choose Common Frequency */
+ sdram_detect_ram_speed(&sysinfo);
+
+ /* Determine smallest common tRAS, tRP, tRCD, etc */
+ sdram_detect_smallest_params(&sysinfo);
+
+ /* Enable HPET */
+ enable_hpet();
+ hpet_udelay(300000);
+
+ MCHBAR16(0xc1c) = MCHBAR16(0xc1c) | (1 << 15);
+
+ hpet_udelay(100000);
+
+ sdram_clk_crossing(&sysinfo);
+
+ sdram_checkreset();
+ PRINTK_DEBUG("Done checkreset\n");
+
+ sdram_clkmode(&sysinfo);
+ PRINTK_DEBUG("Done clkmode\n");
+
+ sdram_timings(&sysinfo);
+ PRINTK_DEBUG("Done timings (dqs dll enabled)\n");
+
+ sdram_dlltiming(&sysinfo);
+ PRINTK_DEBUG("Done dlltiming\n");
+
+ hpet_udelay(200000);
+
+ sdram_rcomp(&sysinfo);
+ PRINTK_DEBUG("Done RCOMP\n");
+
+ sdram_odt(&sysinfo);
+ PRINTK_DEBUG("Done odt\n");
+
+ while ((MCHBAR8(0x130) & 0x1) != 0);
+
+ sdram_mmap(&sysinfo);
+ PRINTK_DEBUG("Done mmap\n");
+
+ // Enable DDR IO buffer
+ MCHBAR8(0x5dd) = (MCHBAR8(0x5dd) & ~0x3f) | 0x8;
+ MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x1;
+
+ sdram_rcompupdate(&sysinfo);
+ PRINTK_DEBUG("Done RCOMP update\n");
+
+ MCHBAR8(0x40) = MCHBAR8(0x40) | 0x2;
+
+ if (sysinfo.boot_path != BOOT_PATH_RESUME) {
+ MCHBAR32(0x260) = MCHBAR32(0x260) | (1 << 27);
+ }
+
+ sdram_jedecinit(&sysinfo);
+ PRINTK_DEBUG("Done MRS\n");
+
+ sdram_misc(&sysinfo);
+ PRINTK_DEBUG("Done misc\n");
+
+ sdram_zqcl(&sysinfo);
+ PRINTK_DEBUG("Done zqcl\n");
+
+ if (sysinfo.boot_path != BOOT_PATH_RESUME) {
+ MCHBAR32(0x268) = MCHBAR32(0x268) | 0xc0000000;
+ }
+
+ sdram_dradrb(&sysinfo);
+ PRINTK_DEBUG("Done dradrb\n");
+
+ sdram_rcven(&sysinfo);
+ PRINTK_DEBUG("Done rcven\n");
+
+ //PRINTK_DEBUG("Start vref margin...");
+ //sdram_vrefmargin(&sysinfo);
+ //PRINTK_DEBUG("Done vref margin\n");
+
+ sdram_new_trd(&sysinfo);
+ PRINTK_DEBUG("Done tRD\n");
+
+ sdram_mmap_regs(&sysinfo);
+ PRINTK_DEBUG("Done mmap regs\n");
+
+ sdram_enhancedmode(&sysinfo);
+ PRINTK_DEBUG("Done enhanced mode\n");
+
+ sdram_powersettings(&sysinfo);
+ PRINTK_DEBUG("Done power settings\n");
+
+ sdram_programddr();
+ PRINTK_DEBUG("Done programming ddr\n");
+
+ sdram_programdqdqs(&sysinfo);
+ PRINTK_DEBUG("Done programming dqdqs\n");
+
+ sdram_periodic_rcomp();
+ PRINTK_DEBUG("Done periodic RCOMP\n");
+
+ /* Set init done */
+ MCHBAR32(0x268) = MCHBAR32(0x268) | 0x40000000;
+
+ /* Tell ICH7 that we're done */
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 & ~0x80);
+
+ /* Tell northbridge we're done */
+ reg8 = pci_read_config8(PCI_DEV(0,0,0), 0xf4);
+ pci_write_config8(PCI_DEV(0,0,0), 0xf4, reg8 | 1);
+
+#if 0
+ PRINTK_DEBUG("Start dummy write/reads...\n");
+ volatile u32 data;
+ u8 ch, r, bank;
+ u32 reg32;
+ u16 i;
+ FOR_EACH_POPULATED_RANK(sysinfo.dimms, ch, r) {
+ bank = i = 0;
+ for (bank = 0; bank < 8; bank++) {
+// for (i = 0; i < (1 << 12); i+=4) {
+ reg32 = (ch << 29) | (r*0x8000000) | (bank << 12) | i;
+ barrier();
+ write32((u32 *)reg32, 0xffffffff);
+ data = read32((u32 *)reg32);
+ PRINTK_DEBUG("Wrote ones: Read: [0x%08x]=0x%08x\n", reg32, data);
+ barrier();
+ write32((u32 *)reg32, 0x00000000);
+ data = read32((u32 *)reg32);
+ PRINTK_DEBUG("Wrote zeroes: Read: [0x%08x]=0x%08x\n", reg32, data);
+// }
+ }
+ }
+#endif
+
+ printk(BIOS_DEBUG, "RAM initialization finished.\n");
+}
diff --git a/src/northbridge/intel/pineview/raminit.h b/src/northbridge/intel/pineview/raminit.h
new file mode 100644
index 0000000..65da603
--- /dev/null
+++ b/src/northbridge/intel/pineview/raminit.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef RAMINIT_H
+#define RAMINIT_H
+
+#include "pineview.h"
+
+void sdram_initialize(int boot_path, const u8 *sdram_addresses);
+
+#endif /* RAMINIT_H */
1
0
Patch set updated for coreboot: southbridge/intel: Use i82801gx code for NM10
by Damien Zammit 20 Nov '15
by Damien Zammit 20 Nov '15
20 Nov '15
Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12431
-gerrit
commit ca02dc4d127556db8b162e0fba50e7df187829d7
Author: Damien Zammit <damien(a)zamaudio.com>
Date: Sat Nov 14 01:03:39 2015 +1100
southbridge/intel: Use i82801gx code for NM10
It works as an ICH7 on Intel D510MO mainboard
Change-Id: Ib8c76c001dffee8f93e3d6aa3156d4413b2e842a
Signed-off-by: Damien Zammit <damien(a)zamaudio.com>
---
src/southbridge/intel/i82801gx/lpc.c | 39 ++++++++++++++----------------------
1 file changed, 15 insertions(+), 24 deletions(-)
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 57ff0dd..cf5fd53 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -697,30 +697,21 @@ static struct device_operations device_ops = {
.ops_pci = &pci_ops,
};
-/* 82801GH (ICH7 DH) */
-static const struct pci_driver ich7_dh_lpc __pci_driver = {
+/* 27b0: 82801GH (ICH7 DH) */
+/* 27b8: 82801GB/GR (ICH7/ICH7R) */
+/* 27b9: 82801GBM/GU (ICH7-M/ICH7-U) */
+/* 27bc: 82NM10 (NM10) */
+/* 27bd: 82801GHM (ICH7-M DH) */
+
+static const unsigned short pci_device_ids[] = { 0x27b0,
+ 0x27b8,
+ 0x27b9,
+ 0x27bc,
+ 0x27bd,
+ 0 };
+
+static const struct pci_driver ich7_lpc __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x27b0,
-};
-
-/* 82801GB/GR (ICH7/ICH7R) */
-static const struct pci_driver ich7_ich7r_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x27b8,
-};
-
-/* 82801GBM/GU (ICH7-M/ICH7-U) */
-static const struct pci_driver ich7m_ich7u_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x27b9,
-};
-
-/* 82801GHM (ICH7-M DH) */
-static const struct pci_driver ich7m_dh_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x27bd,
+ .devices = pci_device_ids,
};
1
0
Patch set updated for coreboot: northbridge/intel/pineview: Add remaining boilerplate code for northbridge
by Damien Zammit 20 Nov '15
by Damien Zammit 20 Nov '15
20 Nov '15
Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12430
-gerrit
commit 7ffb795166287f10c0e065fccd33c37b93650a87
Author: Damien Zammit <damien(a)zamaudio.com>
Date: Sat Nov 14 00:59:21 2015 +1100
northbridge/intel/pineview: Add remaining boilerplate code for northbridge
This patch does *not* include native raminit
Change-Id: I3fb8146ef7fe2ad27c167ecd2fb0fd629f051cc1
Signed-off-by: Damien Zammit <damien(a)zamaudio.com>
---
src/northbridge/intel/pineview/Kconfig | 3 +-
src/northbridge/intel/pineview/Makefile.inc | 3 +
src/northbridge/intel/pineview/acpi/hostbridge.asl | 234 +++++++++
src/northbridge/intel/pineview/acpi/igd.asl | 432 ++++++++++++++++
src/northbridge/intel/pineview/acpi/peg.asl | 41 ++
src/northbridge/intel/pineview/acpi/pineview.asl | 78 +++
src/northbridge/intel/pineview/chip.h | 8 +
src/northbridge/intel/pineview/early_init.c | 179 +++++++
src/northbridge/intel/pineview/gma.c | 552 +++++++++++++++++++++
src/northbridge/intel/pineview/northbridge.c | 286 +++++++++++
src/northbridge/intel/pineview/pineview.h | 177 ++++++-
src/northbridge/intel/pineview/ram_calc.c | 68 +--
12 files changed, 2030 insertions(+), 31 deletions(-)
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
index 6253b84..e37f442 100644
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -26,7 +26,8 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select HAVE_DEBUG_RAM_SETUP
select LAPIC_MONOTONIC_TIMER
select VGA
- select PER_DEVICE_ACPI_TABLES
+ select INTEL_GMA_ACPI
+ select LATE_CBMEM_INIT
config BOOTBLOCK_NORTHBRIDGE_INIT
string
diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc
index 9330b17..7275d70 100644
--- a/src/northbridge/intel/pineview/Makefile.inc
+++ b/src/northbridge/intel/pineview/Makefile.inc
@@ -17,8 +17,11 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW),y)
ramstage-y += ram_calc.c
+ramstage-y += northbridge.c
+ramstage-y += gma.c
ramstage-y += acpi.c
romstage-y += ram_calc.c
+romstage-y += early_init.c
endif
diff --git a/src/northbridge/intel/pineview/acpi/hostbridge.asl b/src/northbridge/intel/pineview/acpi/hostbridge.asl
new file mode 100644
index 0000000..747d7da
--- /dev/null
+++ b/src/northbridge/intel/pineview/acpi/hostbridge.asl
@@ -0,0 +1,234 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/ioapic.h>
+
+Name(_HID,EISAID("PNP0A08")) // PCIe
+Name(_CID,EISAID("PNP0A03")) // PCI
+
+Name(_ADR, 0)
+Name(_BBN, 0)
+
+Device (MCHC)
+{
+ Name(_ADR, 0x00000000) // 0:0.0
+
+ OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
+ Field (MCHP, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x40), // EPBAR
+ EPEN, 1, // Enable
+ , 11, //
+ EPBR, 24, // EPBAR
+
+ Offset (0x48), // MCHBAR
+ MHEN, 1, // Enable
+ , 13, //
+ MHBR, 22, // MCHBAR
+
+ Offset (0x60), // PCIe BAR
+ PXEN, 1, // Enable
+ PXSZ, 2, // BAR size
+ , 23, //
+ PXBR, 10, // PCIe BAR
+
+ Offset (0x68), // DMIBAR
+ DMEN, 1, // Enable
+ , 11, //
+ DMBR, 20, // DMIBAR
+
+ // ...
+
+ Offset (0x90), // PAM0
+ , 4,
+ PM0H, 2,
+ , 2,
+ Offset (0x91), // PAM1
+ PM1L, 2,
+ , 2,
+ PM1H, 2,
+ , 2,
+ Offset (0x92), // PAM2
+ PM2L, 2,
+ , 2,
+ PM2H, 2,
+ , 2,
+ Offset (0x93), // PAM3
+ PM3L, 2,
+ , 2,
+ PM3H, 2,
+ , 2,
+ Offset (0x94), // PAM4
+ PM4L, 2,
+ , 2,
+ PM4H, 2,
+ , 2,
+ Offset (0x95), // PAM5
+ PM5L, 2,
+ , 2,
+ PM5H, 2,
+ , 2,
+ Offset (0x96), // PAM6
+ PM6L, 2,
+ , 2,
+ PM6H, 2,
+ , 2,
+
+ Offset (0xa0), // Top of Used Memory
+ TOM, 8,
+
+ Offset (0xb0), // Top of Low Used Memory
+ , 4,
+ TLUD, 12,
+
+ }
+
+}
+
+
+// Current Resource Settings
+Name (MCRS, ResourceTemplate()
+{
+ // Bus Numbers
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
+
+ // IO Region 0
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
+
+ // PCI Config Space
+ Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+ // IO Region 1
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
+
+ // VGA memory (0xa0000-0xbffff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+ 0x00020000,,, ASEG)
+
+ // OPROM reserved (0xc0000-0xc3fff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+ 0x00004000,,, OPR0)
+
+ // OPROM reserved (0xc4000-0xc7fff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+ 0x00004000,,, OPR1)
+
+ // OPROM reserved (0xc8000-0xcbfff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+ 0x00004000,,, OPR2)
+
+ // OPROM reserved (0xcc000-0xcffff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+ 0x00004000,,, OPR3)
+
+ // OPROM reserved (0xd0000-0xd3fff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+ 0x00004000,,, OPR4)
+
+ // OPROM reserved (0xd4000-0xd7fff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+ 0x00004000,,, OPR5)
+
+ // OPROM reserved (0xd8000-0xdbfff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+ 0x00004000,,, OPR6)
+
+ // OPROM reserved (0xdc000-0xdffff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+ 0x00004000,,, OPR7)
+
+ // BIOS Extension (0xe0000-0xe3fff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+ 0x00004000,,, ESG0)
+
+ // BIOS Extension (0xe4000-0xe7fff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+ 0x00004000,,, ESG1)
+
+ // BIOS Extension (0xe8000-0xebfff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+ 0x00004000,,, ESG2)
+
+ // BIOS Extension (0xec000-0xeffff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+ 0x00004000,,, ESG3)
+
+ // System BIOS (0xf0000-0xfffff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+ 0x00010000,,, FSEG)
+
+ // PCI Memory Region (Top of memory-0xfebfffff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
+ IO_APIC_ADDR,,, PM01)
+
+ // TPM Area (0xfed40000-0xfed44fff)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
+ 0x00005000,,, TPMR)
+})
+
+Method (_CRS, 0, Serialized)
+{
+ // Find PCI resource area in MCRS
+ CreateDwordField(MCRS, ^PM01._MIN, PMIN)
+ CreateDwordField(MCRS, ^PM01._MAX, PMAX)
+ CreateDwordField(MCRS, ^PM01._LEN, PLEN)
+
+ // Fix up PCI memory region:
+ // Enter actual TOLUD. The TOLUD register contains bits 27-31 of
+ // the top of memory address.
+ ShiftLeft (^MCHC.TLUD, 27, PMIN)
+ Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+ Return (MCRS)
+}
+
+/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
+#include "acpi/pineview_pci_irqs.asl"
diff --git a/src/northbridge/intel/pineview/acpi/igd.asl b/src/northbridge/intel/pineview/acpi/igd.asl
new file mode 100644
index 0000000..ca14c1d
--- /dev/null
+++ b/src/northbridge/intel/pineview/acpi/igd.asl
@@ -0,0 +1,432 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (GFX0)
+{
+ Name (_ADR, 0x00020000)
+
+ OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
+ Field (GFXC, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x10),
+ BAR0, 64
+ }
+
+ OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
+ Field (GFRG, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x61250),
+ CR1, 32,
+ BCLV, 16,
+ BCLM, 16,
+ }
+
+ /* Display Output Switching */
+ Method (_DOS, 1)
+ {
+ /* Windows 2000 and Windows XP call _DOS to enable/disable
+ * Display Output Switching during init and while a switch
+ * is already active
+ */
+ Store (And(Arg0, 7), DSEN)
+ }
+
+ /* We try to support as many GM45 systems as possible,
+ * so keep the number of DIDs flexible.
+ */
+ Method (_DOD, 0)
+ {
+ If (LEqual(NDID, 1)) {
+ Name(DOD1, Package() {
+ 0xffffffff
+ })
+ Store (Or(0x00010000, DID1), Index(DOD1, 0))
+ Return(DOD1)
+ }
+
+ If (LEqual(NDID, 2)) {
+ Name(DOD2, Package() {
+ 0xffffffff,
+ 0xffffffff
+ })
+ Store (Or(0x00010000, DID1), Index(DOD2, 0))
+ Store (Or(0x00010000, DID2), Index(DOD2, 1))
+ Return(DOD2)
+ }
+
+ If (LEqual(NDID, 3)) {
+ Name(DOD3, Package() {
+ 0xffffffff,
+ 0xffffffff,
+ 0xffffffff
+ })
+ Store (Or(0x00010000, DID1), Index(DOD3, 0))
+ Store (Or(0x00010000, DID2), Index(DOD3, 1))
+ Store (Or(0x00010000, DID3), Index(DOD3, 2))
+ Return(DOD3)
+ }
+
+ If (LEqual(NDID, 4)) {
+ Name(DOD4, Package() {
+ 0xffffffff,
+ 0xffffffff,
+ 0xffffffff,
+ 0xffffffff
+ })
+ Store (Or(0x00010000, DID1), Index(DOD4, 0))
+ Store (Or(0x00010000, DID2), Index(DOD4, 1))
+ Store (Or(0x00010000, DID3), Index(DOD4, 2))
+ Store (Or(0x00010000, DID4), Index(DOD4, 3))
+ Return(DOD4)
+ }
+
+ If (LGreater(NDID, 4)) {
+ Name(DOD5, Package() {
+ 0xffffffff,
+ 0xffffffff,
+ 0xffffffff,
+ 0xffffffff,
+ 0xffffffff
+ })
+ Store (Or(0x00010000, DID1), Index(DOD5, 0))
+ Store (Or(0x00010000, DID2), Index(DOD5, 1))
+ Store (Or(0x00010000, DID3), Index(DOD5, 2))
+ Store (Or(0x00010000, DID4), Index(DOD5, 3))
+ Store (Or(0x00010000, DID5), Index(DOD5, 4))
+ Return(DOD5)
+ }
+
+ /* Some error happened, but we have to return something */
+ Return (Package() {0x00000400})
+ }
+
+ Device(DD01)
+ {
+ /* Device Unique ID */
+ Method(_ADR, 0, Serialized)
+ {
+ If(LEqual(DID1, 0)) {
+ Return (1)
+ } Else {
+ Return (And(0xffff, DID1))
+ }
+ }
+
+ /* Device Current Status */
+ Method(_DCS, 0)
+ {
+ TRAP(1)
+ If (And(CSTE, 1)) {
+ Return (0x1f)
+ }
+ Return(0x1d)
+ }
+
+ /* Query Device Graphics State */
+ Method(_DGS, 0)
+ {
+ If (And(NSTE, 1)) {
+ Return(1)
+ }
+ Return(0)
+ }
+
+ /* Device Set State */
+ Method(_DSS, 1)
+ {
+ /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+ * display switch was completed
+ */
+ If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+ Store (NSTE, CSTE)
+ }
+ }
+ }
+
+#ifdef DISPLAY_DEVICE_2_IS_LCD_SCREEN
+ Device (LCD0)
+ {
+ /* Device Unique ID */
+ Method(_ADR, 0, Serialized)
+ {
+ If(LEqual(DID2, 0)) {
+ Return (2)
+ } Else {
+ Return (And(0xffff, DID2))
+ }
+ }
+
+ Name (BRCT, 0)
+
+ Name (BRIG, Package (0x12)
+ {
+ 0x61,
+ 0x61,
+ 0x2,
+ 0x4,
+ 0x5,
+ 0x7,
+ 0x9,
+ 0xb,
+ 0xd,
+ 0x11,
+ 0x14,
+ 0x17,
+ 0x1c,
+ 0x20,
+ 0x27,
+ 0x31,
+ 0x41,
+ 0x61,
+ })
+
+ Method (_BCL, 0, NotSerialized)
+ {
+ Store (1, BRCT)
+ Return (BRIG)
+ }
+
+ Method (_BCM, 1, NotSerialized)
+ {
+ Store (ShiftLeft (Arg0, 4), ^^BCLV)
+ Store (0x80000000, ^^CR1)
+ Store (0x0610, ^^BCLM)
+ }
+ Method (_BQC, 0, NotSerialized)
+ {
+ Store (^^BCLV, Local0)
+ ShiftRight (Local0, 4, Local0)
+ Return (Local0)
+ }
+
+ Method(BRID, 1, NotSerialized)
+ {
+ Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0)
+ If (LEqual (Local0, Ones))
+ {
+ Return (0x11)
+ }
+ Return (Local0)
+ }
+
+ /* Using Notify is the right way. But Windows doesn't handle
+ it well. So use both method in a way to avoid double action.
+ */
+ Method (DECB, 0, NotSerialized)
+ {
+ If (BRCT)
+ {
+ Notify (LCD0, 0x87)
+ } Else {
+ Store (BRID (_BQC ()), Local0)
+ If (LNotEqual (Local0, 2))
+ {
+ Decrement (Local0)
+ }
+ _BCM (DerefOf (Index (BRIG, Local0)))
+ }
+ }
+ Method (INCB, 0, NotSerialized)
+ {
+ If (BRCT)
+ {
+ Notify (LCD0, 0x86)
+ } Else {
+ Store (BRID (_BQC ()), Local0)
+ If (LNotEqual (Local0, 0x11))
+ {
+ Increment (Local0)
+ }
+ _BCM (DerefOf (Index (BRIG, Local0)))
+ }
+ }
+ }
+#else
+ Device(DD02)
+ {
+ /* Device Unique ID */
+ Method(_ADR, 0, Serialized)
+ {
+ If(LEqual(DID2, 0)) {
+ Return (2)
+ } Else {
+ Return (And(0xffff, DID2))
+ }
+ }
+
+ /* Device Current Status */
+ Method(_DCS, 0)
+ {
+ TRAP(1)
+ If (And(CSTE, 2)) {
+ Return (0x1f)
+ }
+ Return(0x1d)
+ }
+
+ /* Query Device Graphics State */
+ Method(_DGS, 0)
+ {
+ If (And(NSTE, 2)) {
+ Return(1)
+ }
+ Return(0)
+ }
+
+ /* Device Set State */
+ Method(_DSS, 1)
+ {
+ /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+ * display switch was completed
+ */
+ If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+ Store (NSTE, CSTE)
+ }
+ }
+ }
+#endif
+
+ Device(DD03)
+ {
+ /* Device Unique ID */
+ Method(_ADR, 0, Serialized)
+ {
+ If(LEqual(DID3, 0)) {
+ Return (3)
+ } Else {
+ Return (And(0xffff, DID3))
+ }
+ }
+
+ /* Device Current Status */
+ Method(_DCS, 0)
+ {
+ TRAP(1)
+ If (And(CSTE, 4)) {
+ Return (0x1f)
+ }
+ Return(0x1d)
+ }
+
+ /* Query Device Graphics State */
+ Method(_DGS, 0)
+ {
+ If (And(NSTE, 4)) {
+ Return(1)
+ }
+ Return(0)
+ }
+
+ /* Device Set State */
+ Method(_DSS, 1)
+ {
+ /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+ * display switch was completed
+ */
+ If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+ Store (NSTE, CSTE)
+ }
+ }
+ }
+
+
+ Device(DD04)
+ {
+ /* Device Unique ID */
+ Method(_ADR, 0, Serialized)
+ {
+ If(LEqual(DID4, 0)) {
+ Return (4)
+ } Else {
+ Return (And(0xffff, DID4))
+ }
+ }
+
+ /* Device Current Status */
+ Method(_DCS, 0)
+ {
+ TRAP(1)
+ If (And(CSTE, 8)) {
+ Return (0x1f)
+ }
+ Return(0x1d)
+ }
+
+ /* Query Device Graphics State */
+ Method(_DGS, 0)
+ {
+ If (And(NSTE, 4)) {
+ Return(1)
+ }
+ Return(0)
+ }
+
+ /* Device Set State */
+ Method(_DSS, 1)
+ {
+ /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+ * display switch was completed
+ */
+ If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+ Store (NSTE, CSTE)
+ }
+ }
+ }
+
+
+ Device(DD05)
+ {
+ /* Device Unique ID */
+ Method(_ADR, 0, Serialized)
+ {
+ If(LEqual(DID5, 0)) {
+ Return (5)
+ } Else {
+ Return (And(0xffff, DID5))
+ }
+ }
+
+ /* Device Current Status */
+ Method(_DCS, 0)
+ {
+ TRAP(1)
+ If (And(CSTE, 16)) {
+ Return (0x1f)
+ }
+ Return(0x1d)
+ }
+
+ /* Query Device Graphics State */
+ Method(_DGS, 0)
+ {
+ If (And(NSTE, 4)) {
+ Return(1)
+ }
+ Return(0)
+ }
+
+ /* Device Set State */
+ Method(_DSS, 1)
+ {
+ /* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+ * display switch was completed
+ */
+ If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+ Store (NSTE, CSTE)
+ }
+ }
+ }
+}
diff --git a/src/northbridge/intel/pineview/acpi/peg.asl b/src/northbridge/intel/pineview/acpi/peg.asl
new file mode 100644
index 0000000..227ca27
--- /dev/null
+++ b/src/northbridge/intel/pineview/acpi/peg.asl
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (PEGP)
+{
+ Name (_ADR, 0x00010000)
+
+ // PCI Interrupt Routing.
+ Method (_PRT)
+ {
+ If (PICM) {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, 0, 16 },
+ Package() { 0x0000ffff, 1, 0, 17 },
+ Package() { 0x0000ffff, 2, 0, 18 },
+ Package() { 0x0000ffff, 3, 0, 19 }
+ })
+ } Else {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }
+ })
+ }
+
+ }
+}
diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl
new file mode 100644
index 0000000..b43ce07
--- /dev/null
+++ b/src/northbridge/intel/pineview/acpi/pineview.asl
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "hostbridge.asl"
+#include "../iomap.h"
+
+/* PCI Device Resource Consumption */
+Device (PDRC)
+{
+ Name (_HID, EISAID("PNP0C02"))
+ Name (_UID, 1)
+
+ // This does not seem to work correctly yet - set values statically for
+ // now.
+
+ //Name (PDRS, ResourceTemplate() {
+ // Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA
+ // Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR
+ // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR
+ // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR
+ // Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR
+ // Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH
+ //})
+
+ Name (PDRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
+ Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
+ Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
+ Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
+ Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
+ Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
+ Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
+ Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
+ })
+
+ // Current Resource Settings
+ Method (_CRS, 0, Serialized)
+ {
+ //CreateDwordField(PDRS, ^RCRB._BAS, RBR0)
+ //ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0)
+
+ //CreateDwordField(PDRS, ^MCHB._BAS, MBR0)
+ //ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0)
+
+ //CreateDwordField(PDRS, ^DMIB._BAS, DBR0)
+ //ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0)
+
+ //CreateDwordField(PDRS, ^EGPB._BAS, EBR0)
+ //ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0)
+
+ //CreateDwordField(PDRS, ^PCIE._BAS, PBR0)
+ //ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0)
+
+ //CreateDwordField(PDRS, ^PCIE._LEN, PSZ0)
+ //ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0)
+
+ Return(PDRS)
+ }
+}
+
+// PCIe graphics port 0:1.0
+#include "peg.asl"
+
+// Integrated graphics 0:2.0
+//#include "igd.asl"
diff --git a/src/northbridge/intel/pineview/chip.h b/src/northbridge/intel/pineview/chip.h
new file mode 100644
index 0000000..a620857
--- /dev/null
+++ b/src/northbridge/intel/pineview/chip.h
@@ -0,0 +1,8 @@
+#include <drivers/intel/gma/i915.h>
+
+struct northbridge_intel_pineview_config {
+ u32 gpu_hotplug;
+ u32 gpu_backlight;
+ int gpu_lvds_use_spread_spectrum_clock;
+ struct i915_gpu_controller_info gfx;
+};
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c
new file mode 100644
index 0000000..c57aafc
--- /dev/null
+++ b/src/northbridge/intel/pineview/early_init.c
@@ -0,0 +1,179 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <cbmem.h>
+#include <halt.h>
+#include <string.h>
+#include <northbridge/intel/pineview/pineview.h>
+
+static void pineview_setup_bars(void)
+{
+ u8 reg8;
+ u16 reg16;
+ u32 reg32;
+
+ /* Setting up Southbridge. In the northbridge code. */
+ printk(BIOS_DEBUG, "Setting up static southbridge registers...");
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
+
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
+
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); /* Enable GPIOs */
+
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x007c0291);
+
+ pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+ printk(BIOS_DEBUG, " done.\n");
+
+ printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
+ RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
+ outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
+ printk(BIOS_DEBUG, " done.\n");
+
+ /* Enable upper 128bytes of CMOS */
+ RCBA32(0x3400) = (1 << 2);
+
+ /* Set up GPIO initially */
+ GPIO32(0x0) = 0x1ffde7c1;
+ GPIO32(0x30) = 0x7f;
+ GPIO32(0x4) = 0xe9e001;
+ GPIO32(0x34) = 0x7e;
+ GPIO32(0xc) = 0x4000000;
+ GPIO32(0x2c) = 0x2000;
+ GPIO32(0x18) = 0x0;
+ GPIO32(0xc) = 0xece9e802;
+
+ printk(BIOS_DEBUG, "Setting up static northbridge registers...");
+ /* Set up all hardcoded northbridge BARs */
+ pci_write_config8(PCI_DEV(0, 0x00, 0), 0x8, 0x69);
+
+ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), PMIOBAR, (uintptr_t)0x400 | 1);
+
+
+ reg32 = MCHBAR32(0x30);
+ MCHBAR32(0x30) = 0x21800;
+ DMIBAR32(0x2c) = 0x86000040;
+ pci_write_config8(PCI_DEV(0, 0x00, 0), DEVEN, 0x09);
+ pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00020200);
+ pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00000000);
+ reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe5); // 0x10
+ reg16 = pci_read_config16(PCI_DEV(0, 0x02, 0), 0x0); // 0x8086
+
+ reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), GGC);
+ pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, 0x130);
+ reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), GGC);
+ pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, 0x130);
+ MCHBAR8(0xb08) = 0x20;
+ reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe6); // 0x11
+ reg16 = MCHBAR16(0xc8c);
+ MCHBAR16(0xc8c) = reg16 | 0x0200;
+ reg8 = MCHBAR8(0xc8c);
+ MCHBAR8(0xc8c) = reg8;
+ MCHBAR8(0xc8c) = 0x12;
+ pci_write_config8(PCI_DEV(0, 0x02, 0), 0x62, 0x02);
+ pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe8, 0x8000);
+ MCHBAR32(0x3004) = 0x48000000;
+ MCHBAR32(0x3008) = 0xfffffe00;
+ MCHBAR32(0xb08) = 0x06028220;
+ MCHBAR32(0xff4) = 0xc6db8b5f;
+ MCHBAR16(0xff8) = 0x024f;
+
+ // PLL Voltage controlled oscillator
+ //MCHBAR8(0xc38) = 0x04;
+
+ pci_write_config16(PCI_DEV(0, 0x02, 0), 0xcc, 0x014d);
+ reg32 = MCHBAR32(0x40);
+ MCHBAR32(0x40) = 0x0;
+ reg32 = MCHBAR32(0x40);
+ MCHBAR32(0x40) = 0x8;
+
+ // POST 0x13
+
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x8, 0x1d);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x8, 0x0);
+ RCBA32(0x3410) = 0x00020465;
+ RCBA32(0x88) = 0x0011d000;
+ RCBA32(0x1fc) = 0x60f;
+ RCBA32(0x1f4) = 0x86000040;
+ RCBA32(0x214) = 0x10030509;
+ RCBA32(0x218) = 0x00020504;
+ RCBA32(0x220) = 0xc5;
+ RCBA32(0x3430) = 0x1;
+ RCBA32(0x2027) = 0x38f6a70d;
+ RCBA16(0x3e08) = 0x0080;
+ RCBA16(0x3e48) = 0x0080;
+ RCBA32(0x3e0e) = 0x00000080;
+ RCBA32(0x3e4e) = 0x00000080;
+ RCBA32(0x2034) = 0xb24577cc;
+ RCBA32(0x1c) = 0x03128010;
+ RCBA32(0x2010) = 0x400;
+ RCBA32(0x3400) = 0x4;
+ RCBA32(0x2080) = 0x18006007;
+ RCBA32(0x20a0) = 0x18006007;
+ RCBA32(0x20c0) = 0x18006007;
+ RCBA32(0x20e0) = 0x18006007;
+
+ pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1);
+ pci_write_config32(PCI_DEV(0, 0x1d, 1), 0xca, 0x1);
+ pci_write_config32(PCI_DEV(0, 0x1d, 2), 0xca, 0x1);
+ pci_write_config32(PCI_DEV(0, 0x1d, 3), 0xca, 0x1);
+
+ RCBA32(0x3100) = 0x42210;
+ RCBA32(0x3108) = 0x10004321;
+ RCBA32(0x310c) = 0x00214321;
+ RCBA32(0x3110) = 0x1;
+ RCBA32(0x3140) = 0x01460132;
+ RCBA32(0x3142) = 0x02370146;
+ RCBA32(0x3144) = 0x32010237;
+ RCBA32(0x3146) = 0x01463201;
+ RCBA32(0x3148) = 0x146;
+
+ /* Set C0000-FFFFF to access RAM on both reads and writes */
+ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);
+ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33);
+ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33);
+ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33);
+ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33);
+ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33);
+ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
+
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC);
+ printk(BIOS_DEBUG, " done.\n");
+}
+
+void pineview_early_initialization(void)
+{
+ /* Print some chipset specific information */
+ printk(BIOS_DEBUG, "Intel Pineview northbridge\n");
+
+ /* Setup all BARs required for early PCIe and raminit */
+ pineview_setup_bars();
+
+ /* Change port80 to LPC */
+ RCBA32(GCS) &= (~0x04);
+
+ /* Just do it that way */
+ RCBA32(0x2010) |= (1 << 10);
+}
diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c
new file mode 100644
index 0000000..eca59e9
--- /dev/null
+++ b/src/northbridge/intel/pineview/gma.c
@@ -0,0 +1,552 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <bootmode.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <pc80/mc146818rtc.h>
+#include <edid.h>
+#include <drivers/intel/gma/edid.h>
+#include <drivers/intel/gma/i915.h>
+#include <string.h>
+#include <pc80/vga.h>
+#include <pc80/vga_io.h>
+
+#include "chip.h"
+#include "pineview.h"
+
+#define GDRST 0xc0
+
+#define LVDS_CLOCK_A_POWERUP_ALL (3 << 8)
+#define LVDS_CLOCK_B_POWERUP_ALL (3 << 4)
+#define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2)
+#define DISPPLANE_BGRX888 (0x6<<26)
+#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
+
+#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
+
+#define PGETBL_CTL 0x2020
+#define PGETBL_ENABLED 0x00000001
+
+#define BASE_FREQUENCY 120000
+
+#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
+
+static int gtt_setup(void *mmiobase)
+{
+ unsigned long PGETBL_save;
+ unsigned long tom; // top of memory
+
+ /*
+ * The Video BIOS places the GTT right below top of memory.
+ */
+ tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24;
+ PGETBL_save = tom - 256 * KiB;
+ PGETBL_save |= PGETBL_ENABLED;
+ PGETBL_save |= 2; /* set GTT to 256kb */
+
+ write32(mmiobase + GFX_FLSH_CNTL, 0);
+
+ write32(mmiobase + PGETBL_CTL, PGETBL_save);
+
+ /* verify */
+ if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) {
+ printk(BIOS_DEBUG, "gtt_setup is enabled.\n");
+ } else {
+ printk(BIOS_DEBUG, "gtt_setup failed!!!\n");
+ return 1;
+ }
+ write32(mmiobase + GFX_FLSH_CNTL, 0);
+
+ return 0;
+}
+
+static int intel_gma_init(struct northbridge_intel_pineview_config *conf,
+ unsigned int pphysbase, unsigned int piobase,
+ void *pmmio, unsigned int pgfx)
+{
+ struct edid edid;
+ struct edid_mode *mode;
+ u8 edid_data[128];
+ unsigned long temp;
+ int hpolarity, vpolarity;
+ u32 candp1, candn;
+ u32 best_delta = 0xffffffff;
+ u32 target_frequency;
+ u32 pixel_p1 = 1;
+ u32 pixel_n = 1;
+ u32 pixel_m1 = 1;
+ u32 pixel_m2 = 1;
+ u32 hactive, vactive, right_border, bottom_border;
+ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch;
+ u32 i, j;
+ u32 uma_size;
+ u16 reg16;
+
+ printk(BIOS_SPEW,
+ "i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n",
+ (void *)pgfx, pmmio, piobase, pphysbase);
+
+ intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data, 128);
+ decode_edid(edid_data, sizeof(edid_data), &edid);
+ mode = &edid.mode;
+
+ hpolarity = (mode->phsync == '-');
+ vpolarity = (mode->pvsync == '-');
+ hactive = edid.x_resolution;
+ vactive = edid.y_resolution;
+ right_border = mode->hborder;
+ bottom_border = mode->vborder;
+ vblank = mode->vbl;
+ hblank = mode->hbl;
+ vsync = mode->vspw;
+ hsync = mode->hspw;
+ hfront_porch = mode->hso;
+ vfront_porch = mode->vso;
+
+ for (i = 0; i < 2; i++)
+ for (j = 0; j < 0x100; j++)
+ /* R=j, G=j, B=j. */
+ write32(pmmio + PALETTE(i) + 4 * j, 0x10101 * j);
+
+ write32(pmmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
+ | (read32(pmmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
+
+ write32(pmmio + MI_ARB_STATE, MI_ARB_C3_LP_WRITE_ENABLE | (1 << 27));
+ /* Clean registers. */
+ for (i = 0; i < 0x20; i += 4)
+ write32(pmmio + RENDER_RING_BASE + i, 0);
+ for (i = 0; i < 0x20; i += 4)
+ write32(pmmio + FENCE_REG_965_0 + i, 0);
+ write32(pmmio + PP_ON_DELAYS, 0);
+ write32(pmmio + PP_OFF_DELAYS, 0);
+
+ /* Disable VGA. */
+ write32(pmmio + VGACNTRL, VGA_DISP_DISABLE);
+
+ /* Disable pipes. */
+ write32(pmmio + PIPECONF(0), 0);
+ write32(pmmio + PIPECONF(1), 0);
+
+ /* Init PRB0. */
+ write32(pmmio + HWS_PGA, 0x352d2000);
+ write32(pmmio + PRB0_CTL, 0);
+ write32(pmmio + PRB0_HEAD, 0);
+ write32(pmmio + PRB0_TAIL, 0);
+ write32(pmmio + PRB0_START, 0);
+ write32(pmmio + PRB0_CTL, 0x0001f001);
+
+ write32(pmmio + D_STATE, DSTATE_PLL_D3_OFF
+ | DSTATE_GFX_CLOCK_GATING | DSTATE_DOT_CLOCK_GATING);
+ write32(pmmio + ECOSKPD, 0x00010000);
+ write32(pmmio + HWSTAM, 0xeffe);
+ write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug);
+ write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS);
+
+ target_frequency = mode->lvds_dual_channel ? mode->pixel_clock
+ : (2 * mode->pixel_clock);
+
+ /* Find suitable divisors. */
+ for (candp1 = 1; candp1 <= 8; candp1++) {
+ for (candn = 5; candn <= 10; candn++) {
+ u32 cur_frequency;
+ u32 m; /* 77 - 131. */
+ u32 denom; /* 35 - 560. */
+ u32 current_delta;
+
+ denom = candn * candp1 * 7;
+ /* Doesnt overflow for up to
+ 5000000 kHz = 5 GHz. */
+ m = (target_frequency * denom
+ + BASE_FREQUENCY / 2) / BASE_FREQUENCY;
+
+ if (m < 77 || m > 131)
+ continue;
+
+ cur_frequency = (BASE_FREQUENCY * m) / denom;
+ if (target_frequency > cur_frequency)
+ current_delta = target_frequency - cur_frequency;
+ else
+ current_delta = cur_frequency - target_frequency;
+
+ if (best_delta > current_delta) {
+ best_delta = current_delta;
+ pixel_n = candn;
+ pixel_p1 = candp1;
+ pixel_m2 = ((m + 3) % 5) + 7;
+ pixel_m1 = (m - pixel_m2) / 5;
+ }
+ }
+ }
+
+ if (best_delta == 0xffffffff) {
+ printk (BIOS_ERR, "Couldn't find GFX clock divisors\n");
+ return -1;
+ }
+
+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
+ hactive, vactive);
+ printk(BIOS_DEBUG, "Borders %d x %d\n", right_border, bottom_border);
+ printk(BIOS_DEBUG, "Blank %d x %d\n", hblank, vblank);
+ printk(BIOS_DEBUG, "Sync %d x %d\n", hsync, vsync);
+ printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch);
+ printk(BIOS_DEBUG, (conf->gpu_lvds_use_spread_spectrum_clock
+ ? "Spread spectrum clock\n"
+ : "DREF clock\n"));
+ printk(BIOS_DEBUG, (mode->lvds_dual_channel
+ ? "Dual channel\n"
+ : "Single channel\n"));
+ printk(BIOS_DEBUG, "Polarities %d, %d\n",
+ hpolarity, vpolarity);
+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",
+ pixel_n, pixel_m1, pixel_m2, pixel_p1);
+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
+ BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n
+ / (pixel_p1 * 7));
+
+#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
+ write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16));
+ write32(pmmio + PF_WIN_POS(0), 0);
+ write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
+ write32(pmmio + PFIT_CONTROL, PFIT_ENABLE | (1 << PFIT_PIPE_SHIFT) | HORIZ_AUTO_SCALE | VERT_AUTO_SCALE);
+#else
+ /* Disable panel fitter (we're in native resolution). */
+ write32(pmmio + PF_CTL(0), 0);
+ write32(pmmio + PF_WIN_SZ(0), 0);
+ write32(pmmio + PF_WIN_POS(0), 0);
+ write32(pmmio + PFIT_PGM_RATIOS, 0);
+ write32(pmmio + PFIT_CONTROL, 0);
+#endif
+
+ mdelay(1);
+
+ write32(pmmio + DSPCNTR(0), DISPPLANE_BGRX888
+ | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE);
+
+ mdelay(1);
+ write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS
+ | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
+ write32(pmmio + FP0(1),
+ ((pixel_n - 2) << 16)
+ | ((pixel_m1 - 2) << 8) | pixel_m2);
+ write32(pmmio + DPLL(1),
+ DPLL_VGA_MODE_DIS |
+ DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
+ | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
+ : DPLLB_LVDS_P2_CLOCK_DIV_14)
+ | (conf->gpu_lvds_use_spread_spectrum_clock
+ ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV
+ : 0)
+ | (pixel_p1 << 16)
+ | (pixel_p1));
+ mdelay(1);
+ write32(pmmio + DPLL(1),
+ DPLL_VGA_MODE_DIS |
+ DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
+ | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
+ : DPLLB_LVDS_P2_CLOCK_DIV_14)
+ | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13)
+ | (pixel_p1 << 16)
+ | (pixel_p1));
+ mdelay(1);
+ write32(pmmio + HTOTAL(1),
+ ((hactive + right_border + hblank - 1) << 16)
+ | (hactive - 1));
+ write32(pmmio + HBLANK(1),
+ ((hactive + right_border + hblank - 1) << 16)
+ | (hactive + right_border - 1));
+ write32(pmmio + HSYNC(1),
+ ((hactive + right_border + hfront_porch + hsync - 1) << 16)
+ | (hactive + right_border + hfront_porch - 1));
+
+ write32(pmmio + VTOTAL(1), ((vactive + bottom_border + vblank - 1) << 16)
+ | (vactive - 1));
+ write32(pmmio + VBLANK(1), ((vactive + bottom_border + vblank - 1) << 16)
+ | (vactive + bottom_border - 1));
+ write32(pmmio + VSYNC(1),
+ (vactive + bottom_border + vfront_porch + vsync - 1)
+ | (vactive + bottom_border + vfront_porch - 1));
+
+#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
+ write32(pmmio + PIPESRC(1), (639 << 16) | 399);
+#else
+ write32(pmmio + PIPESRC(1), ((hactive - 1) << 16) | (vactive - 1));
+#endif
+ mdelay(1);
+
+ write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16));
+ write32(pmmio + DSPPOS(0), 0);
+
+ /* Backlight init. */
+ write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK);
+ write32(pmmio + FW_BLC, 0x011d011a);
+ write32(pmmio + FW_BLC2, 0x00000102);
+ write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK);
+ write32(pmmio + FW_BLC_SELF, 0x0001003f);
+ write32(pmmio + FW_BLC, 0x011d0109);
+ write32(pmmio + FW_BLC2, 0x00000102);
+ write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK);
+ write32(pmmio + BLC_PWM_CTL, conf->gpu_backlight);
+
+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
+ write32(pmmio + DSPADDR(0), 0);
+ write32(pmmio + DSPSURF(0), 0);
+ write32(pmmio + DSPSTRIDE(0), edid.bytes_per_line);
+ write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888
+ | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE);
+ mdelay(1);
+
+ write32(pmmio + PIPECONF(1), PIPECONF_ENABLE);
+ write32(pmmio + LVDS, LVDS_ON
+ | (hpolarity << 20) | (vpolarity << 21)
+ | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
+ | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
+ | LVDS_CLOCK_A_POWERUP_ALL
+ | LVDS_PIPE(1));
+
+ write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
+ write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
+ mdelay(1);
+ write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS
+ | PANEL_POWER_ON | PANEL_POWER_RESET);
+
+ printk (BIOS_DEBUG, "waiting for panel powerup\n");
+ while (1) {
+ u32 reg32;
+ reg32 = read32(pmmio + PP_STATUS);
+ if ((reg32 & PP_SEQUENCE_MASK) == PP_SEQUENCE_NONE)
+ break;
+ }
+ printk (BIOS_DEBUG, "panel powered up\n");
+
+ write32(pmmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
+
+ /* Clear interrupts. */
+ write32(pmmio + DEIIR, 0xffffffff);
+ write32(pmmio + SDEIIR, 0xffffffff);
+ write32(pmmio + IIR, 0xffffffff);
+ write32(pmmio + IMR, 0xffffffff);
+ write32(pmmio + EIR, 0xffffffff);
+
+ if (gtt_setup(pmmio)) {
+ printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n");
+ return 0;
+ }
+
+ /* Setup GTT. */
+
+ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
+ uma_size = 0;
+ if (!(reg16 & 2)) {
+ reg16 >>= 4;
+ reg16 &= 7;
+ switch (reg16) {
+ case 1:
+ uma_size = 1024;
+ break;
+ case 3:
+ uma_size = 8192;
+ break;
+ }
+
+ printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
+ }
+
+ for (i = 0; i < (uma_size - 256) / 4; i++)
+ {
+ outl((i << 2) | 1, piobase);
+ outl(pphysbase + (i << 12) + 1, piobase + 4);
+ }
+
+ temp = read32(pmmio + PGETBL_CTL);
+ printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp);
+
+ if (temp & 1)
+ printk(BIOS_INFO, "GTT Enabled\n");
+ else
+ printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n");
+
+#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
+ vga_misc_write(0x67);
+
+ write32(pmmio + DSPCNTR(0), DISPPLANE_SEL_PIPE_B);
+
+ write32(pmmio + VGACNTRL, 0x02c4008e | VGA_PIPE_B_SELECT);
+
+ vga_textmode_init();
+#else
+ printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n",
+ (void *)pgfx, hactive * vactive * 4);
+ memset((void *)pgfx, 0x00, hactive * vactive * 4);
+
+ set_vbe_mode_info_valid(&edid, pgfx);
+#endif
+ return 0;
+}
+#endif
+
+static void gma_func0_init(struct device *dev)
+{
+ u32 reg32;
+
+ /* Unconditionally reset graphics */
+ pci_write_config8(dev, GDRST, 1);
+ udelay(50);
+ pci_write_config8(dev, GDRST, 0);
+ /* wait for device to finish */
+ while (pci_read_config8(dev, GDRST) & 1) { };
+
+ /* IGD needs to be Bus Master */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER
+ | PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
+
+#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
+ /* PCI Init, will run VBIOS */
+ pci_dev_init(dev);
+#endif
+
+
+#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
+ /* This should probably run before post VBIOS init. */
+ printk(BIOS_SPEW, "Initializing VGA without OPROM.\n");
+ void *mmiobase;
+ u32 iobase, graphics_base;
+ struct northbridge_intel_pineview_config *conf = dev->chip_info;
+
+ iobase = dev->resource_list[1].base;
+ mmiobase = (void *)(uintptr_t)dev->resource_list[0].base;
+ graphics_base = dev->resource_list[2].base;
+
+ printk(BIOS_SPEW, "GMADR=0x%08x GTTADR=0x%08x\n",
+ pci_read_config32(dev, GMADR),
+ pci_read_config32(dev, GTTADR)
+ );
+
+ int err;
+ err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf,
+ iobase, mmiobase, graphics_base);
+ if (err == 0)
+ gfx_set_init_done(1);
+#endif
+}
+
+/* This doesn't reclaim stolen UMA memory, but IGD could still
+ be reenabled later. */
+static void gma_func0_disable(struct device *dev)
+{
+ struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0));
+
+ pci_write_config16(dev, GCFC, 0xa00);
+ pci_write_config16(dev_host, GGC, (1 << 1));
+
+ unsigned int reg32 = pci_read_config32(dev_host, DEVEN);
+ reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1);
+ pci_write_config32(dev_host, DEVEN, reg32);
+
+ dev->enabled = 0;
+}
+
+static void gma_func1_init(struct device *dev)
+{
+ u32 reg32;
+
+ /* IGD needs to be Bus Master, also enable IO accesss */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ pci_write_config32(dev, PCI_COMMAND, reg32 |
+ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+
+ /* Permanently set tft_brightness to 0xff. Ignore nvramtool configuration */
+ pci_write_config8(dev, 0xf4, 0xff);
+}
+
+static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+ if (!vendor || !device) {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ pci_read_config32(dev, PCI_VENDOR_ID));
+ } else {
+ pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+ }
+}
+
+const struct i915_gpu_controller_info *
+intel_gma_get_controller_info(void)
+{
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
+ if (!dev) {
+ return NULL;
+ }
+ struct northbridge_intel_pineview_config *chip = dev->chip_info;
+ if (!chip) {
+ return NULL;
+ }
+ return &chip->gfx;
+}
+
+static void gma_ssdt(device_t device)
+{
+ const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
+ if (!gfx) {
+ return;
+ }
+
+ drivers_intel_gma_displays_ssdt_generate(gfx);
+}
+
+static struct pci_operations gma_pci_ops = {
+ .set_subsystem = gma_set_subsystem,
+};
+
+static struct device_operations gma_func0_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = gma_func0_init,
+ .acpi_fill_ssdt_generator = gma_ssdt,
+ .scan_bus = 0,
+ .enable = 0,
+ .disable = gma_func0_disable,
+ .ops_pci = &gma_pci_ops,
+};
+
+
+static struct device_operations gma_func1_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = gma_func1_init,
+ .scan_bus = 0,
+ .enable = 0,
+ .ops_pci = &gma_pci_ops,
+};
+
+static const unsigned short pci_device_ids[] = { 0x27a2, 0x27ae, 0 };
+
+static const struct pci_driver i945_gma_func0_driver __pci_driver = {
+ .ops = &gma_func0_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
+
+static const struct pci_driver i945_gma_func1_driver __pci_driver = {
+ .ops = &gma_func1_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x27a6,
+};
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
new file mode 100644
index 0000000..f19ce6f
--- /dev/null
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -0,0 +1,286 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/hypertransport.h>
+#include <stdlib.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <boot/tables.h>
+#include <arch/acpi.h>
+#include <cbmem.h>
+#include "pineview.h"
+#include "arch/acpi.h"
+
+/* Reserve segments A and B:
+ *
+ * 0xa0000 - 0xbffff: legacy VGA
+ */
+static const int legacy_hole_base_k = 0xa0000 / 1024;
+static const int legacy_hole_size_k = 128;
+
+static int decode_pcie_bar(u32 *const base, u32 *const len)
+{
+ *base = 0;
+ *len = 0;
+
+ const device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+ if (!dev)
+ return 0;
+
+ const u32 pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
+
+ if (!(pciexbar_reg & (1 << 0)))
+ return 0;
+
+ switch ((pciexbar_reg >> 1) & 3) {
+ case 0: /* 256MB */
+ *base = pciexbar_reg & (0x0f << 28);
+ *len = 256 * 1024 * 1024;
+ return 1;
+ case 1: /* 128M */
+ *base = pciexbar_reg & (0x1f << 27);
+ *len = 128 * 1024 * 1024;
+ return 1;
+ case 2: /* 64M */
+ *base = pciexbar_reg & (0x3f << 26);
+ *len = 64 * 1024 * 1024;
+ return 1;
+ }
+
+ return 0;
+}
+
+static void mch_domain_read_resources(device_t dev)
+{
+ u64 tom, touud;
+ u32 tomk, tolud, uma_sizek = 0, usable_tomk;
+ u32 pcie_config_base, pcie_config_size;
+
+ /* Total Memory 2GB example:
+ *
+ * 00000000 0000MB-2014MB 2014MB RAM (writeback)
+ * 7de00000 2014MB-2016MB 2MB GFX GTT (uncached)
+ * 7e000000 2016MB-2048MB 32MB GFX UMA (uncached)
+ * 80000000 2048MB TOLUD
+ * 80000000 2048MB TOM
+ *
+ * Total Memory 4GB example:
+ *
+ * 00000000 0000MB-3038MB 3038MB RAM (writeback)
+ * bde00000 3038MB-3040MB 2MB GFX GTT (uncached)
+ * be000000 3040MB-3072MB 32MB GFX UMA (uncached)
+ * be000000 3072MB TOLUD
+ * 100000000 4096MB TOM
+ * 100000000 4096MB-5120MB 1024MB RAM (writeback)
+ * 140000000 5120MB TOUUD
+ */
+
+ pci_domain_read_resources(dev);
+
+ /* Top of Upper Usable DRAM, including remap */
+ touud = pci_read_config16(dev, 0xa2);
+ touud <<= 20;
+
+ /* Top of Lower Usable DRAM */
+ tolud = pci_read_config16(dev, 0xb0) & 0xfff0;
+ tolud <<= 16;
+
+ /* Top of Memory - does not account for any UMA */
+ tom = pci_read_config16(dev, 0xa0) & 0x1ff;
+ tom <<= 27;
+
+ printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n",
+ touud, tolud, tom);
+
+ tomk = tolud >> 10;
+
+ /* Graphics memory comes next */
+ const u16 ggc = pci_read_config16(dev, GGC);
+
+ /* Graphics memory */
+ const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf);
+ printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10);
+ tomk -= gms_sizek;
+
+ /* GTT Graphics Stolen Memory Size (GGMS) */
+ const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf);
+ printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10);
+ tomk -= gsm_sizek;
+
+ uma_sizek = gms_sizek + gsm_sizek;
+
+ usable_tomk = ALIGN_DOWN(tomk, 64 << 10);
+ if (tomk - usable_tomk > (16 << 10))
+ usable_tomk = tomk;
+
+ printk(BIOS_INFO, "Available memory below 4GB: %uM\n", usable_tomk >> 10);
+
+ /* Report the memory regions */
+ ram_resource(dev, 3, 0, legacy_hole_base_k);
+ ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k,
+ (usable_tomk - (legacy_hole_base_k + legacy_hole_size_k)));
+
+ mmio_resource(dev, 5, legacy_hole_base_k,
+ (0xc0000 >> 10) - legacy_hole_base_k);
+
+ /*
+ * If >= 4GB installed then memory from TOLUD to 4GB
+ * is remapped above TOM, TOUUD will account for both
+ */
+ touud >>= 10; /* Convert to KB */
+ if (touud > 4096 * 1024) {
+ ram_resource(dev, 6, 4096 * 1024, touud - (4096 * 1024));
+ printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
+ (touud >> 10) - 4096);
+ }
+
+ printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx "
+ "size=0x%llx\n", ((u64)tomk) << 10, ((u64)uma_sizek) << 10);
+ /* Don't use uma_resource() as our UMA touches the PCI hole. */
+ fixed_mem_resource(dev, 7, tomk, uma_sizek, IORESOURCE_RESERVE);
+
+ if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) {
+ printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
+ "size=0x%x\n", pcie_config_base, pcie_config_size);
+ fixed_mem_resource(dev, 8, pcie_config_base >> 10,
+ pcie_config_size >> 10, IORESOURCE_RESERVE);
+ }
+
+ set_top_of_ram(tomk << 10);
+}
+
+static void mch_domain_set_resources(device_t dev)
+{
+ struct resource *resource;
+ int i;
+
+ for (i = 3; i < 9; ++i) {
+ /* Report read resources. */
+ resource = probe_resource(dev, i);
+ if (resource)
+ report_resource_stored(dev, resource, "");
+ }
+
+ assign_resources(dev->link_list);
+}
+
+static void mch_domain_init(device_t dev)
+{
+ u32 reg32;
+
+ /* Enable SERR */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 |= PCI_COMMAND_SERR;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+}
+
+static struct device_operations pci_domain_ops = {
+ .read_resources = mch_domain_read_resources,
+ .set_resources = mch_domain_set_resources,
+ .enable_resources = NULL,
+ .init = mch_domain_init,
+ .scan_bus = pci_domain_scan_bus,
+ .ops_pci_bus = pci_bus_default_ops,
+};
+
+static void cpu_bus_init(device_t dev)
+{
+ initialize_cpus(dev->link_list);
+}
+
+static struct device_operations cpu_bus_ops = {
+ .read_resources = DEVICE_NOOP,
+ .set_resources = DEVICE_NOOP,
+ .enable_resources = DEVICE_NOOP,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
+};
+
+
+static void enable_dev(device_t dev)
+{
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+#if CONFIG_HAVE_ACPI_RESUME
+ switch (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), /*D0F0_SKPD*/0xdc)) {
+ case SKPAD_NORMAL_BOOT_MAGIC:
+ printk(BIOS_DEBUG, "Normal boot.\n");
+ acpi_slp_type=0;
+ break;
+ case SKPAD_ACPI_S3_MAGIC:
+ printk(BIOS_DEBUG, "S3 Resume.\n");
+ acpi_slp_type=3;
+ break;
+ default:
+ printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
+ acpi_slp_type=0;
+ break;
+ }
+#endif
+ } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
+ dev->ops = &cpu_bus_ops;
+ }
+}
+
+static void pineview_init(void *const chip_info)
+{
+ int dev, fn, bit_base;
+
+ struct device *const d0f0 = dev_find_slot(0, 0);
+
+ /* Hide internal functions based on devicetree info. */
+ for (dev = 3; dev > 0; --dev) {
+ switch (dev) {
+ case 3: /* ME */
+ fn = 3;
+ bit_base = 6;
+ break;
+ case 2: /* IGD */
+ fn = 1;
+ bit_base = 3;
+ break;
+ case 1: /* PEG */
+ fn = 0;
+ bit_base = 1;
+ break;
+ }
+ for (; fn >= 0; --fn) {
+ const struct device *const d =
+ dev_find_slot(0, PCI_DEVFN(dev, fn));
+ if (!d || d->enabled) continue;
+ const u32 deven = pci_read_config32(d0f0, DEVEN);
+ pci_write_config32(d0f0, DEVEN,
+ deven & ~(1 << (bit_base + fn)));
+ }
+ }
+
+ const u32 deven = pci_read_config32(d0f0, DEVEN);
+ if (!(deven & (0xf << 6)))
+ pci_write_config32(d0f0, DEVEN, deven & ~(1 << 14));
+}
+
+struct chip_operations northbridge_intel_pineview_ops = {
+ CHIP_NAME("Intel Pineview Northbridge")
+ .enable_dev = enable_dev,
+ .init = pineview_init,
+};
diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h
index 5441dc9..93beb95 100644
--- a/src/northbridge/intel/pineview/pineview.h
+++ b/src/northbridge/intel/pineview/pineview.h
@@ -18,6 +18,172 @@
#include <northbridge/intel/pineview/iomap.h>
+typedef enum {
+ FSB_CLOCK_667MHz = 0,
+ FSB_CLOCK_800MHz = 1,
+} fsb_clock_t;
+
+typedef enum {
+ MEM_CLOCK_667MHz = 0,
+ MEM_CLOCK_800MHz = 1,
+} mem_clock_t;
+
+typedef enum {
+ DDR2 = 2,
+ DDR3 = 3,
+} ddr_t;
+
+typedef enum { /* as in DDR3 spd */
+ CHIP_WIDTH_x4 = 0,
+ CHIP_WIDTH_x8 = 1,
+ CHIP_WIDTH_x16 = 2,
+ CHIP_WIDTH_x32 = 3,
+} chip_width_t;
+
+typedef enum { /* as in DDR3 spd */
+ CHIP_CAP_256M = 0,
+ CHIP_CAP_512M = 1,
+ CHIP_CAP_1G = 2,
+ CHIP_CAP_2G = 3,
+ CHIP_CAP_4G = 4,
+ CHIP_CAP_8G = 5,
+ CHIP_CAP_16G = 6,
+} chip_capacity_t;
+
+typedef struct {
+ unsigned int CAS;
+ fsb_clock_t fsb_clock;
+ mem_clock_t mem_clock;
+ unsigned int tRAS;
+ unsigned int tRP;
+ unsigned int tRCD;
+ unsigned int tWR;
+ unsigned int tRFC;
+ unsigned int tWTR;
+ unsigned int tRRD;
+ unsigned int tRTP;
+} timings_t;
+
+typedef struct {
+ unsigned int card_type; /* 0x0: unpopulated,
+ 0xa - 0xf: raw card type A - F */
+ u8 type;
+ chip_width_t width;
+ chip_capacity_t chip_capacity;
+ unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */
+ unsigned int sides;
+ unsigned int banks;
+ unsigned int ranks;
+ unsigned int rows;
+ unsigned int cols;
+ unsigned int cas_latencies;
+ unsigned int tAAmin;
+ unsigned int tCKmin;
+ unsigned int tWR;
+ unsigned int tRP;
+ unsigned int tRCD;
+ unsigned int tRAS;
+ unsigned int rank_capacity_mb; /* per rank in Mega Bytes */
+ u8 spd_data[256];
+} dimminfo_t;
+
+struct pllparam {
+ u8 kcoarse[2][72];
+ u8 pi[2][72];
+ u8 dben[2][72];
+ u8 dbsel[2][72];
+ u8 clkdelay[2][72];
+} __attribute__ ((packed));
+
+typedef struct sys_info {
+ u8 maxpi;
+ u8 pioffset;
+ u8 pi[8];
+ u16 coarsectrl;
+ u16 coarsedelay;
+ u16 mediumphase;
+ u16 readptrdelay;
+
+ int txt_enabled;
+ int cores;
+ int boot_path;
+ int max_ddr2_mhz;
+ int max_ddr3_mt;
+ int max_fsb_mhz;
+ int max_render_mhz;
+ int enable_igd;
+ int enable_peg;
+ u16 ggc;
+
+ int dimm_config[2];
+ int dimms_per_ch;
+ int spd_type;
+ int channel_capacity[2];
+ timings_t selected_timings;
+ dimminfo_t dimms[4];
+ u8 spd_map[4];
+
+ u8 nodll;
+ u8 async;
+ u8 dt0mode;
+ u8 mvco4x; /* 0 (8x) or 1 (4x) */
+} sysinfo_t;
+
+#define DIMM_TCO_BASE 0x30
+#define BURSTLENGTH 8
+
+#define BOOT_PATH_NORMAL 0
+#define BOOT_PATH_RESET 1
+#define BOOT_PATH_RESUME 2
+
+#define SYSINFO_DIMM_NOT_POPULATED 0x00
+#define SYSINFO_DIMM_X16SS 0x01
+#define SYSINFO_DIMM_X16DS 0x02
+#define SYSINFO_DIMM_X8DS 0x05
+#define SYSINFO_DIMM_X8DDS 0x06
+
+#define TOTAL_CHANNELS 1
+#define TOTAL_DIMMS 2
+
+#define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0)
+#define IF_DIMM_POPULATED(dimms, idx) if (dimms[idx].card_type != 0)
+#define ONLY_DIMMA_IS_POPULATED(dimms, ch) ( \
+ (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \
+ !DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3)))
+#define ONLY_DIMMB_IS_POPULATED(dimms, ch) ( \
+ (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3) && \
+ !DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2)))
+#define BOTH_DIMMS_ARE_POPULATED(dimms, ch) ( \
+ (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \
+ (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3))))
+#define FOR_EACH_DIMM(idx) \
+ for (idx = 0; idx < TOTAL_DIMMS; ++idx)
+#define FOR_EACH_POPULATED_DIMM(dimms, idx) \
+ FOR_EACH_DIMM(idx) IF_DIMM_POPULATED(dimms, idx)
+#define CHANNEL_IS_POPULATED(dimms, idx) ((dimms[idx<<1].card_type != 0) || (dimms[(idx<<1) + 1].card_type != 0))
+#define CHANNEL_IS_CARDF(dimms, idx) ((dimms[idx<<1].card_type == 0xf) || (dimms[(idx<<1) + 1].card_type == 0xf))
+#define IF_CHANNEL_POPULATED(dimms, idx) if ((dimms[idx<<1].card_type != 0) || (dimms[(idx<<1) + 1].card_type != 0))
+#define FOR_EACH_CHANNEL(idx) \
+ for (idx = 0; idx < TOTAL_CHANNELS; ++idx)
+#define FOR_EACH_POPULATED_CHANNEL(dimms, idx) \
+ FOR_EACH_CHANNEL(idx) IF_CHANNEL_POPULATED(dimms, idx)
+
+#define RANKS_PER_CHANNEL 4
+#define RANK_IS_POPULATED(dimms, ch, r) \
+ ((dimms[ch<<1].card_type && ((r) < dimms[ch<<1].ranks)) || \
+ (dimms[(ch<<1) + 1].card_type && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2))))
+#define IF_RANK_POPULATED(dimms, ch, r) \
+ if ((dimms[ch<<1].card_type && ((r) < dimms[ch<<1].ranks)) || \
+ (dimms[(ch<<1) + 1].card_type && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2))))
+#define FOR_EACH_RANK_IN_CHANNEL(r) \
+ for (r = 0; r < RANKS_PER_CHANNEL; ++r)
+#define FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) \
+ FOR_EACH_RANK_IN_CHANNEL(r) IF_RANK_POPULATED(dimms, ch, r)
+#define FOR_EACH_RANK(ch, r) \
+ FOR_EACH_CHANNEL(ch) FOR_EACH_RANK_IN_CHANNEL(r)
+#define FOR_EACH_POPULATED_RANK(dimms, ch, r) \
+ FOR_EACH_RANK(ch, r) IF_RANK_POPULATED(dimms, ch, r)
+
/* Device 0:0.0 PCI configuration space (Host Bridge) */
#define EPBAR 0x40
@@ -56,7 +222,7 @@
#define TOUUD 0xa2
#define GBSM 0xa4
#define BGSM 0xa8
-#define TSEGMB 0xac
+#define TSEG 0xac
#define TOLUD 0xb0 /* Top of Low Used Memory */
#define ERRSTS 0xc8
#define ERRCMD 0xca
@@ -84,6 +250,8 @@
#define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */
+#define GPIO32(x) *((volatile u32 *)(DEFAULT_GPIOBASE + x))
+
/*
* MCHBAR
*/
@@ -108,7 +276,14 @@
#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
+void pineview_early_initialization(void);
+u32 decode_igd_memory_size(const u32 gms);
+u32 decode_igd_gtt_size(const u32 gsm);
+
/* provided by mainboard code */
void setup_ich7_gpios(void);
+struct acpi_rsdp;
+unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp);
+
#endif /* NORTHBRIDGE_INTEL_PINEVIEW_H */
diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c
index a898cc0..ae743eb 100644
--- a/src/northbridge/intel/pineview/ram_calc.c
+++ b/src/northbridge/intel/pineview/ram_calc.c
@@ -14,45 +14,55 @@
* GNU General Public License for more details.
*/
-/* Use simple device model for this file even in ramstage */
#define __SIMPLE_DEVICE__
#include <arch/io.h>
+#include <console/console.h>
#include <cbmem.h>
#include <northbridge/intel/pineview/pineview.h>
-static void *find_ramtop(void)
+/** Decodes used Graphics Mode Select (GMS) to kilobytes. */
+u32 decode_igd_memory_size(const u32 gms)
{
- uint32_t tom;
-
- if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) {
- /* IGD enabled, get top of Memory from BSM register */
- tom = pci_read_config32(PCI_DEV(0,2,0), BSM);
- } else
- tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24;
-
- /* if TSEG enabled subtract size */
- switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM) & 0x07) {
- case 0x01:
- /* 1MB TSEG */
- tom -= 0x100000;
- break;
- case 0x03:
- /* 2MB TSEG */
- tom -= 0x200000;
- break;
- case 0x05:
- /* 8MB TSEG */
- tom -= 0x800000;
- break;
+ switch (gms) {
+ case 0:
+ return 0;
+ case 1:
+ return 1 << 10;
+ case 2:
+ return 4 << 10;
+ case 3:
+ return 8 << 10;
+ case 4:
+ return 16 << 10;
+ case 5:
+ return 32 << 10;
+ case 6:
+ return 48 << 10;
+ case 7:
+ return 64 << 10;
+ case 8:
+ return 128 << 10;
+ case 9:
+ return 256 << 10;
default:
- /* TSEG either disabled or invalid */
- break;
+ printk(BIOS_DEBUG, "Bad Graphics Mode Select (GMS) setting.\n");
+ return 0;
}
- return (void *) tom;
}
-void *cbmem_top(void)
+/** Decodes used Graphics Stolen Memory (GSM) to kilobytes. */
+u32 decode_igd_gtt_size(const u32 gsm)
{
- return find_ramtop();
+ switch (gsm) {
+ case 2:
+ case 3:
+ case 0:
+ return 0;
+ case 1:
+ return 1 << 10;
+ default:
+ printk(BIOS_DEBUG, "Bad Graphics Stolen Memory (GSM) setting.\n");
+ return 0;
+ }
}
1
0
Patch set updated for coreboot: mainboard/intel/d510mo: Add Intel D510MO mainboard
by Damien Zammit 20 Nov '15
by Damien Zammit 20 Nov '15
20 Nov '15
Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10074
-gerrit
commit a26f3f9f76e1f6fce7f51dbb59a9d13def769632
Author: Damien Zammit <damien(a)zamaudio.com>
Date: Mon May 4 10:41:21 2015 +1000
mainboard/intel/d510mo: Add Intel D510MO mainboard
Board uses Pineview native raminit
Board boots grub -> linux kernel
NB: For fully functional board, this currently needs patch:
6311,
otherwise board gets stuck on parallel SMI init.
VGA needs work, currently headless machine.
Change-Id: I8e459c6d40e0711fac8fb8cfbf31d9cb2aaab3aa
Signed-off-by: Damien Zammit <damien(a)zamaudio.com>
---
src/mainboard/intel/d510mo/Kconfig | 47 ++++++++
src/mainboard/intel/d510mo/Kconfig.name | 2 +
src/mainboard/intel/d510mo/Makefile.inc | 1 +
src/mainboard/intel/d510mo/acpi/ec.asl | 49 ++++++++
src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl | 82 +++++++++++++
src/mainboard/intel/d510mo/acpi/mainboard.asl | 34 ++++++
.../intel/d510mo/acpi/pineview_pci_irqs.asl | 69 +++++++++++
src/mainboard/intel/d510mo/acpi/superio.asl | 45 +++++++
src/mainboard/intel/d510mo/acpi_tables.c | 32 +++++
src/mainboard/intel/d510mo/board_info.txt | 5 +
src/mainboard/intel/d510mo/cstates.c | 7 ++
src/mainboard/intel/d510mo/devicetree.cb | 86 +++++++++++++
src/mainboard/intel/d510mo/dsdt.asl | 40 ++++++
src/mainboard/intel/d510mo/hda_verb.c | 7 ++
src/mainboard/intel/d510mo/romstage.c | 134 +++++++++++++++++++++
15 files changed, 640 insertions(+)
diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig
new file mode 100644
index 0000000..11944c9
--- /dev/null
+++ b/src/mainboard/intel/d510mo/Kconfig
@@ -0,0 +1,47 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+if BOARD_INTEL_D510MO
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select CPU_INTEL_SOCKET_FCBGA559
+ select NORTHBRIDGE_INTEL_PINEVIEW
+ select SOUTHBRIDGE_INTEL_I82801GX
+ select SUPERIO_WINBOND_W83627THG
+ select HAVE_ACPI_TABLES
+ select BOARD_ROMSIZE_KB_1024
+
+config MAX_CPUS
+ int
+ default 4
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xe0000000
+
+config CBFS_SIZE
+ hex "Size of CBFS filesystem in ROM"
+ default 0x100000
+
+config MAINBOARD_DIR
+ string
+ default intel/d510mo
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "D510MO"
+
+endif # BOARD_INTEL_D510MO
diff --git a/src/mainboard/intel/d510mo/Kconfig.name b/src/mainboard/intel/d510mo/Kconfig.name
new file mode 100644
index 0000000..2df0dca
--- /dev/null
+++ b/src/mainboard/intel/d510mo/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_INTEL_D510MO
+ bool "D510MO"
diff --git a/src/mainboard/intel/d510mo/Makefile.inc b/src/mainboard/intel/d510mo/Makefile.inc
new file mode 100644
index 0000000..f9621db
--- /dev/null
+++ b/src/mainboard/intel/d510mo/Makefile.inc
@@ -0,0 +1 @@
+ramstage-y += cstates.c
diff --git a/src/mainboard/intel/d510mo/acpi/ec.asl b/src/mainboard/intel/d510mo/acpi/ec.asl
new file mode 100644
index 0000000..31c7001
--- /dev/null
+++ b/src/mainboard/intel/d510mo/acpi/ec.asl
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Device(EC0)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 1)
+
+ Method (_CRS, 0)
+ {
+ Name (ECMD, ResourceTemplate()
+ {
+ IO (Decode16, 0x62, 0x62, 0, 1)
+ IO (Decode16, 0x66, 0x66, 0, 1)
+ })
+
+ Return (ECMD)
+ }
+
+ Method (_REG, 2)
+ {
+ // This method is needed by Windows XP/2000
+ // for EC initialization before a driver
+ // is loaded
+ }
+
+ Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI
+
+ // TODO EC Query methods
+
+ // TODO Scope _SB devices for AC power, LID, Power button
+
+}
diff --git a/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl b/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000..cf9f98c
--- /dev/null
+++ b/src/mainboard/intel/d510mo/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, 0, 22},
+ Package() { 0x0000ffff, 1, 0, 20},
+ Package() { 0x0000ffff, 2, 0, 17},
+ Package() { 0x0000ffff, 3, 0, 16},
+
+ Package() { 0x0001ffff, 0, 0, 22},
+ Package() { 0x0001ffff, 1, 0, 20},
+ Package() { 0x0001ffff, 2, 0, 17},
+ Package() { 0x0001ffff, 3, 0, 16},
+
+ Package() { 0x0002ffff, 0, 0, 22},
+ Package() { 0x0002ffff, 1, 0, 20},
+ Package() { 0x0002ffff, 2, 0, 17},
+ Package() { 0x0002ffff, 3, 0, 16},
+
+ Package() { 0x0003ffff, 0, 0, 22},
+ Package() { 0x0003ffff, 1, 0, 20},
+ Package() { 0x0003ffff, 2, 0, 17},
+ Package() { 0x0003ffff, 3, 0, 16},
+
+ Package() { 0x0005ffff, 0, 0, 22},
+ Package() { 0x0005ffff, 1, 0, 20},
+ Package() { 0x0005ffff, 2, 0, 17},
+ Package() { 0x0005ffff, 3, 0, 16},
+
+ Package() { 0x0008ffff, 0, 0, 20},
+ })
+} Else {
+ Return (Package() {
+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+ Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+ Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKB, 0},
+ Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+ Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
+ })
+}
diff --git a/src/mainboard/intel/d510mo/acpi/mainboard.asl b/src/mainboard/intel/d510mo/acpi/mainboard.asl
new file mode 100644
index 0000000..73189be
--- /dev/null
+++ b/src/mainboard/intel/d510mo/acpi/mainboard.asl
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Device (SLPB)
+{
+ Name(_HID, EisaId("PNP0C0E"))
+
+ // Wake
+ Name(_PRW, Package(){0x1d, 0x04})
+}
+
+Device (PWRB)
+{
+ Name(_HID, EisaId("PNP0C0C"))
+
+ // Wake
+ Name(_PRW, Package(){0x1d, 0x04})
+}
diff --git a/src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl b/src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl
new file mode 100644
index 0000000..a36cca4
--- /dev/null
+++ b/src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * i945
+ */
+
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, 0, 22 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, 0, 17 },
+ Package() { 0x001cffff, 1, 0, 16 },
+ Package() { 0x001cffff, 2, 0, 18 },
+ Package() { 0x001cffff, 3, 0, 19 },
+ // USB and EHCI 0:1d.x
+ Package() { 0x001dffff, 0, 0, 23 },
+ Package() { 0x001dffff, 1, 0, 19 },
+ Package() { 0x001dffff, 2, 0, 18 },
+ Package() { 0x001dffff, 3, 0, 16 },
+ // PCI 0:1e.0
+ Package() { 0x001effff, 0, 0, 22 },
+ // SATA/SMBUS (not 0:1f.0), 0:1f.2, 0:1f.3
+ Package() { 0x001fffff, 2, 0, 19 },
+ Package() { 0x001fffff, 3, 0, 19 },
+ })
+ } Else {
+ Return (Package() {
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ // USB and EHCI 0:1d.x
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+ // PCI 0:1e.0
+ Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+ // SATA/SMBUS 0:1f.2, 0:1f.3
+ Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ })
+ }
+}
diff --git a/src/mainboard/intel/d510mo/acpi/superio.asl b/src/mainboard/intel/d510mo/acpi/superio.asl
new file mode 100644
index 0000000..d615242
--- /dev/null
+++ b/src/mainboard/intel/d510mo/acpi/superio.asl
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+Device (SIO1)
+{
+ Name (_HID, EISAID("PNP0A05"))
+ Name (_UID, 1)
+
+ Device (UAR1)
+ {
+ Name(_HID, EISAID("PNP0501"))
+ Name(_UID, 1)
+
+ // Some methods need an implementation here:
+ // missing: _STA, _DIS, _CRS, _PRS,
+ // missing: _SRS, _PS0, _PS3
+ }
+
+ Device (UAR2)
+ {
+ Name(_HID, EISAID("PNP0501"))
+ Name(_UID, 2)
+
+ // Some methods need an implementation here:
+ // missing: _STA, _DIS, _CRS, _PRS,
+ // missing: _SRS, _PS0, _PS3
+ }
+}
diff --git a/src/mainboard/intel/d510mo/acpi_tables.c b/src/mainboard/intel/d510mo/acpi_tables.c
new file mode 100644
index 0000000..677ebcf
--- /dev/null
+++ b/src/mainboard/intel/d510mo/acpi_tables.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <arch/ioapic.h>
+
+#include "southbridge/intel/i82801gx/nvs.h"
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+}
diff --git a/src/mainboard/intel/d510mo/board_info.txt b/src/mainboard/intel/d510mo/board_info.txt
new file mode 100644
index 0000000..192798a
--- /dev/null
+++ b/src/mainboard/intel/d510mo/board_info.txt
@@ -0,0 +1,5 @@
+Category: desktop
+Board URL: http://www.intel.com/p/en_US/support/highlights/dsktpboards/d510mo
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
diff --git a/src/mainboard/intel/d510mo/cstates.c b/src/mainboard/intel/d510mo/cstates.c
new file mode 100644
index 0000000..2d543ff
--- /dev/null
+++ b/src/mainboard/intel/d510mo/cstates.c
@@ -0,0 +1,7 @@
+#include <device/device.h>
+#include <arch/x86/include/arch/acpigen.h>
+
+int get_cst_entries(acpi_cstate_t **entries)
+{
+ return 0;
+}
diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb
new file mode 100644
index 0000000..42a12c3
--- /dev/null
+++ b/src/mainboard/intel/d510mo/devicetree.cb
@@ -0,0 +1,86 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+chip northbridge/intel/pineview # Northbridge
+ device cpu_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_FCBGA559 # CPU
+ device lapic 0 on end # APIC
+ end
+ end
+ device domain 0 on # PCI domain
+ device pci 0.0 on end # Host Bridge
+ device pci 2.0 off end # Integrated graphics controller
+ chip southbridge/intel/i82801gx # Southbridge
+ register "ide_legacy_combined" = "0x1"
+ register "ide_enable_primary" = "0x1"
+ register "ide_enable_secondary" = "0x0"
+ register "sata_ahci" = "0x0"
+
+ device pci 1b.0 on end # Audio
+ device pci 1c.0 on end # PCIe 1
+ device pci 1c.1 on end # PCIe 2
+ device pci 1c.2 on end # PCIe 3
+ device pci 1c.3 on end # PCIe 4
+ device pci 1d.0 on end # USB
+ device pci 1d.1 on end # USB
+ device pci 1d.2 on end # USB
+ device pci 1d.3 on end # USB
+ device pci 1d.7 on end # USB
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on # ISA bridge
+ chip superio/winbond/w83627thg # Super I/O
+ device pnp 4e.0 off end # Floppy
+ device pnp 4e.1 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ irq 0x74 = 4
+ end
+ device pnp 4e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 4e.3 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ irq 0xf1 = 0
+ end
+ device pnp 4e.5 on # PS/2 keyboard / mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ irq 0xf0 = 0x80
+ end
+ device pnp 4e.6 off end
+ device pnp 4e.7 off end
+ device pnp 4e.8 off end
+ device pnp 4e.9 off end
+ device pnp 4e.a off end # ACPI
+ device pnp 4e.b on # HWM
+ io 0x60 = 0x290
+ irq 0x70 = 0
+ end
+ end
+ end
+ device pci 1f.1 off end
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on end # SMbus
+ device pci 1f.4 off end
+ device pci 1f.5 off end
+ device pci 1f.6 off end
+ end
+ end
+end
diff --git a/src/mainboard/intel/d510mo/dsdt.asl b/src/mainboard/intel/d510mo/dsdt.asl
new file mode 100644
index 0000000..b37c213
--- /dev/null
+++ b/src/mainboard/intel/d510mo/dsdt.asl
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20090419 // OEM revision
+)
+{
+ #include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+
+ // mainboard specific devices
+ #include "acpi/mainboard.asl"
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/pineview/acpi/pineview.asl>
+ #include <southbridge/intel/i82801gx/acpi/ich7.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/intel/d510mo/hda_verb.c b/src/mainboard/intel/d510mo/hda_verb.c
new file mode 100644
index 0000000..072a306
--- /dev/null
+++ b/src/mainboard/intel/d510mo/hda_verb.c
@@ -0,0 +1,7 @@
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[0] = {};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
new file mode 100644
index 0000000..5bb6cb3
--- /dev/null
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -0,0 +1,134 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <console/console.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+#include <northbridge/intel/pineview/raminit.h>
+#include <northbridge/intel/pineview/pineview.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/lapic.h>
+#include <superio/winbond/w83627thg/w83627thg.h>
+#include <superio/winbond/common/winbond.h>
+#include <lib.h>
+#include <arch/stages.h>
+
+#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
+#define SUPERIO_DEV PNP_DEV(0x4e, 0)
+
+#include <cpu/intel/romstage.h>
+
+/* Early mainboard specific GPIO setup */
+static void mb_gpio_init(void)
+{
+ device_t dev;
+
+ /* Southbridge GPIOs. */
+ dev = PCI_DEV(0x0, 0x1f, 0x0);
+
+ /* Set the value for GPIO base address register and enable GPIO. */
+ pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1));
+ pci_write_config8(dev, GPIO_CNTL, 0x10);
+
+ outl(0x1ff9f7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
+ outl(0xe0e9e803, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
+ outl(0xece9e842, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+ outl(0x00002000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
+ outl(0x000000fe, DEFAULT_GPIOBASE + 0x30);
+ outl(0x0000007e, DEFAULT_GPIOBASE + 0x34);
+ outl(0x000300f3, DEFAULT_GPIOBASE + 0x38);
+}
+
+static void nm10_enable_lpc(void)
+{
+ /* Disable Serial IRQ */
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0x00);
+ /* Decode range */
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80,
+ pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x80) | 0x0010);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,
+ CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN);
+
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x0291);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x007c);
+}
+
+static void rcba_config(void)
+{
+ /* Set up virtual channel 0 */
+ RCBA32(0x0014) = 0x80000001;
+ RCBA32(0x001c) = 0x03128010;
+
+ /* Device 1f interrupt pin register */
+ RCBA32(0x3100) = 0x00042210;
+ RCBA32(0x3108) = 0x10004321;
+
+ /* PCIe Interrupts */
+ RCBA32(0x310c) = 0x00214321;
+ /* HD Audio Interrupt */
+ RCBA32(0x3110) = 0x00000001;
+
+ /* dev irq route register */
+ RCBA16(0x3140) = 0x0132;
+ RCBA16(0x3142) = 0x0146;
+ RCBA16(0x3144) = 0x0237;
+ RCBA16(0x3146) = 0x3201;
+ RCBA16(0x3148) = 0x0146;
+
+ /* Enable IOAPIC */
+ RCBA8(0x31ff) = 0x03;
+
+ RCBA32(0x3418) = 0x003000e2;
+ RCBA32(0x3418) |= 1;
+}
+
+void main(unsigned long bist)
+{
+ const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 };
+
+ if (bist == 0)
+ enable_lapic();
+
+ /* Disable watchdog timer */
+ RCBA32(0x3410) = RCBA32(0x3410) | 0x20;
+
+ /* Set southbridge and Super I/O GPIOs. */
+ mb_gpio_init();
+
+ nm10_enable_lpc();
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+
+ report_bist_failure(bist);
+ enable_smbus();
+
+ pineview_early_initialization();
+
+ post_code(0x30);
+
+ printk(BIOS_DEBUG, "Start native raminit\n");
+ sdram_initialize(0, spd_addrmap);
+ printk(BIOS_DEBUG, "Done native raminit\n");
+
+ post_code(0x31);
+ ram_check(0x200000,0x300000);
+
+ rcba_config();
+}
1
0
Patch set updated for coreboot: northbridge/intel/pineview: Add minimal Pineview northbridge
by Damien Zammit 20 Nov '15
by Damien Zammit 20 Nov '15
20 Nov '15
Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10073
-gerrit
commit 2592cfcc08b05e350de0316707a47ba64bbd56f7
Author: Damien Zammit <damien(a)zamaudio.com>
Date: Sun May 3 21:34:38 2015 +1000
northbridge/intel/pineview: Add minimal Pineview northbridge
Based on i945. Tested on Intel D510MO mainboard,
board boots to UART console with this code.
Change-Id: I1d92a1aa6d6d767bda8379807dc26b50b9de75c9
Signed-off-by: Damien Zammit <damien(a)zamaudio.com>
---
src/northbridge/intel/pineview/Kconfig | 39 ++++++++++
src/northbridge/intel/pineview/Makefile.inc | 24 ++++++
src/northbridge/intel/pineview/acpi.c | 75 ++++++++++++++++++
src/northbridge/intel/pineview/bootblock.c | 8 ++
src/northbridge/intel/pineview/iomap.h | 26 +++++++
src/northbridge/intel/pineview/pineview.h | 114 ++++++++++++++++++++++++++++
src/northbridge/intel/pineview/ram_calc.c | 58 ++++++++++++++
7 files changed, 344 insertions(+)
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
new file mode 100644
index 0000000..6253b84
--- /dev/null
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -0,0 +1,39 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config NORTHBRIDGE_INTEL_PINEVIEW
+ bool
+
+if NORTHBRIDGE_INTEL_PINEVIEW
+
+config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select MMCONF_SUPPORT
+ select MMCONF_SUPPORT_DEFAULT
+ select HAVE_DEBUG_RAM_SETUP
+ select LAPIC_MONOTONIC_TIMER
+ select VGA
+ select PER_DEVICE_ACPI_TABLES
+
+config BOOTBLOCK_NORTHBRIDGE_INIT
+ string
+ default "northbridge/intel/pineview/bootblock.c"
+
+config VGA_BIOS_ID
+ string
+ default "8086,a001"
+
+endif
diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc
new file mode 100644
index 0000000..9330b17
--- /dev/null
+++ b/src/northbridge/intel/pineview/Makefile.inc
@@ -0,0 +1,24 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2009 coresystems GmbH
+# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+ifeq ($(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW),y)
+
+ramstage-y += ram_calc.c
+ramstage-y += acpi.c
+
+romstage-y += ram_calc.c
+
+endif
diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c
new file mode 100644
index 0000000..17ad631
--- /dev/null
+++ b/src/northbridge/intel/pineview/acpi.c
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpigen.h>
+#include <arch/acpi.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <northbridge/intel/pineview/pineview.h>
+#include <types.h>
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ device_t dev;
+ u32 pciexbar = 0;
+ u32 pciexbar_reg;
+ u32 reg32;
+ int max_buses;
+ typedef struct {
+ u16 num_buses;
+ u32 addr_mask;
+ } busmask_t;
+
+ const busmask_t table[4] = {
+ {256, 0xff000000},
+ {128, 0xf8000000},
+ {64, 0xfc000000},
+ {0, 0},
+ };
+
+ dev = dev_find_slot(0, PCI_DEVFN(0,0));
+ if (!dev)
+ return current;
+
+ pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
+
+ // MMCFG not supported or not enabled.
+ if (!(pciexbar_reg & (1 << 0))) {
+#ifdef SUPPORT_MMCONF_DEFAULT
+ printk(BIOS_WARNING, "WARNING: MMCONF not set\n");
+#endif
+ return current;
+ }
+
+ reg32 = (pciexbar_reg >> 1) & 3;
+ pciexbar = pciexbar_reg & table[reg32].addr_mask;
+ max_buses = table[reg32].num_buses;
+ if (reg32 > 2) {
+ printk(BIOS_WARNING, "WARNING: pciexbar mask out of range\n");
+ return current;
+ }
+
+ if (!pciexbar) {
+ printk(BIOS_WARNING, "WARNING: pciexbar invalid\n");
+ return current;
+ }
+
+ current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
+ pciexbar, 0x0, 0x0, max_buses - 1);
+
+ return current;
+}
diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c
new file mode 100644
index 0000000..1c04c28
--- /dev/null
+++ b/src/northbridge/intel/pineview/bootblock.c
@@ -0,0 +1,8 @@
+#include <arch/io.h>
+#define PCIEXBAR 0x60
+
+static void bootblock_northbridge_init(void)
+{
+ pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR,
+ CONFIG_MMCONF_BASE_ADDRESS | 4 | 1);
+}
diff --git a/src/northbridge/intel/pineview/iomap.h b/src/northbridge/intel/pineview/iomap.h
new file mode 100644
index 0000000..f309eaf
--- /dev/null
+++ b/src/northbridge/intel/pineview/iomap.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Northbridge */
+
+/* 4 KB per PCIe device */
+#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
+
+#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */
+#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
+#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
+
+/* Southbridge */
+#include <southbridge/intel/i82801gx/i82801gx.h>
diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h
new file mode 100644
index 0000000..5441dc9
--- /dev/null
+++ b/src/northbridge/intel/pineview/pineview.h
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef NORTHBRIDGE_INTEL_PINEVIEW_H
+#define NORTHBRIDGE_INTEL_PINEVIEW_H
+
+#include <northbridge/intel/pineview/iomap.h>
+
+/* Device 0:0.0 PCI configuration space (Host Bridge) */
+
+#define EPBAR 0x40
+#define MCHBAR 0x48
+#define PCIEXBAR 0x60
+#define DMIBAR 0x68
+#define PMIOBAR 0x78
+
+#define GGC 0x52 /* GMCH Graphics Control */
+
+#define DEVEN 0x54 /* Device Enable */
+#define DEVEN_D0F0 (1 << 0)
+#define DEVEN_D1F0 (1 << 1)
+#define DEVEN_D2F0 (1 << 3)
+#define DEVEN_D2F1 (1 << 4)
+
+#ifndef BOARD_DEVEN
+#define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 )
+#endif /* BOARD_DEVEN */
+
+#define PAM0 0x90
+#define PAM1 0x91
+#define PAM2 0x92
+#define PAM3 0x93
+#define PAM4 0x94
+#define PAM5 0x95
+#define PAM6 0x96
+
+#define LAC 0x97 /* Legacy Access Control */
+#define REMAPBASE 0x98
+#define REMAPLIMIT 0x9a
+#define SMRAM 0x9d /* System Management RAM Control */
+#define ESMRAM 0x9e /* Extended System Management RAM Control */
+
+#define TOM 0xa0
+#define TOUUD 0xa2
+#define GBSM 0xa4
+#define BGSM 0xa8
+#define TSEGMB 0xac
+#define TOLUD 0xb0 /* Top of Low Used Memory */
+#define ERRSTS 0xc8
+#define ERRCMD 0xca
+#define SMICMD 0xcc
+#define SCICMD 0xce
+#define CGDIS 0xd8
+#define SKPAD 0xdc /* Scratchpad Data */
+#define CAPID0 0xe0
+#define DEV0T 0xf0
+#define MSLCK 0xf4
+#define MID0 0xf8
+#define DEBUP0 0xfc
+
+/* Device 0:1.0 PCI configuration space (PCI Express) */
+
+#define BCTRL1 0x3e /* 16bit */
+#define PEGSTS 0x214 /* 32bit */
+
+
+/* Device 0:2.0 PCI configuration space (Graphics Device) */
+
+#define GMADR 0x18
+#define GTTADR 0x1c
+#define BSM 0x5c
+#define GCFC 0xf0 /* Graphics Clock Frequency & Gating Control */
+
+
+/*
+ * MCHBAR
+ */
+
+#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))
+#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))
+#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))
+
+/*
+ * EPBAR - Egress Port Root Complex Register Block
+ */
+
+#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
+#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
+#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
+
+/*
+ * DMIBAR
+ */
+
+#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
+#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
+#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
+
+/* provided by mainboard code */
+void setup_ich7_gpios(void);
+
+#endif /* NORTHBRIDGE_INTEL_PINEVIEW_H */
diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c
new file mode 100644
index 0000000..a898cc0
--- /dev/null
+++ b/src/northbridge/intel/pineview/ram_calc.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Use simple device model for this file even in ramstage */
+#define __SIMPLE_DEVICE__
+
+#include <arch/io.h>
+#include <cbmem.h>
+#include <northbridge/intel/pineview/pineview.h>
+
+static void *find_ramtop(void)
+{
+ uint32_t tom;
+
+ if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) {
+ /* IGD enabled, get top of Memory from BSM register */
+ tom = pci_read_config32(PCI_DEV(0,2,0), BSM);
+ } else
+ tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24;
+
+ /* if TSEG enabled subtract size */
+ switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM) & 0x07) {
+ case 0x01:
+ /* 1MB TSEG */
+ tom -= 0x100000;
+ break;
+ case 0x03:
+ /* 2MB TSEG */
+ tom -= 0x200000;
+ break;
+ case 0x05:
+ /* 8MB TSEG */
+ tom -= 0x800000;
+ break;
+ default:
+ /* TSEG either disabled or invalid */
+ break;
+ }
+ return (void *) tom;
+}
+
+void *cbmem_top(void)
+{
+ return find_ramtop();
+}
1
0
Patch set updated for coreboot: fsp_model_406dx: use external microcode .h files for rangeley
by Martin Roth 20 Nov '15
by Martin Roth 20 Nov '15
20 Nov '15
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12335
-gerrit
commit 6c73b4476fd1178cc1f4bcc11b350cba96cc091d
Author: Martin Roth <martinroth(a)google.com>
Date: Thu Nov 5 09:00:20 2015 -0700
fsp_model_406dx: use external microcode .h files for rangeley
The microcode for the Rangeley chip is supplied as .h files in the
Rangeley FSP POSTGOLD4 package.
When the rangeley microcode gets put into the blobs directory, this
can be reverted and the binary file put into the makefile.
Change-Id: I30e7436f26a247bc9431f249becfa5fe8c581be7
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
src/cpu/intel/fsp_model_406dx/Kconfig | 20 ++++++++------------
src/cpu/intel/fsp_model_406dx/Makefile.inc | 3 ---
src/cpu/intel/fsp_model_406dx/model_406dx_init.c | 3 ++-
3 files changed, 10 insertions(+), 16 deletions(-)
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
index 30e7e59..2e58b35 100644
--- a/src/cpu/intel/fsp_model_406dx/Kconfig
+++ b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -28,11 +28,14 @@ config CPU_SPECIFIC_OPTIONS
select SMP
select SSE2
select UDELAY_LAPIC
- select SUPPORT_CPU_UCODE_IN_CBFS
+ select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN
select PARALLEL_CPU_INIT
select TSC_SYNC_MFENCE
select LAPIC_MONOTONIC_TIMER
+ # Microcode header files are delivered in FSP package
+ select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN
+
choice
prompt "Rangeley CPU Stepping"
default FSP_MODEL_406DX_B0
@@ -58,16 +61,9 @@ config CPU_MICROCODE_CBFS_LOC
depends on SUPPORT_CPU_UCODE_IN_CBFS
default 0xfff60040
-config HAVE_CPU_MICROCODE_FILE
- bool "Add microcode file"
- help
- The microcode binary
-
-config CPU_MICROCODE_FILE
- string "Path and filename of CPU microcode"
- default "microcode.bin"
- depends on HAVE_CPU_MICROCODE_FILE
- help
- The path and filename of the file containing the CPU microcode.
+#set up microcode for rangeley POSTGOLD4 release
+config CPU_MICROCODE_HEADER_FILES
+ string
+ default "../intel/cpu/rangeley/microcode/microcode-m01406d000e.h ../intel/cpu/rangeley/microcode/microcode-m01406d8128.h"
endif #CPU_INTEL_FSP_MODEL_406DX
diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc
index 91c7d96..3e29348 100644
--- a/src/cpu/intel/fsp_model_406dx/Makefile.inc
+++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc
@@ -23,6 +23,3 @@ cpu_microcode_bins += $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE))
endif
CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx
-# We don't have microcode for this CPU
-# Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file
-# cpu_microcode_bins += ???
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
index 5482e74..17c46b3 100644
--- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
+++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
@@ -170,7 +170,8 @@ static void model_406dx_init(struct device *cpu)
x86_enable_cache();
/* Load microcode */
- intel_update_microcode_from_cbfs();
+ if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))
+ intel_update_microcode_from_cbfs();
/* Clear out pending MCEs */
configure_mca();
1
0
Patch set updated for coreboot: [Not for submission] test whitespace linter on jenkins
by Martin Roth 20 Nov '15
by Martin Roth 20 Nov '15
20 Nov '15
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12472
-gerrit
commit ca3a111c3e08186612b2d5635ca672bb66a97c35
Author: Martin Roth <martinroth(a)google.com>
Date: Wed Nov 18 20:32:21 2015 -0700
[Not for submission] test whitespace linter on jenkins
Change-Id: I8295e149d0e3027eb432e7a08ee9d82da135155d
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
Makefile.inc | 2 +-
src/arch/x86/Makefile.inc | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc
index 65aa71c..f6f7ba0 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -15,7 +15,7 @@
GIT:=$(shell [ -d "$(top)/.git" ] && command -v git)
-#######################################################################
+#######################################################################
# misleadingly named, this is the coreboot version
export KERNELVERSION := $(strip $(if $(GIT),\
$(shell git describe --dirty --always || git describe),\
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 03dba34..6b0a893 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -16,7 +16,7 @@
## GNU General Public License for more details.
##
-################################################################################
+################################################################################
# i386 specific tools
NVRAMTOOL:=$(objutil)/nvramtool/nvramtool
1
0
Patch set updated for coreboot: NOT-YET-FOR-MERGE add gnawty based on rambi
by Alexander Couzens 20 Nov '15
by Alexander Couzens 20 Nov '15
20 Nov '15
Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12500
-gerrit
commit 0f7e5a9141acc7ae84aad81da121ffdd6b55ca10
Author: Alexander Couzens <lynxis(a)fe80.eu>
Date: Wed May 27 22:38:08 2015 +0200
NOT-YET-FOR-MERGE add gnawty based on rambi
Gnawty is very similiar to rambi. Only the ram settings
seems to be different.
Change-Id: Ia5db801423a29888764a9cac019279c171382591
Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu>
---
src/mainboard/google/gnawty/Kconfig | 45 ++++
src/mainboard/google/gnawty/Kconfig.name | 2 +
src/mainboard/google/gnawty/Makefile.inc | 25 +++
src/mainboard/google/gnawty/acpi/chromeos.asl | 32 +++
src/mainboard/google/gnawty/acpi/dptf.asl | 71 +++++++
src/mainboard/google/gnawty/acpi/ec.asl | 20 ++
src/mainboard/google/gnawty/acpi/mainboard.asl | 215 +++++++++++++++++++
src/mainboard/google/gnawty/acpi/superio.asl | 27 +++
src/mainboard/google/gnawty/acpi/video.asl | 43 ++++
src/mainboard/google/gnawty/acpi_tables.c | 64 ++++++
src/mainboard/google/gnawty/chromeos.c | 120 +++++++++++
src/mainboard/google/gnawty/cmos.layout | 137 ++++++++++++
src/mainboard/google/gnawty/devicetree.cb | 101 +++++++++
src/mainboard/google/gnawty/dsdt.asl | 54 +++++
src/mainboard/google/gnawty/ec.c | 48 +++++
src/mainboard/google/gnawty/ec.h | 62 ++++++
src/mainboard/google/gnawty/fadt.c | 46 +++++
src/mainboard/google/gnawty/gpio.c | 230 +++++++++++++++++++++
src/mainboard/google/gnawty/irqroute.c | 18 ++
src/mainboard/google/gnawty/irqroute.h | 58 ++++++
src/mainboard/google/gnawty/mainboard.c | 181 ++++++++++++++++
src/mainboard/google/gnawty/mainboard_smi.c | 121 +++++++++++
src/mainboard/google/gnawty/onboard.h | 39 ++++
src/mainboard/google/gnawty/romstage.c | 98 +++++++++
.../spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex | 17 ++
src/mainboard/google/gnawty/spd/Makefile.inc | 49 +++++
.../spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex | 32 +++
.../spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex | 32 +++
.../spd/hynix_2GiB_dimm_H5TC4G63MFR-PBA.spd.hex | 16 ++
.../spd/kingston_2GiB_dimm_D2516EC4BXGGB.spd.hex | 16 ++
.../spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex | 32 +++
.../spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex | 32 +++
.../spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex | 17 ++
src/mainboard/google/gnawty/w25q64.c | 70 +++++++
34 files changed, 2170 insertions(+)
diff --git a/src/mainboard/google/gnawty/Kconfig b/src/mainboard/google/gnawty/Kconfig
new file mode 100644
index 0000000..1071fe7
--- /dev/null
+++ b/src/mainboard/google/gnawty/Kconfig
@@ -0,0 +1,45 @@
+if BOARD_GOOGLE_GNAWTY
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SOC_INTEL_BAYTRAIL
+ select EC_GOOGLE_CHROMEEC
+ select ENABLE_BUILTIN_COM1
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_ACPI_RESUME
+ select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
+
+config CHROMEOS
+ select CHROMEOS_VBNV_CMOS
+ select LID_SWITCH
+ select EC_SOFTWARE_SYNC
+ select VIRTUAL_DEV_SWITCH
+
+config MAINBOARD_DIR
+ string
+ default google/gnawty
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Gnawty"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0166.rom"
+
+config HAVE_IFD_BIN
+ bool
+ default n
+
+config HAVE_ME_BIN
+ bool
+ default n
+
+config HAVE_GBE_BIN
+ bool
+ default n
+
+endif # BOARD_GOOGLE_GNAWTY
diff --git a/src/mainboard/google/gnawty/Kconfig.name b/src/mainboard/google/gnawty/Kconfig.name
new file mode 100644
index 0000000..8fbb160
--- /dev/null
+++ b/src/mainboard/google/gnawty/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_GOOGLE_GNAWTY
+ bool "Gnawty"
diff --git a/src/mainboard/google/gnawty/Makefile.inc b/src/mainboard/google/gnawty/Makefile.inc
new file mode 100644
index 0000000..65221ac
--- /dev/null
+++ b/src/mainboard/google/gnawty/Makefile.inc
@@ -0,0 +1,25 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+subdirs-y += spd
+
+romstage-y += chromeos.c
+ramstage-y += chromeos.c
+ramstage-y += gpio.c
+ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
+ramstage-y += irqroute.c
+ramstage-y += w25q64.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
diff --git a/src/mainboard/google/gnawty/acpi/chromeos.asl b/src/mainboard/google/gnawty/acpi/chromeos.asl
new file mode 100644
index 0000000..3072eca
--- /dev/null
+++ b/src/mainboard/google/gnawty/acpi/chromeos.asl
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Fields are in the following order.
+ * - Type: recovery = 1 developer mode = 2 write protect = 3
+ * - Active Level - if -1 not a valid gpio
+ * - GPIO number encoding - if -1 not a valid gpio
+ * - Chipset Name
+ *
+ * Note: On Bay Trail we need to encode gpios within the 3 separate banks
+ * with the MMIO offset of each banks space. e.g. GPIO_SUS[8] would be encoded
+ * as 0x2008 where the SUS offset (IO_BASE_OFFSET_GPSSUS) is 0x2000.
+ */
+
+Name(OIPG, Package() {
+ // No physical recovery button
+ Package () { 0x0001, 0, 0xFFFFFFFF, "BayTrail" },
+ Package () { 0x0003, 1, 0x2006, "BayTrail" },
+})
diff --git a/src/mainboard/google/gnawty/acpi/dptf.asl b/src/mainboard/google/gnawty/acpi/dptf.asl
new file mode 100644
index 0000000..46e54d0
--- /dev/null
+++ b/src/mainboard/google/gnawty/acpi/dptf.asl
@@ -0,0 +1,71 @@
+#define DPTF_CPU_PASSIVE 80
+#define DPTF_CPU_CRITICAL 90
+
+#define DPTF_TSR0_SENSOR_ID 1
+#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal"
+#define DPTF_TSR0_PASSIVE 45
+#define DPTF_TSR0_CRITICAL 80
+
+#define DPTF_TSR1_SENSOR_ID 2
+#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE 70
+#define DPTF_TSR1_CRITICAL 85
+
+#define DPTF_TSR2_SENSOR_ID 3
+#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE 44
+#define DPTF_TSR2_CRITICAL 75
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+ Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */
+})
+
+/* Mainboard specific _PDL is 1GHz */
+Name (MPDL, 8)
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TCPU, 100, 50, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 0 */
+ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 300, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Charger Effect on Temp Sensor 1 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 1200, 0, 0, 0, 0 },
+#endif
+
+ /* CPU Effect on Temp Sensor 2 */
+ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, // Revision
+ Package () { // Power Limit 1
+ 0, // PowerLimitIndex, 0 for Power Limit 1
+ 1600, // PowerLimitMinimum
+ 6300, // PowerLimitMaximum
+ 1000, // TimeWindowMinimum
+ 1000, // TimeWindowMaximum
+ 200 // StepSize
+ },
+ Package () { // Power Limit 2
+ 1, // PowerLimitIndex, 1 for Power Limit 2
+ 8000, // PowerLimitMinimum
+ 8000, // PowerLimitMaximum
+ 1000, // TimeWindowMinimum
+ 1000, // TimeWindowMaximum
+ 1000 // StepSize
+ }
+})
+
+/* Include Baytrail DPTF */
+#include <soc/intel/baytrail/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/gnawty/acpi/ec.asl b/src/mainboard/google/gnawty/acpi/ec.asl
new file mode 100644
index 0000000..94976c4
--- /dev/null
+++ b/src/mainboard/google/gnawty/acpi/ec.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include <mainboard/google/gnawty/ec.h>
+
+/* ACPI code for EC functions */
+#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/gnawty/acpi/mainboard.asl b/src/mainboard/google/gnawty/acpi/mainboard.asl
new file mode 100644
index 0000000..d1aafd2
--- /dev/null
+++ b/src/mainboard/google/gnawty/acpi/mainboard.asl
@@ -0,0 +1,215 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <mainboard/google/gnawty/onboard.h>
+
+Scope (\_SB)
+{
+ Device (LID0)
+ {
+ Name (_HID, EisaId ("PNP0C0D"))
+ Name (_PRW, Package() { BOARD_PCH_WAKE_GPIO, 0x5 })
+ Method (_LID, 0)
+ {
+ Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
+ Return (\LIDS)
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, EisaId ("PNP0C0C"))
+ Name (_UID, 1)
+ }
+
+ /* Wake device for touchpad */
+ Device (TPAD)
+ {
+ Name (_HID, EisaId ("PNP0C0E"))
+ Name (_UID, 1)
+ Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+ })
+
+ Method (_CRS)
+ {
+ /* Only return interrupt if I2C1 is PCI mode */
+ If (LEqual (\S1EN, 0)) {
+ Return (^RBUF)
+ }
+ }
+ }
+
+ /* Wake device for touchscreen */
+ Device (TSCR)
+ {
+ Name (_HID, EisaId ("PNP0C0E"))
+ Name (_UID, 2)
+ Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TOUCHSCREEN_IRQ
+ }
+ })
+
+ Method (_CRS)
+ {
+ /* Only return interrupt if I2C6 is PCI mode */
+ If (LEqual (\S6EN, 0)) {
+ Return (^RBUF)
+ }
+ }
+ }
+}
+
+Scope (\_SB.I2C1)
+{
+ Device (ETPA)
+ {
+ Name (_HID, "ELAN0000")
+ Name (_DDN, "Elan Touchpad")
+ Name (_UID, 3)
+ Name (ISTP, 1) /* Touchpad */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x15, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.I2C1", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+}
+
+Scope (\_SB.I2C2)
+{
+ Device (CODC)
+ {
+ /*
+ * TODO(dlaurie): Need official HID.
+ *
+ * The current HID is created from the Maxim Integrated
+ * PCI Vendor ID 193Ch and a shortened device identifier.
+ */
+ Name (_HID, "193C9890")
+ Name (_DDN, "Maxim 98090 Codec")
+ Name (_UID, 1)
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x10, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.I2C2", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_CODEC_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S2EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+ }
+}
+
+Scope (\_SB.I2C6)
+{
+ Device (ETSA)
+ {
+ Name (_HID, "ELAN0001")
+ Name (_DDN, "ELAN Touchscreen")
+ Name (_UID, 6)
+ Name (ISTP, 0) /* TouchScreen */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x10, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.I2C6", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TOUCHSCREEN_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S6EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+}
+
+Scope (\_SB.LPEA)
+{
+ Name (GBUF, ResourceTemplate ()
+ {
+ /* Jack Detect (index 0) */
+ GpioInt (Edge, ActiveHigh, Exclusive, PullNone,,
+ "\\_SB.GPSC") { 14 }
+
+ /* Mic Detect (index 1) */
+ GpioInt (Edge, ActiveHigh, Exclusive, PullNone,,
+ "\\_SB.GPSC") { 15 }
+ })
+}
diff --git a/src/mainboard/google/gnawty/acpi/superio.asl b/src/mainboard/google/gnawty/acpi/superio.asl
new file mode 100644
index 0000000..2917a9e
--- /dev/null
+++ b/src/mainboard/google/gnawty/acpi/superio.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include <mainboard/google/gnawty/ec.h>
+#include <mainboard/google/gnawty/onboard.h>
+
+#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
+#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
+#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
+// Override default IRQ settings
+#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Edge, ActiveLow) {BOARD_I8042_IRQ}
+
+/* ACPI code for EC SuperIO functions */
+#include <ec/google/chromeec/acpi/superio.asl>
diff --git a/src/mainboard/google/gnawty/acpi/video.asl b/src/mainboard/google/gnawty/acpi/video.asl
new file mode 100644
index 0000000..3ececa9
--- /dev/null
+++ b/src/mainboard/google/gnawty/acpi/video.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+ // TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+ // TODO (no displays defined yet)
+}
+
diff --git a/src/mainboard/google/gnawty/acpi_tables.c b/src/mainboard/google/gnawty/acpi_tables.c
new file mode 100644
index 0000000..c647c9b
--- /dev/null
+++ b/src/mainboard/google/gnawty/acpi_tables.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+#include <soc/iomap.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ acpi_init_gnvs(gnvs);
+
+ /* Enable USB ports in S3 */
+ gnvs->s3u0 = 1;
+ gnvs->s3u1 = 1;
+
+ /* Disable USB ports in S5 */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* TPM Present */
+ gnvs->tpmp = 1;
+
+ /* Enable DPTF */
+ gnvs->dpte = 1;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ current = acpi_madt_irq_overrides(current);
+
+ return current;
+}
diff --git a/src/mainboard/google/gnawty/chromeos.c b/src/mainboard/google/gnawty/chromeos.c
new file mode 100644
index 0000000..3f2e9c0
--- /dev/null
+++ b/src/mainboard/google/gnawty/chromeos.c
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <bootmode.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <soc/gpio.h>
+
+#if CONFIG_EC_GOOGLE_CHROMEEC
+#include "ec.h"
+#include <ec/google/chromeec/ec.h>
+#endif
+
+/* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */
+#define WP_STATUS_PAD 36
+
+#ifndef __PRE_RAM__
+#include <boot/coreboot_tables.h>
+
+#define GPIO_COUNT 6
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio *gpio;
+
+ gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
+ gpios->count = GPIO_COUNT;
+
+ gpio = gpios->gpios;
+ fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect",
+ get_write_protect_state());
+ fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery",
+ recovery_mode_enabled());
+ fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer",
+ get_developer_mode_switch());
+ fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", get_lid_switch());
+ fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0);
+ fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done());
+}
+#endif
+
+int get_lid_switch(void)
+{
+#if CONFIG_EC_GOOGLE_CHROMEEC
+ u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
+
+ return !!(ec_switches & EC_SWITCH_LID_OPEN);
+#else
+ /* Default to force open. */
+ return 1;
+#endif
+}
+
+int get_developer_mode_switch(void)
+{
+ return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+#if CONFIG_EC_GOOGLE_CHROMEEC
+ u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
+ u32 ec_events;
+
+ /* If a switch is set, we don't need to look at events. */
+ if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY))
+ return 1;
+
+ /* Else check if the EC has posted the keyboard recovery event. */
+ ec_events = google_chromeec_get_events_b();
+
+ return !!(ec_events &
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+#else
+ return 0;
+#endif
+}
+
+int clear_recovery_mode_switch(void)
+{
+#if CONFIG_EC_GOOGLE_CHROMEEC
+ const uint32_t kb_rec_mask =
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY);
+ /* Unconditionally clear the EC recovery request. */
+ return google_chromeec_clear_events_b(kb_rec_mask);
+#else
+ return 0;
+#endif
+}
+
+int get_write_protect_state(void)
+{
+ /*
+ * The vboot loader queries this function in romstage. The GPIOs have
+ * not been set up yet as that configuration is done in ramstage. The
+ * hardware defaults to an input but there is a 20K pulldown. Externally
+ * there is a 10K pullup. Disable the internal pull in romstage so that
+ * there isn't any ambiguity in the reading.
+ */
+#if defined(__PRE_RAM__)
+ ssus_disable_internal_pull(WP_STATUS_PAD);
+#endif
+
+ /* WP is enabled when the pin is reading high. */
+ return ssus_get_gpio(WP_STATUS_PAD);
+}
diff --git a/src/mainboard/google/gnawty/cmos.layout b/src/mainboard/google/gnawty/cmos.layout
new file mode 100644
index 0000000..49fb262
--- /dev/null
+++ b/src/mainboard/google/gnawty/cmos.layout
@@ -0,0 +1,137 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416 128 r 0 vbnv
+#544 440 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/google/gnawty/devicetree.cb b/src/mainboard/google/gnawty/devicetree.cb
new file mode 100644
index 0000000..bb6fcad
--- /dev/null
+++ b/src/mainboard/google/gnawty/devicetree.cb
@@ -0,0 +1,101 @@
+chip soc/intel/baytrail
+
+ # SATA port enable mask (2 ports)
+ register "sata_port_map" = "0x1"
+ register "sata_ahci" = "0x1"
+ register "ide_legacy_combined" = "0x0"
+
+ # Route USB ports to XHCI
+ register "usb_route_to_xhci" = "1"
+
+ # USB Port Disable Mask
+ register "usb2_port_disable_mask" = "0x0"
+ register "usb3_port_disable_mask" = "0x0"
+
+ # USB PHY settings
+ # TODO: These values are from Baytrail and need tuned for Gnawty board
+ register "usb2_per_port_lane0" = "0x00049a09"
+ register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+ register "usb2_per_port_lane1" = "0x00049a09"
+ register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+ register "usb2_per_port_lane2" = "0x00049209"
+ register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+ register "usb2_per_port_lane3" = "0x00049a09"
+ register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
+ # LPE audio codec settings
+ register "lpe_codec_clk_freq" = "25" # 25MHz clock
+ register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
+
+ # SD Card controller
+ register "sdcard_cap_low" = "0x036864b2"
+ register "sdcard_cap_high" = "0x0"
+
+ # Enable devices in ACPI mode
+ register "lpe_acpi_mode" = "1"
+ register "lpss_acpi_mode" = "1"
+ register "scc_acpi_mode" = "1"
+
+ # Allow PCIe devices to wake system from suspend
+ register "pcie_wake_enable" = "1"
+
+ # Enable PIPEA as DP_C
+ register "gpu_pipea_port_select" = "2" # DP_C
+ register "gpu_pipea_power_cycle_delay" = "6" # 600ms
+ register "gpu_pipea_power_on_delay" = "5000" # 500ms
+ register "gpu_pipea_light_on_delay" = "70" # 7ms
+ register "gpu_pipea_power_off_delay" = "500" # 50ms
+ register "gpu_pipea_light_off_delay" = "2000" # 200ms
+
+ # VR PS2 control
+ register "vnn_ps2_enable" = "1"
+ register "vcc_ps2_enable" = "1"
+
+ # Disable SLP_X stretching after SUS power well fail.
+ register "disable_slp_x_stretch_sus_fail" = "1"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # SoC router
+ device pci 02.0 on end # GFX
+ device pci 11.0 off end # SDIO
+ device pci 12.0 on end # SD
+ device pci 13.0 on end # SATA
+ device pci 14.0 on end # XHCI
+ device pci 15.0 on end # LPE
+ device pci 17.0 on end # MMC
+ device pci 18.0 on end # SIO_DMA1
+ device pci 18.1 on end # I2C1
+ device pci 18.2 on end # I2C2
+ device pci 18.3 off end # I2C3
+ device pci 18.4 off end # I2C4
+ device pci 18.5 on end # I2C5
+ device pci 18.6 on end # I2C6
+ device pci 18.7 off end # I2C7
+ device pci 1a.0 on end # TXE
+ device pci 1b.0 on end # HDA
+ device pci 1c.0 on end # PCIE_PORT1
+ device pci 1c.1 on end # PCIE_PORT2
+ device pci 1c.2 off end # PCIE_PORT3
+ device pci 1c.3 off end # PCIE_PORT4
+ device pci 1d.0 on end # EHCI
+ device pci 1e.0 on end # SIO_DMA2
+ device pci 1e.1 off end # PWM1
+ device pci 1e.2 off end # PWM2
+ device pci 1e.3 off end # HSUART1
+ device pci 1e.4 off end # HSUART2
+ device pci 1e.5 off end # SPI
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ # We only have one init function that
+ # we need to call to initialize the
+ # keyboard part of the EC.
+ device pnp ff.1 on # dummy address
+ end
+ end
+ end # LPC Bridge
+ device pci 1f.3 off end # SMBus
+ end
+end
diff --git a/src/mainboard/google/gnawty/dsdt.asl b/src/mainboard/google/gnawty/dsdt.asl
new file mode 100644
index 0000000..6475e1c
--- /dev/null
+++ b/src/mainboard/google/gnawty/dsdt.asl
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define ENABLE_TPM
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x05, // DSDT revision: ACPI v5.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include <soc/intel/baytrail/acpi/platform.asl>
+
+ // global NVS and variables
+ #include <soc/intel/baytrail/acpi/globalnvs.asl>
+
+ #include <soc/intel/baytrail/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ //#include <soc/intel/baytrail/acpi/northcluster.asl>
+ #include <soc/intel/baytrail/acpi/southcluster.asl>
+ }
+
+ /* Dynamic Platform Thermal Framework */
+ #include "acpi/dptf.asl"
+ }
+
+ #include "acpi/chromeos.asl"
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ /* Chipset specific sleep states */
+ #include <soc/intel/baytrail/acpi/sleepstates.asl>
+
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/google/gnawty/ec.c b/src/mainboard/google/gnawty/ec.c
new file mode 100644
index 0000000..27fcb0f
--- /dev/null
+++ b/src/mainboard/google/gnawty/ec.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <types.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include "ec.h"
+
+void mainboard_ec_init(void)
+{
+ printk(BIOS_DEBUG, "mainboard_ec_init\n");
+ post_code(0xf0);
+
+ /* Restore SCI event mask on resume. */
+ if (acpi_is_wakeup_s3()) {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S3_WAKE_EVENTS);
+
+ /* Disable SMI and wake events */
+ google_chromeec_set_smi_mask(0);
+
+ /* Clear pending events */
+ while (google_chromeec_get_event() != 0);
+ google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+ } else {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S5_WAKE_EVENTS);
+ google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
+ }
+
+ /* Clear wake events, these are enabled on entry to sleep */
+ google_chromeec_set_wake_mask(0);
+
+ post_code(0xf1);
+}
diff --git a/src/mainboard/google/gnawty/ec.h b/src/mainboard/google/gnawty/ec.h
new file mode 100644
index 0000000..159351b
--- /dev/null
+++ b/src/mainboard/google/gnawty/ec.h
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <ec/google/chromeec/ec_commands.h>
+
+/* GPIO_S0_000 is EC_SCI#, but it is bit 24 in GPE_STS */
+#define EC_SCI_GPI 24
+/* GPIO_S5_07 is EC_SMI#, but it is bit 23 in GPE_STS and ALT_GPIO_SMI. */
+#define EC_SMI_GPI 23
+
+#define MAINBOARD_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid or power button or key press */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+ (MAINBOARD_EC_S5_WAKE_EVENTS |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
+
+#ifndef __ACPI__
+extern void mainboard_ec_init(void);
+#endif
+
+#endif
diff --git a/src/mainboard/google/gnawty/fadt.c b/src/mainboard/google/gnawty/fadt.c
new file mode 100644
index 0000000..2434d1a
--- /dev/null
+++ b/src/mainboard/google/gnawty/fadt.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <soc/acpi.h>
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_MOBILE;
+
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ acpi_fill_in_fadt(fadt);
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/google/gnawty/gpio.c b/src/mainboard/google/gnawty/gpio.c
new file mode 100644
index 0000000..89930f2
--- /dev/null
+++ b/src/mainboard/google/gnawty/gpio.c
@@ -0,0 +1,230 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdlib.h>
+#include <soc/gpio.h>
+#include "irqroute.h"
+
+/* TODO(SHAWNN): Modify gpios labeled 'INT' for interrupt handling */
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+ GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */
+ GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */
+ GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */
+ GPIO_NC, /* S0_NC03 - NC */
+ GPIO_NC, /* S0_NC04 - NC */
+ GPIO_NC, /* S0_NC05 - NC */
+ GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */
+ GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */
+ GPIO_NC, /* S0_NC08 - NC */
+ GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */
+ GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */
+ GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */
+ GPIO_NC, /* S0_NC12 - NC */
+ GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */
+ GPIO_NC, /* S0_NC14 - NC */
+ GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */
+ GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */
+ GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */
+ GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */
+ GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */
+ GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */
+ GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */
+ GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */
+ GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */
+ GPIO_NC, /* S0_NC24 - NC */
+ GPIO_NC, /* S0_NC25 - NC */
+ GPIO_NC, /* S0_NC26 - NC */
+ GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+ GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */
+ GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */
+ GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */
+ GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */
+ GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */
+ GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */
+ GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */
+ GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */
+ GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */
+ GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */
+ GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */
+ GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */
+ GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */
+ GPIO_NC, /* S0-SC013 - NC */
+ GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */
+ GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */
+ GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */
+ GPIO_NC, /* S0-SC027 - NC */
+ GPIO_NC, /* S0-SC028 - NC */
+ GPIO_NC, /* S0-SC029 - NC */
+ GPIO_NC, /* S0-SC030 - NC */
+ GPIO_NC, /* S0-SC031 - NC */
+ GPIO_NC, /* S0-SC032 - NC */
+ GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */
+ GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */
+ GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */
+ GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */
+ GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */
+ GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */
+ GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */
+ GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */
+ GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */
+ GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */
+ GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */
+ GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */
+ GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */
+ GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */
+ GPIO_DEFAULT, /* S0-SC054 - NC */
+ GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */
+ GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */
+ GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */
+ GPIO_INPUT, /* S0-SC058 - SIM_DET_C */
+ GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */
+ GPIO_NC, /* S0-SC060 - NC */
+ GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */
+ GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */
+ GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */
+ GPIO_FUNC1, /* S0-SC064 - I2S_DIN */
+ GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */
+ GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */
+ GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */
+ GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */
+ GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */
+ GPIO_NC, /* S0-SC070 - ALS_INT_L - INT(NC) */
+ GPIO_NC, /* S0-SC071 - NC */
+ GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */
+ GPIO_NC, /* S0-SC073 - NC */
+ GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */
+ GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */
+ GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */
+ GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */
+ GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */
+ GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */
+ GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */
+ GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */
+ GPIO_NC, /* S0-SC082 - NC */
+ GPIO_NC, /* S0-SC083 - NC */
+ GPIO_NC, /* S0-SC084 - NC */
+ GPIO_NC, /* S0-SC085 - NC */
+ GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */
+ GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */
+ GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */
+ GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */
+ GPIO_NC, /* S0-SC090 - NC */
+ GPIO_NC, /* S0-SC091 - NC */
+ GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */
+ GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */
+ GPIO_NC, /* S0-SC094 - NC */
+ GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */
+ GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */
+ GPIO_NC, /* S0-SC097 - NC */
+ GPIO_NC, /* S0-SC098 - NC */
+ GPIO_NC, /* S0-SC099 - NC */
+ GPIO_NC, /* S0-SC100 - NC */
+ GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */
+ GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+ GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */
+ GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */
+ GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */
+ GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */
+ GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */
+ GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */
+ GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */
+ GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */
+ GPIO_NC, /* S508 - NC */
+ GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */
+ GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */
+ GPIO_FUNC0, /* S511 - SUSPWRDNACK */
+ GPIO_FUNC0, /* S512 - WIFI_SUSCLK */
+ GPIO_FUNC0, /* S513 - SLP_SX */
+ GPIO_NC, /* S514 - NC */
+ GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */
+ GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */
+ GPIO_NC, /* S517 - NC */
+ GPIO_FUNC0, /* S518 - SUS_STAT# */
+ GPIO_FUNC0, /* S519 - USB_OC0# */
+ GPIO_FUNC0, /* S520 - USB_OC1# */
+ GPIO_NC, /* S521 - NC */
+ GPIO_NC, /* S522 - XDP_GPIO_DFX0 */
+ GPIO_NC, /* S523 - XDP_GPIO_DFX1 */
+ GPIO_NC, /* S524 - XDP_GPIO_DFX2 */
+ GPIO_NC, /* S525 - XDP_GPIO_DFX3 */
+ GPIO_NC, /* S526 - XDP_GPIO_DFX4 */
+ GPIO_NC, /* S527 - XDP_GPIO_DFX5 */
+ GPIO_NC, /* S528 - XDP_GPIO_DFX6 */
+ GPIO_NC, /* S529 - XDP_GPIO_DFX7 */
+ GPIO_NC, /* S530 - XDP_GPIO_DFX8 */
+ GPIO_NC, /* S531 - NC */
+ GPIO_NC, /* S532 - NC */
+ GPIO_NC, /* S533 - NC */
+ GPIO_NC, /* S534 - NC */
+ GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */
+ GPIO_NC, /* S536 - NC */
+ GPIO_INPUT, /* S537 - RAM_ID0 */
+ GPIO_INPUT, /* S538 - RAM_ID1 */
+ GPIO_INPUT, /* S539 - RAM_ID2 */
+ GPIO_NC, /* S540 - NC */
+ GPIO_NC, /* S541 - NC */
+ GPIO_NC, /* S542 - NC */
+ GPIO_NC, /* S543 - NC */
+ GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+ [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO,
+ [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO,
+ [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
+};
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+ [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
+};
+
+static struct soc_gpio_config gpio_config = {
+ .ncore = gpncore_gpio_map,
+ .score = gpscore_gpio_map,
+ .ssus = gpssus_gpio_map,
+ .core_dirq = &core_dedicated_irq,
+ .sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+ return &gpio_config;
+}
diff --git a/src/mainboard/google/gnawty/irqroute.c b/src/mainboard/google/gnawty/irqroute.c
new file mode 100644
index 0000000..db8c512
--- /dev/null
+++ b/src/mainboard/google/gnawty/irqroute.c
@@ -0,0 +1,18 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "irqroute.h"
+
+DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/google/gnawty/irqroute.h b/src/mainboard/google/gnawty/irqroute.h
new file mode 100644
index 0000000..abec081
--- /dev/null
+++ b/src/mainboard/google/gnawty/irqroute.h
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/irq.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \
+ PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \
+ PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \
+ PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
+
+#define PIRQ_PIC_ROUTES \
+ PIRQ_PIC(A, DISABLE), \
+ PIRQ_PIC(B, DISABLE), \
+ PIRQ_PIC(C, DISABLE), \
+ PIRQ_PIC(D, DISABLE), \
+ PIRQ_PIC(E, DISABLE), \
+ PIRQ_PIC(F, DISABLE), \
+ PIRQ_PIC(G, DISABLE), \
+ PIRQ_PIC(H, DISABLE)
+
+/* CORE bank DIRQs - up to 16 supported */
+#define TPAD_IRQ_OFFSET 0
+#define TOUCH_IRQ_OFFSET 1
+#define I8042_IRQ_OFFSET 2
+/* Corresponding SCORE GPIO pins */
+#define TPAD_IRQ_GPIO 55
+#define TOUCH_IRQ_GPIO 72
+#define I8042_IRQ_GPIO 101
+
+/* SUS bank DIRQs - up to 16 supported */
+#define CODEC_IRQ_OFFSET 0
+/* Corresponding SUS GPIO pins */
+#define CODEC_IRQ_GPIO 9
diff --git a/src/mainboard/google/gnawty/mainboard.c b/src/mainboard/google/gnawty/mainboard.c
new file mode 100644
index 0000000..29cebb1
--- /dev/null
+++ b/src/mainboard/google/gnawty/mainboard.c
@@ -0,0 +1,181 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if CONFIG_VGA_ROM_RUN
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+#include <smbios.h>
+#include "ec.h"
+#include "onboard.h"
+#include <soc/gpio.h>
+#include <bootstate.h>
+
+void mainboard_suspend_resume(void)
+{
+}
+
+#if CONFIG_VGA_ROM_RUN
+static int int15_handler(void)
+{
+ int res = 1;
+
+ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+ __func__, X86_AX, X86_BX, X86_CX, X86_DX);
+
+ switch (X86_AX) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video bios default
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0001;
+ res = 1;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV
+ * bit 2 = EFP (HDMI)
+ * bit 3 = LFP (eDP)*
+ * bit 4 = CRT2
+ * bit 5 = TV2
+ * bit 6 = EFP2
+ * bit 7 = LFP2
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0008;
+ res = 1;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0003;
+ res = 1;
+ break;
+ case 0x5f70:
+ switch ((X86_CX >> 8) & 0xff) {
+ case 0:
+ /* Get Mux */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 1:
+ /* Set Mux */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG,
+ "Unknown INT15 5f70 function: 0x%02x\n",
+ ((X86_CX >> 8) & 0xff));
+ break;
+ }
+ break;
+
+ default:
+ printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX);
+ break;
+ }
+ return res;
+}
+#endif
+
+static void mainboard_init(device_t dev)
+{
+ mainboard_ec_init();
+}
+
+static int mainboard_smbios_data(device_t dev, int *handle,
+ unsigned long *current)
+{
+ int len = 0;
+
+ len += smbios_write_type41(
+ current, handle,
+ BOARD_TRACKPAD_NAME, /* name */
+ BOARD_TRACKPAD_IRQ, /* instance */
+ BOARD_TRACKPAD_I2C_BUS, /* segment */
+ BOARD_TRACKPAD_I2C_ADDR, /* bus */
+ 0, /* device */
+ 0); /* function */
+
+ len += smbios_write_type41(
+ current, handle,
+ BOARD_TOUCHSCREEN_NAME, /* name */
+ BOARD_TOUCHSCREEN_IRQ, /* instance */
+ BOARD_TOUCHSCREEN_I2C_BUS, /* segment */
+ BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */
+ 0, /* device */
+ 0); /* function */
+
+ return len;
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+ dev->ops->get_smbios_data = mainboard_smbios_data;
+#if CONFIG_VGA_ROM_RUN
+ /* Install custom int15 handler for VGA OPROM */
+ mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
+
+static void edp_vdden_cb(void *unused)
+{
+ ncore_select_func(SOC_DDI1_VDDEN_PAD, PAD_FUNC2);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, edp_vdden_cb, NULL);
diff --git a/src/mainboard/google/gnawty/mainboard_smi.c b/src/mainboard/google/gnawty/mainboard_smi.c
new file mode 100644
index 0000000..a3d5273
--- /dev/null
+++ b/src/mainboard/google/gnawty/mainboard_smi.c
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <elog.h>
+
+#include <ec/google/chromeec/ec.h>
+#include "ec.h"
+
+#include <soc/nvs.h>
+#include <soc/pmc.h>
+
+/* The wake gpio is SUS_GPIO[0]. */
+#define WAKE_GPIO_EN SUS_GPIO_EN0
+
+static uint8_t mainboard_smi_ec(void)
+{
+ uint8_t cmd = google_chromeec_get_event();
+ uint16_t pmbase = get_pmbase();
+ uint32_t pm1_cnt;
+
+#if CONFIG_ELOG_GSMI
+ /* Log this event */
+ if (cmd)
+ elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
+#endif
+
+ switch (cmd) {
+ case EC_HOST_EVENT_LID_CLOSED:
+ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
+
+ /* Go to S5 */
+ pm1_cnt = inl(pmbase + PM1_CNT);
+ pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT);
+ outl(pm1_cnt, pmbase + PM1_CNT);
+ break;
+ }
+
+ return cmd;
+}
+
+/* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that
+ * this includes the enable bits in the lower 16 bits. */
+void mainboard_smi_gpi(uint32_t alt_gpio_smi)
+{
+ if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
+ /* Process all pending events */
+ while (mainboard_smi_ec() != 0);
+ }
+}
+
+void mainboard_smi_sleep(uint8_t slp_typ)
+{
+ /* Disable USB charging if required */
+ switch (slp_typ) {
+ case 3:
+ if (smm_get_gnvs()->s3u0 == 0)
+ google_chromeec_set_usb_charge_mode(
+ 0, USB_CHARGE_MODE_DISABLED);
+ if (smm_get_gnvs()->s3u1 == 0)
+ google_chromeec_set_usb_charge_mode(
+ 1, USB_CHARGE_MODE_DISABLED);
+
+ /* Enable wake events */
+ google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
+ /* Enable wake pin in GPE block. */
+ enable_gpe(WAKE_GPIO_EN);
+ break;
+ case 5:
+ if (smm_get_gnvs()->s5u0 == 0)
+ google_chromeec_set_usb_charge_mode(
+ 0, USB_CHARGE_MODE_DISABLED);
+ if (smm_get_gnvs()->s5u1 == 0)
+ google_chromeec_set_usb_charge_mode(
+ 1, USB_CHARGE_MODE_DISABLED);
+
+ /* Enable wake events */
+ google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
+ break;
+ }
+
+ /* Disable SCI and SMI events */
+ google_chromeec_set_smi_mask(0);
+ google_chromeec_set_sci_mask(0);
+
+ /* Clear pending events that may trigger immediate wake */
+ while (google_chromeec_get_event() != 0);
+}
+
+int mainboard_smi_apmc(uint8_t apmc)
+{
+ switch (apmc) {
+ case APM_CNT_ACPI_ENABLE:
+ google_chromeec_set_smi_mask(0);
+ /* Clear all pending events */
+ while (google_chromeec_get_event() != 0);
+ google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ google_chromeec_set_sci_mask(0);
+ /* Clear all pending events */
+ while (google_chromeec_get_event() != 0);
+ google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/google/gnawty/onboard.h b/src/mainboard/google/gnawty/onboard.h
new file mode 100644
index 0000000..708b1f6
--- /dev/null
+++ b/src/mainboard/google/gnawty/onboard.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include "irqroute.h"
+
+/* PCH wake signal from EC. */
+#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0)
+
+#define BOARD_TRACKPAD_NAME "trackpad"
+#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET)
+#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1)
+#define BOARD_TRACKPAD_I2C_BUS 0
+#define BOARD_TRACKPAD_I2C_ADDR 0x4b
+
+#define BOARD_TOUCHSCREEN_NAME "touchscreen"
+#define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET)
+#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2)
+#define BOARD_TOUCHSCREEN_I2C_BUS 5
+#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */
+
+#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
+#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
+
+#endif
diff --git a/src/mainboard/google/gnawty/romstage.c b/src/mainboard/google/gnawty/romstage.c
new file mode 100644
index 0000000..21b20f9
--- /dev/null
+++ b/src/mainboard/google/gnawty/romstage.c
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <soc/gpio.h>
+#include <soc/mrc_wrapper.h>
+#include <soc/romstage.h>
+
+/*
+ * RAM_ID[2:0] are on GPIO_SSUS[39:37]
+ * 0b000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
+ * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
+ * 0b011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63MFR-PBA 1600MHz
+ * 0b100 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz
+ * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
+ * 0b110 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz
+ * 0b111 - 4GiB total - 2 x 2GiB Hynix H5TC4G63MFR-PBA 1600MHz
+*/
+static const uint32_t dual_channel_config =
+ (1 << 0) | (1 << 1) | (1 << 2) | (1 << 6) | (1 << 7) ;
+
+#define SPD_SIZE 256
+#define GPIO_SSUS_37_PAD 57
+#define GPIO_SSUS_38_PAD 50
+#define GPIO_SSUS_39_PAD 58
+
+static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual)
+{
+ int ram_id = 0;
+
+ /* The ram_id[2:0] pullups on gnawty are too large for the default 20K
+ * pulldown on the pad. Therefore, disable the internal pull resistor to
+ * read high values correctly. */
+ ssus_disable_internal_pull(GPIO_SSUS_37_PAD);
+ ssus_disable_internal_pull(GPIO_SSUS_38_PAD);
+ ssus_disable_internal_pull(GPIO_SSUS_39_PAD);
+
+ ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0);
+ ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1);
+ ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2);
+
+ printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds);
+
+ if (ram_id >= total_spds)
+ return NULL;
+
+ /* Single channel configs */
+ if (dual_channel_config & (1 << ram_id))
+ *dual = 1;
+
+ return &spd_file_content[SPD_SIZE * ram_id];
+}
+
+void mainboard_romstage_entry(struct romstage_params *rp)
+{
+ void *spd_content;
+ int dual_channel = 0;
+ void *spd_file;
+ size_t spd_fsize;
+
+ struct mrc_params mp = {
+ .mainboard = {
+ .dram_type = DRAM_DDR3L,
+ .dram_info_location = DRAM_INFO_SPD_MEM,
+ .weaker_odt_settings = 1,
+ },
+ };
+
+ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
+ &spd_fsize);
+ if (!spd_file)
+ die("SPD data not found.");
+
+ spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE,
+ &dual_channel);
+ mp.mainboard.dram_data[0] = spd_content;
+ if (dual_channel)
+ mp.mainboard.dram_data[1] = spd_content;
+
+ rp->mrc_params = ∓
+ romstage_common(rp);
+}
diff --git a/src/mainboard/google/gnawty/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex b/src/mainboard/google/gnawty/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
new file mode 100644
index 0000000..8ced790
--- /dev/null
+++ b/src/mainboard/google/gnawty/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
@@ -0,0 +1,17 @@
+# Hynix HMT425S6CFR6A-PBA
+92 13 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 01 00 00 00 00 00 00 C9 C0
+48 4D 54 34 32 35 53 36 43 46 52 36 41 2D 50 42
+20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/gnawty/spd/Makefile.inc b/src/mainboard/google/gnawty/spd/Makefile.inc
new file mode 100644
index 0000000..7514279
--- /dev/null
+++ b/src/mainboard/google/gnawty/spd/Makefile.inc
@@ -0,0 +1,49 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+# Order matters for SPD sources. The following indicies
+# define the SPD data to use.
+# 0b000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
+# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
+# 0b011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63MFR-PBA 1600MHz
+# 0b100 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz
+# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
+# 0b110 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz
+# 0b111 - 4GiB total - 2 x 2GiB Hynix H5TC4G63MFR-PBA 1600MHz
+SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63MFR-PBA
+SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63MFR-PBA
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/gnawty/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex b/src/mainboard/google/gnawty/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex
new file mode 100644
index 0000000..4bd8e0e
--- /dev/null
+++ b/src/mainboard/google/gnawty/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex
@@ -0,0 +1,32 @@
+92 12 0b 03 03 11 02 02
+03 52 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 81
+00 05 3c 3c 01 40 83 01
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 11 22 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 ad 01
+00 00 00 00 00 00 41 5f
+48 4d 54 33 31 32 53 36
+44 46 52 36 41 2d 50 42
+20 20 4e 30 80 ad 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/gnawty/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/google/gnawty/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
new file mode 100644
index 0000000..ff4fd29
--- /dev/null
+++ b/src/mainboard/google/gnawty/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
@@ -0,0 +1,32 @@
+92 12 0b 03 04 19 02 02
+03 52 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 81
+20 08 3c 3c 01 40 83 01
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 11 62 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 ad 01
+00 00 00 00 00 00 ff ab
+48 4d 54 34 32 35 53 36
+41 46 52 36 41 2d 50 42
+20 20 4e 30 80 ad 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/gnawty/spd/hynix_2GiB_dimm_H5TC4G63MFR-PBA.spd.hex b/src/mainboard/google/gnawty/spd/hynix_2GiB_dimm_H5TC4G63MFR-PBA.spd.hex
new file mode 100644
index 0000000..0e8c1bd
--- /dev/null
+++ b/src/mainboard/google/gnawty/spd/hynix_2GiB_dimm_H5TC4G63MFR-PBA.spd.hex
@@ -0,0 +1,16 @@
+92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 11 22 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 01 00 00 00 00 00 00 96 77
+48 4D 54 34 32 35 53 36 4D 46 52 36 41 2D 50 42
+20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/gnawty/spd/kingston_2GiB_dimm_D2516EC4BXGGB.spd.hex b/src/mainboard/google/gnawty/spd/kingston_2GiB_dimm_D2516EC4BXGGB.spd.hex
new file mode 100644
index 0000000..3097589
--- /dev/null
+++ b/src/mainboard/google/gnawty/spd/kingston_2GiB_dimm_D2516EC4BXGGB.spd.hex
@@ -0,0 +1,16 @@
+92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 81
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 62 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 01 98 00 00 00 00 00 00 00 FE CE
+44 32 35 31 36 45 43 34 42 58 47 47 42 20 20 20
+20 20 00 00 01 98 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/gnawty/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex b/src/mainboard/google/gnawty/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex
new file mode 100644
index 0000000..f99c92a
--- /dev/null
+++ b/src/mainboard/google/gnawty/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex
@@ -0,0 +1,32 @@
+92 11 0b 03 03 11 02 02
+03 11 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 86
+50 00 3c 3c 01 40 83 05
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 01 02 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2c 00
+00 00 00 00 00 00 6a 15
+34 4b 54 46 32 35 36 36
+34 48 5a 2d 31 47 36 45
+31 20 45 31 80 2c 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/gnawty/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex b/src/mainboard/google/gnawty/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex
new file mode 100644
index 0000000..f3bcb56
--- /dev/null
+++ b/src/mainboard/google/gnawty/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex
@@ -0,0 +1,32 @@
+92 11 0b 03 04 19 02 02
+03 11 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 86
+20 08 3c 3c 01 40 83 05
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 01 02 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2c 00
+00 00 00 00 00 00 19 d2
+34 4b 54 46 32 35 36 36
+34 48 5a 2d 31 47 36 45
+31 20 45 31 80 2c 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/gnawty/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex b/src/mainboard/google/gnawty/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex
new file mode 100644
index 0000000..ac9a0e0
--- /dev/null
+++ b/src/mainboard/google/gnawty/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex
@@ -0,0 +1,17 @@
+# Samsung K4B4G1646Q-HYK0
+92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
+00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01 00 00 00 00 00 00 6C F9
+4D 34 37 31 42 35 36 37 34 51 48 30 2D 59 4B 30
+20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/gnawty/w25q64.c b/src/mainboard/google/gnawty/w25q64.c
new file mode 100644
index 0000000..a9ed8ac
--- /dev/null
+++ b/src/mainboard/google/gnawty/w25q64.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <soc/spi.h>
+
+/*
+ * SPI lockdown configuration W25Q64FW.
+ */
+#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
+#define SPI_OPTYPE_0 0x01 /* Write, no address */
+
+#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
+#define SPI_OPTYPE_1 0x03 /* Write, address required */
+
+#define SPI_OPMENU_2 0x03 /* READ: Read Data */
+#define SPI_OPTYPE_2 0x02 /* Read, address required */
+
+#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
+#define SPI_OPTYPE_3 0x00 /* Read, no address */
+
+#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
+#define SPI_OPTYPE_4 0x03 /* Write, address required */
+
+#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
+#define SPI_OPTYPE_5 0x00 /* Read, no address */
+
+#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
+#define SPI_OPTYPE_6 0x03 /* Write, address required */
+
+#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
+#define SPI_OPTYPE_7 0x02 /* Read, address required */
+
+#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
+#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
+ (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
+ (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
+ (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0))
+#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
+ (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0))
+#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
+ (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0))
+#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB)
+
+static const struct spi_config spi_config = {
+ .preop = SPI_OPPREFIX,
+ .optype = SPI_OPTYPE,
+ .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER },
+ .lvscc = SPI_VSCC,
+ .uvscc = SPI_VSCC,
+};
+
+int mainboard_get_spi_config(struct spi_config *cfg)
+{
+ memcpy(cfg, &spi_config, sizeof(*cfg));
+
+ return 0;
+}
1
0
20 Nov '15
the following patch was just integrated into master:
commit 8b4f98a41f0ef053c623b8e4c111080755a38044
Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com>
Date: Tue Sep 29 11:12:03 2015 +0800
AMD Bettong: add README
This is the initial version of README.
AMD provides stable Bettong code in github. Add the link and bug fixed
list to README.
Change-Id: Ie8b761096fd1850afb9363ebb761aa4992b47643
Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com>
Reviewed-on: http://review.coreboot.org/11737
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc(a)marcjonesconsulting.com>
See http://review.coreboot.org/11737 for details.
-gerrit
1
0
Patch merged into coreboot/master: AMD Bettong: refactor PCI interrupt table
by gerrit＠coreboot.org 20 Nov '15
by gerrit＠coreboot.org 20 Nov '15
20 Nov '15
the following patch was just integrated into master:
commit 839d68f1019f9d1a0e57b1429bf1be4685d5e095
Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com>
Date: Tue Aug 18 06:22:22 2015 +0800
AMD Bettong: refactor PCI interrupt table
1. Use write_pci_int_table to write registers 0xC00/0xC01.
2. Add GPIO, I2C and UART interrupt according
"BKDG for AMD Family 15h Models 60h-6Fh Processors",
50742 Rev 3.01 - July 17, 2015
3. The interrupt valudes are moved from bettong/mptable.c.
All devices work in Windows 10.
Change-Id: Iad13bc02c84a5dfc7c24356436ac560f593304d7
Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com>
Reviewed-on: http://review.coreboot.org/11746
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
Reviewed-by: Marc Jones <marc(a)marcjonesconsulting.com>
See http://review.coreboot.org/11746 for details.
-gerrit
1
0