coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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1544 discussions

Patch merged into coreboot/master: lib/timestamp.c: only log "Timestamp table full" once
by gerrit＠coreboot.org 24 Nov '15

24 Nov '15

the following patch was just integrated into master: commit f5fd4c99d5b05fd9677cf81124d5ad5ef2270011 Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Fri Nov 20 13:25:25 2015 -0600 lib/timestamp.c: only log "Timestamp table full" once If the timestamp table gets corrupted (separate issue), the timestamp_sync_cache_to_cbmem() function may add a large number of bogus timestamp entries. This causes a flood of "ERROR: Timestamp table full". With logs going to a serial console, this renders the system essentially unbootable. There really isn't a need to log that more than once, so log it when the last slot in the timestamp table is filled. Change-Id: I05d131183afceca31f4dac91c5edc95cfb1e443f Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> Reviewed-on: http://review.coreboot.org/12506 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/12506 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/braswell: Drop gfx_read_resources()
by gerrit＠coreboot.org 24 Nov '15

24 Nov '15

the following patch was just integrated into master: commit 1ef80141c05bd1a5acb17b3b59567fd2d4dee9f0 Author: Nico Huber <nico.h(a)gmx.de> Date: Thu Nov 5 23:27:06 2015 +0100 soc/intel/braswell: Drop gfx_read_resources() Drop the last remnant of vanished CONFIG_MARK_GRAPHICS_MEM_WRCOMB. Could not build test google/cyan and intel/strago due to lack of UEFI headers, OMG. Change-Id: I0b9eac5c040d24bab2b85e9b63042b6aaa9879d9 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: http://review.coreboot.org/12338 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12338 for details. -gerrit

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Patch merged into coreboot/master: AMD/bettong: Add UART support
by gerrit＠coreboot.org 24 Nov '15

24 Nov '15

the following patch was just integrated into master: commit 22861385613e34a16ef745917f6956a92243d88b Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Sat Nov 21 12:19:22 2015 +0800 AMD/bettong: Add UART support The function delay in uart8250mem.c is not enough for hudson. I guess there are some problems in lapic_timer(). I uploaded a patch to gerrit to show the way to enable UART feature. http://review.coreboot.org/#/c/12343/4 Currently the HUDSON_UART is unchecked by default. Select HUDSON_UART to enable this feature. The UART is test at BIOS stage. Since it is not a standart UART device, the windows internal UART driver doesnt support it. I guess we need a driver to use it on windows. Change-Id: I4cec833cc2ff8069c82886837f7cbd4483ff11bb Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: http://review.coreboot.org/11749 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11749 for details. -gerrit

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Patch set updated for coreboot: baytrail: fix missing brackets around ir_base to fix IRQ routing
by Alexander Couzens 24 Nov '15

24 Nov '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12525 -gerrit commit 943e87a1b9e53a5c45bb39020c39006fa6286f4a Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Tue Nov 24 09:46:18 2015 +0100 baytrail: fix missing brackets around ir_base to fix IRQ routing This missing brackets overwritten other registers including the IO APIC enable bit (AEN in OIC). Bug introduced by bde6d309 (x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer) Change-Id: I1d5aa2af6d74405a1a125af6221ac0e635a6b693 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/soc/intel/baytrail/southcluster.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 49c4545..090b988 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -184,7 +184,7 @@ static void sc_init(device_t dev) { int i; u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08); - u16 *ir_base = (u16 *)ILB_BASE_ADDRESS + 0x20; + u16 *ir_base = (u16 *)(ILB_BASE_ADDRESS + 0x20); u32 *gen_pmcon1 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1); u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); const struct baytrail_irq_route *ir = &global_baytrail_irq_route;

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New patch to review for coreboot: sconfig: pass in devicetree filename
by Martin Roth 24 Nov '15

24 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12529 -gerrit commit 8d3c826f938583ed34f2c5347cc271a696ad31f8 Author: Martin Roth <martinroth(a)google.com> Date: Tue Nov 24 12:34:16 2015 -0700 sconfig: pass in devicetree filename Instead of forcing the hardcoded 'devicetree.cb' filename under the mainboard directory, this allows mainboards to select a filename for the devicetree file. This allows mainboard variants that need to use different devicetree files to live in the same directory. Change-Id: I761e676ba5d5f70d1fb86656b528f63db169fcef Signed-off-by: Martin Roth <martinroth(a)google.com> --- Makefile.inc | 4 ++-- src/Kconfig | 8 ++++++++ util/sconfig/main.c | 32 +++++++++++++++++++++----------- 3 files changed, 31 insertions(+), 13 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 53b658b..4e9f9a9 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -369,10 +369,10 @@ $(BIMGTOOL): $(top)/util/bimgtool/bimgtool.c ####################################################################### # needed objects that every mainboard uses # Creation of these is architecture and mainboard independent -$(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb $(objutil)/sconfig/sconfig +$(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/$(call strip_quotes, $(CONFIG_DEVICETREE)) $(objutil)/sconfig/sconfig @printf " SCONFIG $(subst $(src)/,,$(<))\n" mkdir -p $(obj)/mainboard/$(MAINBOARDDIR) - $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR) + $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR) $(call strip_quotes, $(CONFIG_DEVICETREE)) ramstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c romstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c diff --git a/src/Kconfig b/src/Kconfig index 8439a00..471d305 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -323,6 +323,14 @@ config BOARD_ID_STRING This string is placed in the 'board_id' CBFS file for indicating board type. +config DEVICETREE + string + default "devicetree.cb" + help + This symbol is for mainboards to select a different file name for + their devicetree.cb file. This allows board variants that need + different devicetree files to be in the same directory. + config RAM_CODE_SUPPORT bool default n diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 27027f5..afed63c 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -547,7 +547,7 @@ static void inherit_subsystem_ids(FILE *file, struct device *dev) static void usage(void) { - printf("usage: sconfig vendor/mainboard outputdir [-{s|b|k} outputfile]\n"); + printf("usage: sconfig vendor/mainboard outputdir devicefile [-{s|b|k} outputfile]\n"); printf("\t-s file\tcreate ramstage static device map\n"); printf("\t-b file\tcreate bootblock init_mainboard()\n"); printf("\t-k file\tcreate Kconfig devicetree section\n"); @@ -555,27 +555,37 @@ static void usage(void) exit (1); } +#define VENDOR_MAINBOARD_ARG 1 +#define OUTPUTDIR_ARG 2 +#define DEVICEFILE_ARG 3 +#define OUTPUTTYPE_ARG 4 +#define OUTPUTFILE_ARG 5 + +#define MIN_ARGS 4 +#define MAX_ARGS 6 int main(int argc, char** argv) { - if (argc != 3 && argc != 5) + if (argc != MIN_ARGS && argc != MAX_ARGS) usage(); - char *mainboard=argv[1]; - char *outputdir=argv[2]; - char *devtree=malloc(strlen(mainboard)+30); - sprintf(devtree, "src/mainboard/%s/devicetree.cb", mainboard); + char *mainboard=argv[VENDOR_MAINBOARD_ARG]; + char *outputdir=argv[OUTPUTDIR_ARG]; + char *devfile=argv[DEVICEFILE_ARG]; + char *devtree=malloc(strlen(mainboard)+strlen(devfile)+30); + sprintf(devtree, "src/mainboard/%s/%s", mainboard, devfile); char *outputc; - if (argc == 3) { + if (argc == MIN_ARGS) { scan_mode = STATIC_MODE; outputc=malloc(strlen(outputdir)+20); sprintf(outputc, "%s/static.c", outputdir); - } else if (argc == 5) { - if ((argv[3][0] != '-') || (argv[3][2] == 0)) { + } else if (argc == MAX_ARGS) { + if ((argv[OUTPUTTYPE_ARG][0] != '-') || + (argv[OUTPUTTYPE_ARG][2] == 0)) { usage(); } - switch (argv[3][1]) { + switch (argv[OUTPUTTYPE_ARG][1]) { case 's': scan_mode = STATIC_MODE; break; @@ -589,7 +599,7 @@ int main(int argc, char** argv) { usage(); break; } - char *outputfile=argv[4]; + char *outputfile=argv[OUTPUTFILE_ARG]; outputc=malloc(strlen(outputdir)+strlen(outputfile)+2); sprintf(outputc, "%s/%s", outputdir, outputfile);

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Patch set updated for coreboot: amd/car: don't apply Fam10h/Fam12h Errata 343 fix to Fam0Fh
by Jonathan A. Kollasch 24 Nov '15

24 Nov '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12528 -gerrit commit f1dc6b99e184fbb97d3c39224d48b90e7c80d312 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Tue Nov 24 10:15:22 2015 -0600 amd/car: don't apply Fam10h/Fam12h Errata 343 fix to Fam0Fh Fixes early fault problem on Fam0Fh introduced in Change I8e01a4ab68b463efe02c27f589e0b4b719532eb5, commit 991f18475c951dcd728eb8550b10dd62938b1770. Change-Id: Id215d2822b78917939c28f7a922a94e02e5d15bf Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/cpu/amd/car/post_cache_as_ram.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 2c11777..b532345 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -79,18 +79,18 @@ static void prepare_ramstage_region(void *resume_backup_memory) print_car_debug(" Done\n"); } -/* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 */ +/* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 + * and RevGuide for Fam12h, Pub#44739 Rev 3.10 + */ static void vErrata343(void) { -#ifdef BU_CFG2_MSR msr_t msr; unsigned int uiMask = 0xFFFFFFF7; msr = rdmsr(BU_CFG2_MSR); msr.hi &= uiMask; // IcDisSpecTlbWr (bit 35) = 0 wrmsr(BU_CFG2_MSR, msr); -#endif } void post_cache_as_ram(void) @@ -121,8 +121,8 @@ void post_cache_as_ram(void) prepare_romstage_ramstack(resume_backup_memory); /* from here don't store more data in CAR */ - if (family < 0x6f) { - /* Family 10h or earlier */ + if (family > 0xf && family < 0x6f) { + /* Family 10h and 12h, maybe others */ vErrata343(); }

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Patch set updated for coreboot: southbridge/amd/sr5650: Add MCFG ACPI table support
by Timothy Pearson 24 Nov '15

24 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12050 -gerrit commit 76ae63becd49b14e07535599885067d35d818bfd Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Aug 14 15:20:42 2015 -0500 southbridge/amd/sr5650: Add MCFG ACPI table support Change-Id: I0c4ba74ddcc727cd92b848d5d3240e6f9f392101 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 22 +++--- src/southbridge/amd/rs780/rs780.c | 11 +++ src/southbridge/amd/rs780/rs780.h | 1 + src/southbridge/amd/sb700/lpc.c | 6 -- src/southbridge/amd/sb800/lpc.c | 7 +- src/southbridge/amd/sr5650/Kconfig | 9 +++ src/southbridge/amd/sr5650/ht.c | 107 ++++++++++++++++++++++++++++- src/southbridge/amd/sr5650/sr5650.c | 18 +++++ 8 files changed, 156 insertions(+), 25 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 600fdf8..60ad8c4 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -740,16 +740,18 @@ static void amdfam10_domain_read_resources(device_t dev) pci_domain_read_resources(dev); -#if CONFIG_MMCONF_SUPPORT - struct resource *res = new_resource(dev, 0xc0010058); - res->base = CONFIG_MMCONF_BASE_ADDRESS; - res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; - res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ - ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); -#endif + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT) && !IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + struct resource *res = new_resource(dev, 0xc0010058); + res->base = CONFIG_MMCONF_BASE_ADDRESS; + res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; + res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + } + + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) { + /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ + ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); + } if (is_fam15h()) { enable_cc6 = 0; diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index c82a629..0d482ae 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -349,6 +349,17 @@ void rs780_enable(device_t dev) } } +#if !IS_ENABLED(CONFIG_AMD_SB_CIMX) +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* FIXME + * Leave table blank until proper contents + * are determined. + */ + return current; +} +#endif + struct chip_operations southbridge_amd_rs780_ops = { CHIP_NAME("ATI RS780") .enable_dev = rs780_enable, diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h index 341de0d..abc601f 100644 --- a/src/southbridge/amd/rs780/rs780.h +++ b/src/southbridge/amd/rs780/rs780.h @@ -17,6 +17,7 @@ #define __RS780_H__ #include <stdint.h> +#include <arch/acpi.h> #include <device/pci_ids.h> #include "chip.h" #include "rev.h" diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index a71fe1f..78933fa 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -30,12 +30,6 @@ #include <cpu/amd/powernow.h> #include "sb700.h" -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - static void lpc_init(device_t dev) { u8 byte; diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 756a0c4..18d4471 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,12 +26,6 @@ #include <arch/acpi.h> #include "sb800.h" -unsigned long acpi_fill_mcfg(unsigned long current) -{ - /* Just a dummy */ - return current; -} - static void lpc_init(device_t dev) { u8 byte; diff --git a/src/southbridge/amd/sr5650/Kconfig b/src/southbridge/amd/sr5650/Kconfig index 29017c6..f2d12ff 100644 --- a/src/southbridge/amd/sr5650/Kconfig +++ b/src/southbridge/amd/sr5650/Kconfig @@ -15,3 +15,12 @@ config SOUTHBRIDGE_AMD_SR5650 bool + +if SOUTHBRIDGE_AMD_SR5650 +config EXT_CONF_SUPPORT + bool "Enable PCI-E MMCONFIG support" + default n + help + Select to enable PCI-E MMCONFIG support on the SR5650. + +endif diff --git a/src/southbridge/amd/sr5650/ht.c b/src/southbridge/amd/sr5650/ht.c index 6119985..e74d36b 100644 --- a/src/southbridge/amd/sr5650/ht.c +++ b/src/southbridge/amd/sr5650/ht.c @@ -20,7 +20,9 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <arch/ioapic.h> +#include <lib.h> #include "sr5650.h" +#include "cmn.h" /* Table 6-6 Recommended Interrupt Routing Configuration */ typedef struct _apic_device_info { @@ -154,11 +156,29 @@ static void pcie_init(struct device *dev) static void sr5690_read_resource(struct device *dev) { + struct resource *res; + + if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + printk(BIOS_DEBUG,"%s: %s\n", __func__, dev_path(dev)); + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); /* Hide BAR3 */ + } + pci_dev_read_resources(dev); /* rpr6.2.(1). Write the Base Address Register (BAR) */ - pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ - pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */ + pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */ + pci_get_resource(dev, 0xfc); /* APIC located in sr5690 */ + + if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + res = new_resource(dev, 0x1c); /* PCIe MCFG space */ + res->base = EXT_CONF_BASE_ADDRESS; + res->size = CONFIG_MMCONF_BUS_NUMBER * 1024 * 1024; /* Each bus needs 1M */ + res->align = log2(res->size); + res->gran = log2(res->size); + res->limit = 0xffffffffffffffffULL; /* 64-bit location allowed */ + res->flags = IORESOURCE_FIXED | IORESOURCE_MEM | IORESOURCE_PCI64 + | IORESOURCE_ASSIGNED | IORESOURCE_RESERVE | IORESOURCE_BRIDGE; + } compact_resources(dev); } @@ -166,7 +186,88 @@ static void sr5690_read_resource(struct device *dev) /* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */ static void sr5690_set_resources(struct device *dev) { - pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ + pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */ + + if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + uint32_t reg; + device_t amd_ht_cfg_dev; + device_t amd_addr_map_dev; + resource_t res_base; + resource_t res_end; + uint32_t base; + uint32_t limit; + struct resource *res; + + printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__); + + res = probe_resource(dev, 0x1c); + if (res) { + /* Find requisite AMD CPU devices */ + amd_ht_cfg_dev = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + amd_addr_map_dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + + if (!amd_ht_cfg_dev || !amd_addr_map_dev) { + printk(BIOS_WARNING, "%s: %s Unable to locate CPU control devices\n", __func__, dev_path(dev)); + } + else { + /* Set up MMCONFIG bus range */ + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 0 << 3); /* Make BAR3 visible */ + set_nbcfg_enable_bits(dev, 0x7c, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register */ + set_nbcfg_enable_bits(dev, 0x84, 7 << 16, 0 << 16); /* Program bus range = 255 busses */ + pci_write_config32(dev, 0x1c, res->base); + + /* Enable MMCONFIG decoding. */ + set_htiu_enable_bits(dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */ + set_nbcfg_enable_bits(dev, 0x7c, 1 << 30, 0 << 30); /* Disable writes to the BAR3 register */ + set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); /* Hide BAR3 */ + + /* Set up nonposted resource in MMIO space */ + res_base = res->base; /* Get the base address */ + res_end = resource_end(res); /* Get the limit (rounded up) */ + printk(BIOS_DEBUG, "%s: %s[0x1c] base = %0llx limit = %0llx\n", __func__, dev_path(dev), res_base, res_end); + + /* Locate an unused MMIO resource */ + for (reg = 0xb8; reg >= 0x80; reg -= 8) { + base = pci_read_config32(amd_addr_map_dev, reg); + limit = pci_read_config32(amd_addr_map_dev, reg + 4); + if (!(base & 0x3)) + break; /* Unused resource found */ + } + + /* If an unused MMIO resource was available, set up the mapping */ + if (!(base & 0x3)) { + uint32_t sblk; + + /* Remember this resource has been stored. */ + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, " <mmconfig>"); + + /* Get SBLink value (HyperTransport I/O Hub Link ID). */ + sblk = (pci_read_config32(amd_ht_cfg_dev, 0x64) >> 8) & 0x3; + + /* Calculate the MMIO mapping base */ + base &= 0x000000f0; + base |= ((res_base >> 8) & 0xffffff00); + base |= 3; + + /* Calculate the MMIO mapping limit */ + limit &= 0x00000048; + limit |= ((res_end >> 8) & 0xffffff00); + limit |= (sblk << 4); + limit |= (1 << 7); + + /* Configure and enable MMIO mapping */ + printk(BIOS_INFO, "%s: %s <- index %x base %04x limit %04x\n", __func__, dev_path(amd_addr_map_dev), reg, base, limit); + pci_write_config32(amd_addr_map_dev, reg + 4, limit); + pci_write_config32(amd_addr_map_dev, reg, base); + } + else { + printk(BIOS_WARNING, "%s: %s No free MMIO resources available\n", __func__, dev_path(dev)); + } + } + } + } + pci_dev_set_resources(dev); } diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 07b4a02..54f0071 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -796,6 +796,24 @@ static void add_ivrs_device_entries(struct device *parent, struct device *dev, i free(root_level); } +unsigned long acpi_fill_mcfg(unsigned long current) +{ + struct resource *res; + resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; + + if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) { + device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + /* Report MMCONF base */ + res = probe_resource(dev, 0x1c); + if (res) + mmconf_base = res->base; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); + } + + return current; +} + static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current) { uint8_t *p;

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Add IOMMU nvram configuration option
by Timothy Pearson 24 Nov '15

24 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12048 -gerrit commit 0cfcb47e2e77cf482bf795cf363ec3327e15e9e5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Aug 11 17:53:45 2015 -0500 mainboard/asus/kgpe-d16: Add IOMMU nvram configuration option Change-Id: I45b04e8fbdfc65603e1057f7b0e5a13d073fe348 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/cmos.default | 3 ++- src/mainboard/asus/kgpe-d16/cmos.layout | 7 ++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index 3319497..b5e9f07 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -3,7 +3,7 @@ debug_level = Spew multi_core = Enable slow_cpu = off compute_unit_siblings = Enable -gart = Disable +iommu = Enable nmi = Disable hypertransport_speed_limit = Auto max_mem_clock = DDR3-1600 @@ -23,6 +23,7 @@ maximum_p_state_limit = 0xf probe_filter = Auto l3_cache_partitioning = Disable ieee1394_controller = Enable +gart = Disable experimental_memory_speed_boost = Disable power_on_after_fail = On boot_option = Fallback diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index a34547a..d1c0702 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -46,9 +46,10 @@ entries 473 2 e 13 dimm_spd_checksum 475 1 e 14 probe_filter 476 1 e 1 l3_cache_partitioning -477 1 e 1 experimental_memory_speed_boost -478 1 r 0 allow_spd_nvram_cache_restore -479 1 e 1 ieee1394_controller +477 1 e 1 ieee1394_controller +478 1 e 1 iommu +479 1 e 1 experimental_memory_speed_boost +480 1 r 0 allow_spd_nvram_cache_restore 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers

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Patch set updated for coreboot: southbridge/amd/sr5650: Use correct PCI configuration block offset
by Timothy Pearson 24 Nov '15

24 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12049 -gerrit commit 13a63340fc69c562d5acfb9b1b128108bb24c033 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Aug 14 02:50:44 2015 -0500 southbridge/amd/sr5650: Use correct PCI configuration block offset Change-Id: I4277d1788d8f9a501399218544aa6d4d11349ccc Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sr5650/acpi/sr5650.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/sr5650/acpi/sr5650.asl b/src/southbridge/amd/sr5650/acpi/sr5650.asl index 54259b0..93a74e3 100644 --- a/src/southbridge/amd/sr5650/acpi/sr5650.asl +++ b/src/southbridge/amd/sr5650/acpi/sr5650.asl @@ -15,8 +15,8 @@ */ Scope(\) { - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ - Name(HPBA, 0xFED00000) /* Base address of HPET table */ + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ /* PIC IRQ mapping registers, C00h-C01h */ OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)

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Patch set updated for coreboot: northbridge/amd/amdfam10: Work around sporadic lockups when CC6 enabled
by Timothy Pearson 24 Nov '15

24 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12054 -gerrit commit 9346e87bb14e284fe1051576b7f692ee5e244768 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Aug 20 15:53:25 2015 -0500 northbridge/amd/amdfam10: Work around sporadic lockups when CC6 enabled Change-Id: If31140651f25f9c524a824b2da552ce3690eae18 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 60ad8c4..3177a5f 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -812,6 +812,20 @@ static void amdfam10_domain_read_resources(device_t dev) else qword = 0x1000000; + /* FIXME + * The BKDG appears to be incorrect as to the location of the CC6 save region + * lower boundary on non-interleaved systems, causing lockups on attempted write + * to the CC6 save region. + * + * For now, work around by allocating the maximum possible CC6 save region size. + * + * Determine if this is a BKDG error or a setup problem and remove this warning! + */ + qword = (0x1 << 27); + max_range_limit = (((uint64_t)(pci_read_config32(get_node_pci(max_node, 1), 0x124) & 0x1fffff)) << 27) - 1; + + printk(BIOS_INFO, "Reserving CC6 save segment base: %08llx size: %08llx\n", (max_range_limit + 1), qword); + /* Reserve the CC6 save segment */ reserved_ram_resource(dev, 8, (max_range_limit + 1) >> 10, qword >> 10); }

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coreboot-gerrit November 2015