coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Add missing IOMMU setup
by Timothy Pearson 24 Nov '15

24 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12527 -gerrit commit b14a1f5b1afcee989e88de1043efc61fc547a5d0 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 04:06:10 2015 -0600 mainboard/asus/kgpe-d16: Add missing IOMMU setup Change-Id: I9a00bdbcd47804b6d83c0231cd515773d02ff951 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/devicetree.cb | 1 + src/mainboard/asus/kgpe-d16/romstage.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb index ef7277d..014a35f 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb @@ -15,6 +15,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex chip southbridge/amd/sr5650 # Primary southbridge device pci 0.0 on end # HT Root Complex 0x9600 device pci 0.1 on end # CLKCONFIG + device pci 0.2 on end # IOMMU device pci 2.0 on # PCIE P2P bridge 0x9603 (GPP1 Port0) # Slot # PCI E 1 / PCI E 2 end diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 6503b90..ccb85f4 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -458,6 +458,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) die("After soft_reset_x - shouldn't see this message!!!\n"); } + sr5650_htinit_dect_and_enable_isochronous_link(); + /* Set default DDR memory voltage * This will be overridden later during RAM initialization */

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Patch merged into coreboot/master: nb/amd/amdfam10: Fix gart setup not working on Fam15h processors
by gerrit＠coreboot.org 24 Nov '15

24 Nov '15

the following patch was just integrated into master: commit ce3456dacd78df10c3bad360deb3ff9bc521aec5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Aug 11 17:52:31 2015 -0500 nb/amd/amdfam10: Fix gart setup not working on Fam15h processors Change-Id: Ib78620c30502df6add9cc2ea1dbd4fb6dc89203e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12047 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> See http://review.coreboot.org/12047 for details. -gerrit

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Patch merged into coreboot/master: northbridge/amd/amdht: Add isochronous setup support
by gerrit＠coreboot.org 24 Nov '15

24 Nov '15

the following patch was just integrated into master: commit 50001b80f54c3d1cdd926102c68d33e549541205 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Aug 11 17:47:48 2015 -0500 northbridge/amd/amdht: Add isochronous setup support The coherent fabric on all Family 10h/15h devices supports isochronous mode, which is required for IOMMU operation. Add initial support for isochronous operation. Change-Id: Idd7c9b94a65f856b0059e1d45f8719d9475771b6 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12042 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12042 for details. -gerrit

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Patch merged into coreboot/master: amd/amdfam10: Control Fam15h cache partitioning via nvram
by gerrit＠coreboot.org 24 Nov '15

24 Nov '15

the following patch was just integrated into master: commit 68130f506df5c77107ece8d71aa45b598be77b45 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Aug 9 02:47:51 2015 -0500 amd/amdfam10: Control Fam15h cache partitioning via nvram Add options to control cache partitioning and overall memory performance via nvram. Change-Id: I3dd5d7f3640aee0395a68645c0242307605d3ce7 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12041 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12041 for details. -gerrit

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Patch merged into coreboot/master: northbridge/amd/amdfam10: Rename mislabeled iommu nvram option to gart
by gerrit＠coreboot.org 24 Nov '15

24 Nov '15

the following patch was just integrated into master: commit b174667534c327b8558ff04986a2c1a971b7f04e Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Aug 11 17:52:03 2015 -0500 northbridge/amd/amdfam10: Rename mislabeled iommu nvram option to gart Change-Id: Ia24102e164eb5753ade3f9b5ab21eba2fa60836b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12046 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12046 for details. -gerrit

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New patch to review for coreboot: amd/car: don't apply Fam10h Errata 343 fix to Fam0Fh
by Jonathan A. Kollasch 24 Nov '15

24 Nov '15

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12528 -gerrit commit 3b62f24e4e41f5ddac2c83afc362aca78c678503 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Tue Nov 24 10:15:22 2015 -0600 amd/car: don't apply Fam10h Errata 343 fix to Fam0Fh Change-Id: Id215d2822b78917939c28f7a922a94e02e5d15bf Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/cpu/amd/car/post_cache_as_ram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 2c11777..c1218d1 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -121,7 +121,7 @@ void post_cache_as_ram(void) prepare_romstage_ramstack(resume_backup_memory); /* from here don't store more data in CAR */ - if (family < 0x6f) { + if (family < 0x6f && family > 0xf) { /* Family 10h or earlier */ vErrata343(); }

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Patch merged into coreboot/master: Unify OBJCOPY arguments throughout various x86 stages
by gerrit＠coreboot.org 24 Nov '15

24 Nov '15

the following patch was just integrated into master: commit 593f5c8a48043153963c04060ed8de7d60604bc1 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 18:03:18 2015 -0700 Unify OBJCOPY arguments throughout various x86 stages Instead of having to have an ifeq() all across the code base, use $(target-objcopy). And correct target-objcopy to a value that objcopy actually understands. Change-Id: Id5dea6420bee02a044dc488b5086d109e806d605 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/11090 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11090 for details. -gerrit

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Patch merged into coreboot/master: northbridge/intel/pineview: Add minimal Pineview northbridge
by gerrit＠coreboot.org 24 Nov '15

24 Nov '15

the following patch was just integrated into master: commit 62477931c88c701617445a3a23769583e7b830b5 Author: Damien Zammit <damien(a)zamaudio.com> Date: Sun May 3 21:34:38 2015 +1000 northbridge/intel/pineview: Add minimal Pineview northbridge Based on i945. Tested on Intel D510MO mainboard, board boots to UART console with this code. Change-Id: I1d92a1aa6d6d767bda8379807dc26b50b9de75c9 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: http://review.coreboot.org/10073 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/10073 for details. -gerrit

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Patch merged into coreboot/master: cpu/intel/socket_FCBGA559: Add new socket for Atom D5xx
by gerrit＠coreboot.org 24 Nov '15

24 Nov '15

the following patch was just integrated into master: commit 0cf0805e924b834c30fe290412e94e42f8f49cfb Author: Damien Zammit <damien(a)zamaudio.com> Date: Sun May 3 19:49:37 2015 +1000 cpu/intel/socket_FCBGA559: Add new socket for Atom D5xx Tested on Intel D510MO board, boots to UART console. Change-Id: I82a630c9836c099d0fcc62e019c20f328a75151d Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: http://review.coreboot.org/10066 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/10066 for details. -gerrit

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Patch merged into coreboot/master: southbridge/intel: Use i82801gx code for NM10
by gerrit＠coreboot.org 24 Nov '15

24 Nov '15

the following patch was just integrated into master: commit ef33e035e7bb4ab913e58709524f7f8bf24b5bb1 Author: Damien Zammit <damien(a)zamaudio.com> Date: Sat Nov 14 01:03:39 2015 +1100 southbridge/intel: Use i82801gx code for NM10 It works as an ICH7 on Intel D510MO mainboard Change-Id: Ib8c76c001dffee8f93e3d6aa3156d4413b2e842a Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: http://review.coreboot.org/12431 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/12431 for details. -gerrit

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coreboot-gerrit November 2015