Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6620
-gerrit
commit 5ca8738ea6bdc9c71f24fe04288f4da9e33ad484
Author: Gabe Black <gabeblack(a)google.com>
Date: Sun Oct 6 10:54:53 2013 -0700
tegra124: Implement the monotonic timer by reading the 1us timer register.
It turns out there's a register in tegra which automatically counts at 1us
increments. It's primarily intended for hardware to use (I think to drive
other timers) but we can read it ourselves since a 1us timer is exactly what
we need to support the monotonic timer API.
Change-Id: I68e947944acec7b460e61f42dbb325643a9739e8
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/172044
Reviewed-by: Ronald Minnich <rminnich(a)chromium.org>
Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit 161a39c53404ea0125221bbd54e54996967d6855)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/soc/nvidia/tegra124/monotonic_timer.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/soc/nvidia/tegra124/monotonic_timer.c b/src/soc/nvidia/tegra124/monotonic_timer.c
index 3423dde..7967b83 100644
--- a/src/soc/nvidia/tegra124/monotonic_timer.c
+++ b/src/soc/nvidia/tegra124/monotonic_timer.c
@@ -17,8 +17,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <arch/io.h>
+#include <soc/addressmap.h>
#include <timer.h>
void timer_monotonic_get(struct mono_time *mt)
{
+ mono_time_set_usecs(mt, read32((void *)TEGRA_TMRUS_BASE));
}
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6619
-gerrit
commit fd36c315919a021ce4e8a8ee70da60fa4e9b5e94
Author: Gabe Black <gabeblack(a)google.com>
Date: Sat Sep 28 20:39:21 2013 -0700
tegra124: Add stack related config options to the Kconfig.
Otherwise the stack ends up down at 0 and has 0 bytes.
Change-Id: I0e3c80a0c5b0180d95819ab44829c2a0b527a54d
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/171015
Reviewed-by: Ronald Minnich <rminnich(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit 3e69a477474697bcbc40762ec166e8a515d8b0c2)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/soc/nvidia/tegra124/Kconfig | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig
index 5d8fd4c..8a0dee4 100644
--- a/src/soc/nvidia/tegra124/Kconfig
+++ b/src/soc/nvidia/tegra124/Kconfig
@@ -39,4 +39,16 @@ config BOOTBLOCK_BASE
hex
default 0x80000000
+config STACK_TOP
+ hex
+ default 0x80400000
+
+config STACK_BOTTOM
+ hex
+ default 0x803f8000
+
+config STACK_SIZE
+ hex
+ default 0x800
+
endif
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6618
-gerrit
commit 45c5939bbc0047cf1098cf8b4a708e406b039308
Author: Gabe Black <gabeblack(a)google.com>
Date: Fri Sep 27 03:06:34 2013 -0700
tegra124: Add some make rules which will wrap the bootblock in the BCT.
These rules slip into the normal bootblock preperation process and use the
cbootimage utility to wrap it in a BCT.
Change-Id: I8cf2a3fb6e9f1d792d536c533d4813acfb550cea
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/170924
Reviewed-by: Gabe Black <gabeblack(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit cf4a9b0712c21b885bb59310671fb87e38abb665)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/soc/nvidia/tegra124/Makefile.inc | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc
index 49e2b1f..14707df 100644
--- a/src/soc/nvidia/tegra124/Makefile.inc
+++ b/src/soc/nvidia/tegra124/Makefile.inc
@@ -1,3 +1,5 @@
+CBOOTIMAGE = cbootimage
+
bootblock-y += cbfs.c
romstage-y += cbfs.c
@@ -7,3 +9,32 @@ romstage-y += timer.c
ramstage-y += cbfs.c
ramstage-y += monotonic_timer.c
ramstage-y += timer.c
+
+# We want to grab the bootblock right before it goes into the image and wrap
+# it inside a BCT, but ideally we would do that without making special, one
+# use modifications to the main ARM Makefile. We do this in two ways. First,
+# we copy bootblock.elf to bootblock.raw.elf and allow the %.bin: %.elf
+# template rule to turn it into bootblock.raw.bin. This makes sure whatever
+# processing is supposed to happen to turn an .elf into a .bin happens.
+#
+# Second, we add our own rule for creating bootblock.bin from
+# bootblock.raw.bin which displaces the template rule. When other rules that
+# package up the image pull in bootblock.bin, it will be this wrapped version
+# instead of the raw bootblock.
+
+$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
+ cp $< $@
+
+$(obj)/generated/bct.bin: $(obj)/generated/bct.cfg
+ @printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n"
+ $(CBOOTIMAGE) -gbct --soc tegra124 $< $@
+
+BCT_BIN = $(obj)/generated/bct.bin
+BCT_WRAPPER = $(obj)/generated/bct.wrapper
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BCT_BIN)
+ echo "Version = 1;" > $(BCT_WRAPPER)
+ echo "Redundancy = 1;" >> $(BCT_WRAPPER)
+ echo "Bctfile = $(BCT_BIN);" >> $(BCT_WRAPPER)
+ echo "BootLoader = $<,$(CONFIG_BOOTBLOCK_BASE),$(CONFIG_BOOTBLOCK_BASE),Complete;" >> $(BCT_WRAPPER)
+ @printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n"
+ $(CBOOTIMAGE) $(BCT_WRAPPER) $@
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6617
-gerrit
commit 158a6db183cbe33d301a94193082a0e2f751ee68
Author: Julius Werner <jwerner(a)chromium.org>
Date: Tue Sep 3 16:44:15 2013 -0700
libpayload: usbhub: Don't clear PSC unless it was set
The current USB hub code always clears the port status change after
checking it, regardless of whether it was set in the first place. Since
this check runs on every poll, it might create a race condition where
the port status changes right between the GET_PORT_STATUS and the
CLEAR_FEATURE(C_PORT_CONNECT), thus clearing the statrus change flag
before it was ever read. Let's add one extra if() to avoid that possible
headache.
Change-Id: Idd46c2199dc6c240bd9ef068fbe70cccc88bac42
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/168098
(cherry picked from commit f7f6f008f701ab3e4a4f785032d8024d676e11cb)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
payloads/libpayload/drivers/usb/usbhub.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/payloads/libpayload/drivers/usb/usbhub.c b/payloads/libpayload/drivers/usb/usbhub.c
index 4e077f6..ff7904c 100644
--- a/payloads/libpayload/drivers/usb/usbhub.c
+++ b/payloads/libpayload/drivers/usb/usbhub.c
@@ -48,7 +48,8 @@ usb_hub_port_status_changed(usbdev_t *const dev, const int port)
{
unsigned short buf[2] = { 0, 0 };
get_status (dev, port, DR_PORT, 4, buf);
- clear_feature (dev, port, SEL_C_PORT_CONNECTION, DR_PORT);
+ if (buf[1] & PORT_CONNECTION)
+ clear_feature (dev, port, SEL_C_PORT_CONNECTION, DR_PORT);
return buf[1] & PORT_CONNECTION;
}
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6616
-gerrit
commit 06e5a3e67cd63b09504897c08074695098c40921
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Thu Aug 29 15:57:11 2013 -0700
chromeos: On ARM platforms VBNV lives in the EC
This patch renames the x86 way of doing things to
explicitly mention CMOS (which is not available on
our ARM platforms) and adds an implementation to
get VBNV through the Chrome EC. We might want to
refine this further in the future to allow VBNV
in the EC even on x86 platforms. Will be fixed when
that appears. Also, not all ARM platforms running
ChromeOS might use the Google EC in the future, in
which case this code will need additional work.
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Change-Id: Ice09d0e277dbb131f9ad763e762e8877007db901
Reviewed-on: https://chromium-review.googlesource.com/167540
Reviewed-by: David Hendrix <dhendrix(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)google.com>
Commit-Queue: Stefan Reinauer <reinauer(a)google.com>
(cherry picked from commit 8df6cdbcacb082af88c069ef8b542b44ff21d97a)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/ec/google/chromeec/ec.c | 34 ++++++-
src/ec/google/chromeec/ec.h | 1 +
src/mainboard/google/pit/chromeos.c | 4 +-
src/vendorcode/google/chromeos/Makefile.inc | 7 +-
src/vendorcode/google/chromeos/vbnv.c | 147 ----------------------------
src/vendorcode/google/chromeos/vbnv_cmos.c | 147 ++++++++++++++++++++++++++++
src/vendorcode/google/chromeos/vbnv_ec.c | 140 ++++++++++++++++++++++++++
7 files changed, 328 insertions(+), 152 deletions(-)
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index ab4db54..24f9693 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -18,6 +18,7 @@
*/
#include <stdint.h>
+#include <string.h>
#include <console/console.h>
#include <bootmode.h>
#include <arch/io.h>
@@ -26,7 +27,6 @@
#include <reset.h>
#include <elog.h>
#include <stdlib.h>
-#include <string.h>
#include "chip.h"
#include "ec.h"
@@ -154,6 +154,38 @@ u16 google_chromeec_get_board_version(void)
return board_v.board_version;
}
+
+int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len)
+{
+ struct chromeec_command cec_cmd;
+ struct ec_params_vbnvcontext cmd_vbnvcontext;
+ struct ec_response_vbnvcontext rsp_vbnvcontext;
+
+ if (len != EC_VBNV_BLOCK_SIZE)
+ return -1;
+
+
+ cec_cmd.cmd_code = EC_CMD_VBNV_CONTEXT;
+ cec_cmd.cmd_version = EC_VER_VBNV_CONTEXT;
+ cec_cmd.cmd_data_in = &cmd_vbnvcontext;
+ cec_cmd.cmd_data_out = &rsp_vbnvcontext;
+ cec_cmd.cmd_size_in = sizeof(cmd_vbnvcontext);
+ cec_cmd.cmd_size_out = sizeof(rsp_vbnvcontext);
+
+ cmd_vbnvcontext.op = is_read ? EC_VBNV_CONTEXT_OP_READ :
+ EC_VBNV_CONTEXT_OP_WRITE;
+
+ if (!is_read)
+ memcpy(&cmd_vbnvcontext.block, data, EC_VBNV_BLOCK_SIZE);
+
+ google_chromeec_command(&cec_cmd);
+
+ if (is_read)
+ memcpy(data, &rsp_vbnvcontext.block, EC_VBNV_BLOCK_SIZE);
+
+ return cec_cmd.cmd_code;
+}
+
#endif /* ! __SMM__ */
#ifndef __PRE_RAM__
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index d033bab..cf77b69 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -46,6 +46,7 @@ u32 google_chromeec_get_events_b(void);
int google_chromeec_kbbacklight(int percent);
void google_chromeec_post(u8 postcode);
void google_chromeec_log_events(u32 mask);
+int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len);
enum usb_charge_mode {
USB_CHARGE_MODE_DISABLED,
diff --git a/src/mainboard/google/pit/chromeos.c b/src/mainboard/google/pit/chromeos.c
index 28ec2b5..c2db165 100644
--- a/src/mainboard/google/pit/chromeos.c
+++ b/src/mainboard/google/pit/chromeos.c
@@ -95,7 +95,7 @@ int get_recovery_mode_switch(void)
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
}
-int get_recovery_mode_from_vbnv(void)
+int get_write_protect_state(void)
{
- return 0;
+ return 0; // FIXME what GPIO? // WP hard coded to disabled
}
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index ccde71a..b9e42da 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -17,9 +17,12 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vbnv.c
-ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += vbnv.c
+romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vbnv_cmos.c
+ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += vbnv_cmos.c
+romstage-$(CONFIG_ARCH_ROMSTAGE_ARMV7) += vbnv_ec.c
+ramstage-$(CONFIG_ARCH_RAMSTAGE_ARMV7) += vbnv_ec.c
romstage-$(CONFIG_ARCH_ROMSTAGE_X86_32) += vboot.c
+
ramstage-y += gnvs.c
romstage-y += fmap.c
ramstage-y += fmap.c
diff --git a/src/vendorcode/google/chromeos/vbnv.c b/src/vendorcode/google/chromeos/vbnv.c
deleted file mode 100644
index a13726d..0000000
--- a/src/vendorcode/google/chromeos/vbnv.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <types.h>
-#include <string.h>
-#include <console/console.h>
-#include <pc80/mc146818rtc.h>
-#include <arch/early_variables.h>
-#include "chromeos.h"
-
-#define VBNV_BLOCK_SIZE 16 /* Size of NV storage block in bytes */
-
-/* Constants for NV storage. We use this rather than structs and
- * bitfields so the data format is consistent across platforms and
- * compilers.
- */
-#define HEADER_OFFSET 0
-#define HEADER_MASK 0xC0
-#define HEADER_SIGNATURE 0x40
-#define HEADER_FIRMWARE_SETTINGS_RESET 0x20
-#define HEADER_KERNEL_SETTINGS_RESET 0x10
-
-#define BOOT_OFFSET 1
-#define BOOT_DEBUG_RESET_MODE 0x80
-#define BOOT_DISABLE_DEV_REQUEST 0x40
-#define BOOT_OPROM_NEEDED 0x20
-#define BOOT_TRY_B_COUNT_MASK 0x0F
-
-#define RECOVERY_OFFSET 2
-#define LOCALIZATION_OFFSET 3
-
-#define DEV_FLAGS_OFFSET 4
-#define DEV_BOOT_USB_MASK 0x01
-#define DEV_BOOT_SIGNED_ONLY_MASK 0x02
-
-#define KERNEL_FIELD_OFFSET 11
-#define CRC_OFFSET 15
-
-static int vbnv_initialized CAR_GLOBAL;
-static uint8_t vbnv[CONFIG_VBNV_SIZE] CAR_GLOBAL;
-
-/* Wrappers for accessing the variables marked as CAR_GLOBAL. */
-static inline int is_vbnv_initialized(void)
-{
- return car_get_var(vbnv_initialized);
-}
-
-static inline uint8_t *vbnv_data_addr(int index)
-{
- uint8_t *vbnv_arr = car_get_var_ptr(vbnv);
-
- return &vbnv_arr[index];
-}
-
-static inline uint8_t vbnv_data(int index)
-{
- return *vbnv_data_addr(index);
-}
-
-/* Return CRC-8 of the data, using x^8 + x^2 + x + 1 polynomial. A
- * table-based algorithm would be faster, but for only 15 bytes isn't
- * worth the code size.
- */
-
-static uint8_t crc8(const uint8_t * data, int len)
-{
- unsigned crc = 0;
- int i, j;
-
- for (j = len; j; j--, data++) {
- crc ^= (*data << 8);
- for (i = 8; i; i--) {
- if (crc & 0x8000)
- crc ^= (0x1070 << 3);
- crc <<= 1;
- }
- }
-
- return (uint8_t) (crc >> 8);
-}
-
-void read_vbnv(uint8_t *vbnv_copy)
-{
- int i;
-
- for (i = 0; i < CONFIG_VBNV_SIZE; i++)
- vbnv_copy[i] = cmos_read(CONFIG_VBNV_OFFSET + 14 + i);
-
- /* Check data for consistency */
- if ((HEADER_SIGNATURE != (vbnv_copy[HEADER_OFFSET] & HEADER_MASK))
- || (crc8(vbnv_copy, CRC_OFFSET) != vbnv_copy[CRC_OFFSET])) {
-
- /* Data is inconsistent (bad CRC or header),
- * so reset to defaults
- */
- memset(vbnv_copy, 0, VBNV_BLOCK_SIZE);
- vbnv_copy[HEADER_OFFSET] =
- (HEADER_SIGNATURE | HEADER_FIRMWARE_SETTINGS_RESET |
- HEADER_KERNEL_SETTINGS_RESET);
- }
-}
-
-void save_vbnv(const uint8_t *vbnv_copy)
-{
- int i;
-
- for (i = 0; i < CONFIG_VBNV_SIZE; i++)
- cmos_write(vbnv_copy[i], CONFIG_VBNV_OFFSET + 14 + i);
-}
-
-
-static void vbnv_setup(void)
-{
- read_vbnv(vbnv_data_addr(0));
- car_set_var(vbnv_initialized, 1);
-}
-
-int get_recovery_mode_from_vbnv(void)
-{
- if (!is_vbnv_initialized())
- vbnv_setup();
- return vbnv_data(RECOVERY_OFFSET);
-}
-
-int vboot_wants_oprom(void)
-{
- if (!is_vbnv_initialized())
- vbnv_setup();
-
- return (vbnv_data(BOOT_OFFSET) & BOOT_OPROM_NEEDED) ? 1 : 0;
-}
diff --git a/src/vendorcode/google/chromeos/vbnv_cmos.c b/src/vendorcode/google/chromeos/vbnv_cmos.c
new file mode 100644
index 0000000..a13726d
--- /dev/null
+++ b/src/vendorcode/google/chromeos/vbnv_cmos.c
@@ -0,0 +1,147 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/early_variables.h>
+#include "chromeos.h"
+
+#define VBNV_BLOCK_SIZE 16 /* Size of NV storage block in bytes */
+
+/* Constants for NV storage. We use this rather than structs and
+ * bitfields so the data format is consistent across platforms and
+ * compilers.
+ */
+#define HEADER_OFFSET 0
+#define HEADER_MASK 0xC0
+#define HEADER_SIGNATURE 0x40
+#define HEADER_FIRMWARE_SETTINGS_RESET 0x20
+#define HEADER_KERNEL_SETTINGS_RESET 0x10
+
+#define BOOT_OFFSET 1
+#define BOOT_DEBUG_RESET_MODE 0x80
+#define BOOT_DISABLE_DEV_REQUEST 0x40
+#define BOOT_OPROM_NEEDED 0x20
+#define BOOT_TRY_B_COUNT_MASK 0x0F
+
+#define RECOVERY_OFFSET 2
+#define LOCALIZATION_OFFSET 3
+
+#define DEV_FLAGS_OFFSET 4
+#define DEV_BOOT_USB_MASK 0x01
+#define DEV_BOOT_SIGNED_ONLY_MASK 0x02
+
+#define KERNEL_FIELD_OFFSET 11
+#define CRC_OFFSET 15
+
+static int vbnv_initialized CAR_GLOBAL;
+static uint8_t vbnv[CONFIG_VBNV_SIZE] CAR_GLOBAL;
+
+/* Wrappers for accessing the variables marked as CAR_GLOBAL. */
+static inline int is_vbnv_initialized(void)
+{
+ return car_get_var(vbnv_initialized);
+}
+
+static inline uint8_t *vbnv_data_addr(int index)
+{
+ uint8_t *vbnv_arr = car_get_var_ptr(vbnv);
+
+ return &vbnv_arr[index];
+}
+
+static inline uint8_t vbnv_data(int index)
+{
+ return *vbnv_data_addr(index);
+}
+
+/* Return CRC-8 of the data, using x^8 + x^2 + x + 1 polynomial. A
+ * table-based algorithm would be faster, but for only 15 bytes isn't
+ * worth the code size.
+ */
+
+static uint8_t crc8(const uint8_t * data, int len)
+{
+ unsigned crc = 0;
+ int i, j;
+
+ for (j = len; j; j--, data++) {
+ crc ^= (*data << 8);
+ for (i = 8; i; i--) {
+ if (crc & 0x8000)
+ crc ^= (0x1070 << 3);
+ crc <<= 1;
+ }
+ }
+
+ return (uint8_t) (crc >> 8);
+}
+
+void read_vbnv(uint8_t *vbnv_copy)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_VBNV_SIZE; i++)
+ vbnv_copy[i] = cmos_read(CONFIG_VBNV_OFFSET + 14 + i);
+
+ /* Check data for consistency */
+ if ((HEADER_SIGNATURE != (vbnv_copy[HEADER_OFFSET] & HEADER_MASK))
+ || (crc8(vbnv_copy, CRC_OFFSET) != vbnv_copy[CRC_OFFSET])) {
+
+ /* Data is inconsistent (bad CRC or header),
+ * so reset to defaults
+ */
+ memset(vbnv_copy, 0, VBNV_BLOCK_SIZE);
+ vbnv_copy[HEADER_OFFSET] =
+ (HEADER_SIGNATURE | HEADER_FIRMWARE_SETTINGS_RESET |
+ HEADER_KERNEL_SETTINGS_RESET);
+ }
+}
+
+void save_vbnv(const uint8_t *vbnv_copy)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_VBNV_SIZE; i++)
+ cmos_write(vbnv_copy[i], CONFIG_VBNV_OFFSET + 14 + i);
+}
+
+
+static void vbnv_setup(void)
+{
+ read_vbnv(vbnv_data_addr(0));
+ car_set_var(vbnv_initialized, 1);
+}
+
+int get_recovery_mode_from_vbnv(void)
+{
+ if (!is_vbnv_initialized())
+ vbnv_setup();
+ return vbnv_data(RECOVERY_OFFSET);
+}
+
+int vboot_wants_oprom(void)
+{
+ if (!is_vbnv_initialized())
+ vbnv_setup();
+
+ return (vbnv_data(BOOT_OFFSET) & BOOT_OPROM_NEEDED) ? 1 : 0;
+}
diff --git a/src/vendorcode/google/chromeos/vbnv_ec.c b/src/vendorcode/google/chromeos/vbnv_ec.c
new file mode 100644
index 0000000..78da541
--- /dev/null
+++ b/src/vendorcode/google/chromeos/vbnv_ec.c
@@ -0,0 +1,140 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <arch/early_variables.h>
+#include <ec/google/chromeec/ec.h>
+#include "chromeos.h"
+
+#define VBNV_BLOCK_SIZE 16 /* Size of NV storage block in bytes */
+
+/* Constants for NV storage. We use this rather than structs and
+ * bitfields so the data format is consistent across platforms and
+ * compilers.
+ */
+#define HEADER_OFFSET 0
+#define HEADER_MASK 0xC0
+#define HEADER_SIGNATURE 0x40
+#define HEADER_FIRMWARE_SETTINGS_RESET 0x20
+#define HEADER_KERNEL_SETTINGS_RESET 0x10
+
+#define BOOT_OFFSET 1
+#define BOOT_DEBUG_RESET_MODE 0x80
+#define BOOT_DISABLE_DEV_REQUEST 0x40
+#define BOOT_OPROM_NEEDED 0x20
+#define BOOT_TRY_B_COUNT_MASK 0x0F
+
+#define RECOVERY_OFFSET 2
+#define LOCALIZATION_OFFSET 3
+
+#define DEV_FLAGS_OFFSET 4
+#define DEV_BOOT_USB_MASK 0x01
+#define DEV_BOOT_SIGNED_ONLY_MASK 0x02
+
+#define KERNEL_FIELD_OFFSET 11
+#define CRC_OFFSET 15
+
+static int vbnv_initialized CAR_GLOBAL;
+static uint8_t vbnv[VBNV_BLOCK_SIZE] CAR_GLOBAL;
+
+/* Wrappers for accessing the variables marked as CAR_GLOBAL. */
+static inline int is_vbnv_initialized(void)
+{
+ return car_get_var(vbnv_initialized);
+}
+
+static inline uint8_t *vbnv_data_addr(int index)
+{
+ uint8_t *vbnv_arr = car_get_var_ptr(vbnv);
+
+ return &vbnv_arr[index];
+}
+
+static inline uint8_t vbnv_data(int index)
+{
+ return *vbnv_data_addr(index);
+}
+
+/* Return CRC-8 of the data, using x^8 + x^2 + x + 1 polynomial. A
+ * table-based algorithm would be faster, but for only 15 bytes isn't
+ * worth the code size.
+ */
+
+static uint8_t crc8(const uint8_t * data, int len)
+{
+ unsigned crc = 0;
+ int i, j;
+
+ for (j = len; j; j--, data++) {
+ crc ^= (*data << 8);
+ for (i = 8; i; i--) {
+ if (crc & 0x8000)
+ crc ^= (0x1070 << 3);
+ crc <<= 1;
+ }
+ }
+
+ return (uint8_t) (crc >> 8);
+}
+
+void read_vbnv(uint8_t *vbnv_copy)
+{
+ google_chromeec_vbnv_context(1, vbnv_copy, VBNV_BLOCK_SIZE);
+
+ /* Check data for consistency */
+ if ((HEADER_SIGNATURE != (vbnv_copy[HEADER_OFFSET] & HEADER_MASK))
+ || (crc8(vbnv_copy, CRC_OFFSET) != vbnv_copy[CRC_OFFSET])) {
+
+ /* Data is inconsistent (bad CRC or header),
+ * so reset to defaults
+ */
+ memset(vbnv_copy, 0, VBNV_BLOCK_SIZE);
+ vbnv_copy[HEADER_OFFSET] =
+ (HEADER_SIGNATURE | HEADER_FIRMWARE_SETTINGS_RESET |
+ HEADER_KERNEL_SETTINGS_RESET);
+ }
+}
+
+void save_vbnv(const uint8_t *vbnv_copy)
+{
+ google_chromeec_vbnv_context(0, (uint8_t *)vbnv_copy, VBNV_BLOCK_SIZE);
+}
+
+static void vbnv_setup(void)
+{
+ read_vbnv(vbnv_data_addr(0));
+ car_set_var(vbnv_initialized, 1);
+}
+
+int get_recovery_mode_from_vbnv(void)
+{
+ if (!is_vbnv_initialized())
+ vbnv_setup();
+ return vbnv_data(RECOVERY_OFFSET);
+}
+
+int vboot_wants_oprom(void)
+{
+ if (!is_vbnv_initialized())
+ vbnv_setup();
+
+ return (vbnv_data(BOOT_OFFSET) & BOOT_OPROM_NEEDED) ? 1 : 0;
+}
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6615
-gerrit
commit 1e4c0430945cd58c6e6395f6f0cdf452247959b4
Author: ChromeOS Developer <dparker(a)chromium.org>
Date: Mon Dec 16 23:41:11 2013 -0800
Haswell: Lower TJ_MAX to 100C. Adjust critical temps to match.
Change-Id: I3326b6e3c412b6360af37030cefd13d95b704e70
Signed-off-by: Dave Parker <dparker(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180750
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit 1978b0f91b2e91d2251721c7c6981d51a6930b61)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/mainboard/google/bolt/thermal.h | 10 +++++-----
src/mainboard/google/falco/thermal.h | 6 +++---
src/mainboard/google/peppy/thermal.h | 10 +++++-----
3 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/src/mainboard/google/bolt/thermal.h b/src/mainboard/google/bolt/thermal.h
index eeedf25..32eec0e 100644
--- a/src/mainboard/google/bolt/thermal.h
+++ b/src/mainboard/google/bolt/thermal.h
@@ -28,16 +28,16 @@
#define CTDP_NOMINAL_THRESHOLD_ON 0
/* Config TDP Down */
-#define CTDP_DOWN_THRESHOLD_OFF 80
-#define CTDP_DOWN_THRESHOLD_ON 90
+#define CTDP_DOWN_THRESHOLD_OFF 75
+#define CTDP_DOWN_THRESHOLD_ON 85
/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE 104
+#define CRITICAL_TEMPERATURE 99
/* Temperature which OS will throttle CPU */
-#define PASSIVE_TEMPERATURE 100
+#define PASSIVE_TEMPERATURE 95
/* Tj_max value for calculating PECI CPU temperature */
-#define MAX_TEMPERATURE 105
+#define MAX_TEMPERATURE 100
#endif
diff --git a/src/mainboard/google/falco/thermal.h b/src/mainboard/google/falco/thermal.h
index 9bd6ee6..332e5a0 100644
--- a/src/mainboard/google/falco/thermal.h
+++ b/src/mainboard/google/falco/thermal.h
@@ -26,12 +26,12 @@
#define EC_THROTTLE_POWER_LIMIT 12 /* 12W */
/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE 104
+#define CRITICAL_TEMPERATURE 99
/* Temperature which OS will throttle CPU */
-#define PASSIVE_TEMPERATURE 100
+#define PASSIVE_TEMPERATURE 95
/* Tj_max value for calculating PECI CPU temperature */
-#define MAX_TEMPERATURE 105
+#define MAX_TEMPERATURE 100
#endif
diff --git a/src/mainboard/google/peppy/thermal.h b/src/mainboard/google/peppy/thermal.h
index 74ec0b5..afa4391 100644
--- a/src/mainboard/google/peppy/thermal.h
+++ b/src/mainboard/google/peppy/thermal.h
@@ -23,16 +23,16 @@
/* Control TDP Settings */
#define CTL_TDP_SENSOR_ID 0 /* PECI */
#define CTL_TDP_POWER_LIMIT 12 /* 12W */
-#define CTL_TDP_THRESHOLD_OFF 68 /* Normal at 68C */
-#define CTL_TDP_THRESHOLD_ON 73 /* Limited at 73C */
+#define CTL_TDP_THRESHOLD_OFF 80 /* Normal at 80C */
+#define CTL_TDP_THRESHOLD_ON 85 /* Limited at 85C */
/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE 104
+#define CRITICAL_TEMPERATURE 99
/* Temperature which OS will throttle CPU */
-#define PASSIVE_TEMPERATURE 100
+#define PASSIVE_TEMPERATURE 95
/* Tj_max value for calculating PECI CPU temperature */
-#define MAX_TEMPERATURE 105
+#define MAX_TEMPERATURE 100
#endif
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6613
-gerrit
commit 48825d430ec745cc0b7d397a0481fc0567287be4
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Thu Aug 29 14:05:21 2013 -0700
exynos5420/pit/kirby: re-factor membaseconfig0/1 usage
membaseconfig0/1 are utterly dependent on the mainboard's particular
DRAM setup. This defines their values in the mem_timings struct for
pit and kirby.
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Old-Change-Id: Ifd782d1229b2418f8ddbf0bcb3f45cc828ac34b0
Reviewed-on: https://chromium-review.googlesource.com/167488
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-by: ron minnich <rminnich(a)chromium.org>
(cherry picked from commit 80eebd5bc0dbb9fabf81f46c25dcd5c5d5747579)
exynos5420/kirby: necessary updates for DRAM
This updates DRAM usage for Kirby so that we can actually
use the available 3.5GB:
- The chips on Kirby have 16 row address lines.
- CONFIG_DRAM_SIZE_MB should be 3584 (4096-512).
- We use 2 DMC channels on Kirby (each with 2GB).
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Old-Change-Id: I86d1a96d0d1a028587f7655f8de5a2e52165e9d2
Reviewed-on: https://chromium-review.googlesource.com/167489
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-by: ron minnich <rminnich(a)chromium.org>
(cherry picked from commit 04bbaf5d8e125166dd689f656d5b37776be01fb1)
Squashed a small commit that mainly dealt with the already
deleted kirby mainboard.
Change-Id: I4e45bc8a446715897ec21b0160701152fa6b226b
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/cpu/samsung/exynos5420/dmc_init_ddr3.c | 24 +++++++++---------------
src/cpu/samsung/exynos5420/setup.h | 16 +++++++---------
src/mainboard/google/pit/memory.c | 7 +++++++
3 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
index 1126dca..1d7b8a8 100644
--- a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
+++ b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
@@ -145,21 +145,15 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
update_reset_dll(drex0, DDR_MODE_DDR3);
update_reset_dll(drex1, DDR_MODE_DDR3);
- /* Set Base Address:
- * 0x2000_0000 ~ 0x5FFF_FFFF
- * 0x6000_0000 ~ 0x9FFF_FFFF
- */
- /* MEMBASECONFIG0 */
- val = DMC_MEMBASECONFIGx_CHIP_BASE(DMC_CHIP_BASE_0) |
- DMC_MEMBASECONFIGx_CHIP_MASK(DMC_CHIP_MASK);
- writel(val, &tzasc0->membaseconfig0);
- writel(val, &tzasc1->membaseconfig0);
-
- /* MEMBASECONFIG1 */
- val = DMC_MEMBASECONFIGx_CHIP_BASE(DMC_CHIP_BASE_1) |
- DMC_MEMBASECONFIGx_CHIP_MASK(DMC_CHIP_MASK);
- writel(val, &tzasc0->membaseconfig1);
- writel(val, &tzasc1->membaseconfig1);
+ /* MEMBASECONFIG0 (CS0) */
+ writel(mem->membaseconfig0, &tzasc0->membaseconfig0);
+ writel(mem->membaseconfig0, &tzasc1->membaseconfig0);
+
+ /* MEMBASECONFIG1 (CS1) */
+ if (mem->chips_per_channel == 2) {
+ writel(mem->membaseconfig1, &tzasc0->membaseconfig1);
+ writel(mem->membaseconfig1, &tzasc1->membaseconfig1);
+ }
/* Memory Channel Inteleaving Size
* Exynos5420 Channel interleaving = 128 bytes
diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h
index 3bd36b2..950c2c6 100644
--- a/src/cpu/samsung/exynos5420/setup.h
+++ b/src/cpu/samsung/exynos5420/setup.h
@@ -136,6 +136,7 @@ struct exynos5_phy_control;
#define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8)
#define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4)
#define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4)
+#define DMC_MEMCONFIGx_CHIP_ROW_16 (4 << 4)
#define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0)
#define DMC_MEMBASECONFIGx_CHIP_BASE(x) (x << 16)
@@ -767,15 +768,12 @@ struct exynos5_phy_control;
#define DPWRDN_EN (1 << 1)
#define DSREF_EN (1 << 5)
-/* As we use channel interleaving, therefore value of the base address
- * register must be set as half of the bus base address
- * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
- * we need to set half 0x10 to the membaseconfigx registers
- * see exynos5420 UM section 17.17.3.21 for more
- */
-#define DMC_CHIP_BASE_0 0x10
-#define DMC_CHIP_BASE_1 0x50
-#define DMC_CHIP_MASK 0x7C0
+/* AXI base address mask */
+#define DMC_CHIP_MASK_256MB 0x7f0
+#define DMC_CHIP_MASK_512MB 0x7e0
+#define DMC_CHIP_MASK_1GB 0x7c0
+#define DMC_CHIP_MASK_2GB 0x780
+#define DMC_CHIP_MASK_4GB 0x700
#define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0
#define MEMBASECONFIG_CHIP_MASK_OFFSET 0
diff --git a/src/mainboard/google/pit/memory.c b/src/mainboard/google/pit/memory.c
index 4ac3d0c..0c30773 100644
--- a/src/mainboard/google/pit/memory.c
+++ b/src/mainboard/google/pit/memory.c
@@ -90,6 +90,13 @@ const struct mem_timings mem_timings = {
DMC_MEMCONTROL_BL_8 |
DMC_MEMCONTROL_PZQ_DISABLE |
DMC_MEMCONTROL_MRR_BYTE_7_0,
+ /*
+ * For channel interleaving, the chip_base needs to be set to
+ * half the bus address. So for a base address of 0x2000_0000,
+ * the chip_base value is 0x20 without interleaving and 0x10
+ * with channel interleaving. See note in section 17.14.
+ */
+ .membaseconfig0 = (0x10 << 16) | DMC_CHIP_MASK_1GB,
.memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
DMC_MEMCONFIGx_CHIP_COL_10 |
DMC_MEMCONFIGx_CHIP_ROW_15 |