the following patch was just integrated into master:
commit 40c845d3529cfd1a58c63f2cf356388b5d76e955
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Sun Aug 10 19:32:34 2014 +0200
lint: provide better GPL license text test
Still not lint-stable due to too many open issues, but
at least it doesn't try to touch files that aren't part
of the repository anymore.
Change-Id: I654b15480094c7731a7d0d17fa1622a0b41ac34a
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6584
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/6584 for details.
-gerrit
Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6364
-gerrit
commit 4b28554901d119fc52f5a705021d40168766b2d6
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Fri Jul 25 14:39:05 2014 -0600
payloads/external/SeaBIOS: Allow setting buffers below 0xC0000
Add the option to coreboot to set the SeaBIOS buffers below 0xC0000.
This is an absolute requirement on the upcoming Intel Rangeley
processor because it is designed so that only the processor can write
the higher memory areas. This prevents USB from bus-mastering into
the buffers when they're set in the typical 0xE0000 area.
This will be set to Y unless defaulted to N by the mainboard or
chipset.
Change-Id: I15638605d1c66a2277d4b852796db89978551a34
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
---
payloads/external/SeaBIOS/Makefile.inc | 3 +++
src/Kconfig | 13 +++++++++++++
src/arch/x86/Makefile.inc | 1 +
3 files changed, 17 insertions(+)
diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc
index 21f933a..03e2b08 100644
--- a/payloads/external/SeaBIOS/Makefile.inc
+++ b/payloads/external/SeaBIOS/Makefile.inc
@@ -31,6 +31,9 @@ ifeq ($(CONFIG_CONSOLE_SERIAL),y)
else
echo "# CONFIG_DEBUG_SERIAL is not set" >> $(OUT)/seabios/.config
endif
+ifneq ($(CONFIG_SEABIOS_MALLOC_UPPERMEMORY),y)
+ echo "# CONFIG_MALLOC_UPPERMEMORY is not set" >> $(OUT)/seabios/.config
+endif
ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y)
echo "# CONFIG_THREAD_OPTIONROMS is not set" >> $(OUT)/seabios/.config
endif
diff --git a/src/Kconfig b/src/Kconfig
index 693e0e7..eaa1329 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -636,6 +636,19 @@ config SEABIOS_THREAD_OPTIONROMS
variations during option ROM code execution. It is not
known if all option ROMs will behave properly with this option.
+config SEABIOS_MALLOC_UPPERMEMORY
+ bool
+ default y
+ depends on PAYLOAD_SEABIOS
+ help
+ Use the "Upper Memory Block" area (0xc0000-0xf0000) for internal
+ "low memory" allocations. If this is not selected, the memory is
+ instead allocated from the "9-segment" (0x90000-0xa0000).
+ This is not typically needed, but may be required on some platforms
+ to allow USB and SATA buffers to be written correctly by the
+ hardware. In general, if this is desired, the option will be
+ set to 'N' by the chipset Kconfig.
+
choice
prompt "GRUB2 version"
default GRUB2_MASTER
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 036dc1a..aa058c0 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -351,6 +351,7 @@ seabios:
CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \
CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \
CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) \
+ CONFIG_SEABIOS_MALLOC_UPPERMEMORY=$(CONFIG_SEABIOS_MALLOC_UPPERMEMORY) \
OUT=$(abspath $(obj)) IASL="$(IASL)"
filo:
the following patch was just integrated into master:
commit 4b65c2ad3300990ea6b471559c5d10b5c6111430
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Sun Aug 10 19:07:09 2014 +0200
lint: improve whitespace test
The whitespace test only trips on files that are part
of the git index - in particular not temporary editor
files or other cruft that doesn't hurt anyone.
Change-Id: I793fcc773845ee02281d8614b07e9c5958126a5a
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6582
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/6582 for details.
-gerrit
the following patch was just integrated into master:
commit f3155d205e6c78b09e4a69af89aa4853bf6a9f6d
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sun Aug 10 23:53:42 2014 +0200
gm45: Declare brightness variables for ACPI use.
Change-Id: I23a088919aaac16066e5dd8300a081a8095a93f0
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6589
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
See http://review.coreboot.org/6589 for details.
-gerrit
the following patch was just integrated into master:
commit e6df041b8bf8e37debc0d6a871080b64eea7a372
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Mon Jul 28 14:22:32 2014 -0600
mainboard/intel/minnowmax: Add MinnowMax mainboard
MinnowMax board using Intel's Bay Trail FSP
Working:
- Booting from SATA / USB / (USB3 with latest SeaBIOS)
Not working:
- Boot from SD
- S3 Suspend / Resume
***** To configure the FSP *****
Download the Bay Trail FSP and the binary config tool:
Modify the standard Bay Trail FSP:
run the bct tool with the command line options:
bct --bin <Bay Trail FSP Binary> \
--absf src/vendorcode/intel/fsp/baytrail/absf/minnowmax_Xgb.absf \
--bout <path to save the updated FSP to>
Here are the required changes for modifying the FSP manually:
Enable Memory Down: Enabled
DRAM Speed: 1066 MHz
DIMM_DWidth: x16
DIMM_Density: 4 Gbit (2GB Minnow Max) / 2 Gbit (1GB Minnow Max)
tCL: 7
tRP_tRCD: 7
tWR: 8
tRRD: 6
tRTP: 4
tFAW: 27
Other FSP values can remain the same.
***** To configure the vbios *****
The vbios is in the Bay Trail FSP package.
Download Intel's "Binary Modification Program" (BMP)
Use it to disable all ports except HDMI on port B.
Change-Id: I00d90e0d838d70c9d25c69f5115d0c9d6d19855c
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6429
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/6429 for details.
-gerrit