Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6606
-gerrit
commit 8de6efd2a28c47ea76c9235afa1469043d0ff378
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Mon Aug 11 12:37:24 2014 -0600
southbridge/intel/fsp_rangeley: fix to include irqroute.h twice
This matches what was done on baytrail in commit bfca984b -
soc/intel/fsp_baytrail: set up for including irqroute.h twice
irq_helper.h intentionally gets included into irqroute.asl twice - once
for pic mode and once for apic mode. Since people are used to seeing
guard statements on the .h files, add the guards to irqroute.h and add
a comment to irq_helper.h explaining why they aren't there.
Change-Id: I709f9370ce7db1b3ffac2297aeaba5cc670ec20c
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
---
src/mainboard/intel/mohonpeak/irqroute.h | 5 +++++
src/southbridge/intel/fsp_rangeley/acpi/irq_helper.h | 6 ++++++
2 files changed, 11 insertions(+)
diff --git a/src/mainboard/intel/mohonpeak/irqroute.h b/src/mainboard/intel/mohonpeak/irqroute.h
index 0e71a88..cbd320a 100644
--- a/src/mainboard/intel/mohonpeak/irqroute.h
+++ b/src/mainboard/intel/mohonpeak/irqroute.h
@@ -18,6 +18,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#ifndef IRQROUTE_H
+#define IRQROUTE_H
+
#include <southbridge/intel/fsp_rangeley/irq.h>
#include <southbridge/intel/fsp_rangeley/pci_devs.h>
@@ -66,3 +69,5 @@
PIRQ_PIC(F, 15), \
PIRQ_PIC(G, 14), \
PIRQ_PIC(H, 15)
+
+#endif /* IRQROUTE_H */
\ No newline at end of file
diff --git a/src/southbridge/intel/fsp_rangeley/acpi/irq_helper.h b/src/southbridge/intel/fsp_rangeley/acpi/irq_helper.h
index 4a298d3..49aca6e 100644
--- a/src/southbridge/intel/fsp_rangeley/acpi/irq_helper.h
+++ b/src/southbridge/intel/fsp_rangeley/acpi/irq_helper.h
@@ -19,6 +19,11 @@
*/
/*
+ * This file intentionally gets included multiple times, to set pic and apic
+ * modes, so should not have guard statements added.
+ */
+
+/*
* This file will use irqroute.asl and mainboard/irqroute.h
* to generate the ACPI IRQ routing for the mainboard being compiled.
* This method uses #defines in irqroute.h along with the macros contained
@@ -29,6 +34,7 @@
#undef PCI_DEV_PIRQ_ROUTE
#undef PIRQ_PIC_ROUTES
#undef PIRQ_PIC
+#undef IRQROUTE_H
#if defined(PIC_MODE)
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6604
-gerrit
commit c0836535a18b70c4d106738f283bc8637c2397ea
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Tue Aug 20 17:13:01 2013 -0700
exynos5420: Alter init sequence as per recommendation
As per hardware recommendation, CKE PAD retention release must
happen just before gate leveling enable and only in case of resume.
Hence, this patch moves pad retention release from dmc_common.c to
dmc_init_ddr3_exynos5420.c. In addition to this we are providing
125 (+3 extra being safe) times auto refresh to DRAM by sending
REFA direct command. This is required because when CKE PAD retention
release happens, self refresh mode of DDR3 is disabled.
Hence, auto refresh 125 times.
This is ported from https://gerrit.chromium.org/gerrit/#/c/65573
Note: Since WAKEUP_DIRECT does not go thru memory init, it should be
safe to move CKE PAD retention out of bootblock.c.
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Change-Id: Idec5d6fbbe3c6344d47401ba7203079c52a9b866
Reviewed-on: https://gerrit.chromium.org/gerrit/66788
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org>
(cherry picked from commit 96cbcb09245d4df92d3e1998704ab440be42df25)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/cpu/samsung/exynos5420/bootblock.c | 17 -------------
src/cpu/samsung/exynos5420/dmc_init_ddr3.c | 39 ++++++++++++++++++++++++++----
src/cpu/samsung/exynos5420/setup.h | 1 +
3 files changed, 35 insertions(+), 22 deletions(-)
diff --git a/src/cpu/samsung/exynos5420/bootblock.c b/src/cpu/samsung/exynos5420/bootblock.c
index 1ad75ef..2c42b03 100644
--- a/src/cpu/samsung/exynos5420/bootblock.c
+++ b/src/cpu/samsung/exynos5420/bootblock.c
@@ -31,23 +31,6 @@
void bootblock_cpu_init(void);
void bootblock_cpu_init(void)
{
- u32 ret;
- /*
- * During Suspend-Resume & S/W-Reset, as soon as PMU releases
- * pad retention, CKE goes high. This causes memory contents
- * not to be retained during DRAM initialization. Therfore,
- * there is a new control register(0x100431e8[28]) which lets us
- * release pad retention and retain the memory content until the
- * initialization is complete.
- */
- if (read32(((void *)INF_REG_BASE + INF_REG1_OFFSET)) == S5P_CHECK_SLEEP) {
- write32(PAD_RETENTION_DRAM_COREBLK_VAL,
- (void *)PAD_RETENTION_DRAM_COREBLK_OPTION);
- do {
- ret = read32((void *)PAD_RETENTION_DRAM_STATUS);
- } while (ret != 0x1);
- }
-
/* kick off the multi-core timer.
* We want to do this as early as we can.
*/
diff --git a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
index 6c431f3..0a4edc8 100644
--- a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
+++ b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
@@ -184,14 +184,43 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
writel(mem->timing_power, &drex0->timingpower);
writel(mem->timing_power, &drex1->timingpower);
- /* Send NOP, MRS and ZQINIT commands.
- * Sending MRS command will reset the DRAM. We should not be
- * reseting the DRAM after resume, this will lead to memory
- * corruption as DRAM content is lost after DRAM reset.
- */
if (reset) {
+ /* Send NOP, MRS and ZQINIT commands.
+ * Sending MRS command will reset the DRAM. We should not be
+ * reseting the DRAM after resume, this will lead to memory
+ * corruption as DRAM content is lost after DRAM reset.
+ */
dmc_config_mrs(mem, drex0);
dmc_config_mrs(mem, drex1);
+ } else {
+ u32 ret;
+
+ /*
+ * During Suspend-Resume & S/W-Reset, as soon as PMU releases
+ * pad retention, CKE goes high. This causes memory contents
+ * not to be retained during DRAM initialization. Therfore,
+ * there is a new control register(0x100431e8[28]) which lets us
+ * release pad retention and retain the memory content until the
+ * initialization is complete.
+ */
+ write32(PAD_RETENTION_DRAM_COREBLK_VAL,
+ (void *)PAD_RETENTION_DRAM_COREBLK_OPTION);
+ do {
+ ret = read32((void *)PAD_RETENTION_DRAM_STATUS);
+ } while (ret != 0x1);
+
+ /*
+ * CKE PAD retention disables DRAM self-refresh mode.
+ * Send auto refresh command for DRAM refresh.
+ */
+ for (i = 0; i < 128; i++) {
+ writel(DIRECT_CMD_REFA, &drex0->directcmd);
+ writel(DIRECT_CMD_REFA | (0x1 << DIRECT_CMD_CHIP_SHIFT),
+ &drex0->directcmd);
+ writel(DIRECT_CMD_REFA, &drex1->directcmd);
+ writel(DIRECT_CMD_REFA | (0x1 << DIRECT_CMD_CHIP_SHIFT),
+ &drex1->directcmd);
+ }
}
if (mem->gate_leveling_enable) {
diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h
index ca7281d..9dc49d8 100644
--- a/src/cpu/samsung/exynos5420/setup.h
+++ b/src/cpu/samsung/exynos5420/setup.h
@@ -715,6 +715,7 @@ struct exynos5_phy_control;
#define DIRECT_CMD_ZQINIT 0x0a000000
#define DIRECT_CMD_CHANNEL_SHIFT 28
#define DIRECT_CMD_CHIP_SHIFT 20
+#define DIRECT_CMD_BANK_SHIFT 16
#define DIRECT_CMD_REFA (5 << 24)
#define DIRECT_CMD_MRS1 0x71C00
#define DIRECT_CMD_MRS2 0x10BFC
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6530
-gerrit
commit 5b3c347af1851f1531b14c1d33fcc12d033c774c
Author: Julius Werner <jwerner(a)chromium.org>
Date: Wed Aug 21 17:33:31 2013 -0700
exynos5420: Make USB A-A booting work with early data cache
Apparently the IROM doesn't like data caches... the recently added
dcache-in-bootblock makes A-A booting fail, and flushes/invalidations
alone don't seem to fix it. It's pretty fast anyway, so we just disable
the cache again for the duration of the IROM call.
Also removes a superfluous invalidation line from the bootblock code...
dcache_mmu_enable/disable already take care of that.
Old-Change-Id: I35580d15664c7b4197d4ed14028720147adbf918
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66602
Reviewed-by: Gabe Black <gabeblack(a)chromium.org>
Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
(cherry picked from commit e9c28a6a7a88c8286e62764ee5ad2694da2e822f)
exynos5: Implement booting from SDMMC media
This patch augments the alternative CBFS media source implementation for
Exynos5250 and Exynos5420 to allow booting from SDMMC devices (such as
an SD or uSD card reader, if available). It also moves MMC
initialization for the Snow, Pit and Kirby boards from romstage to
ramstage (mainboard_init) to prevent it from interfering with the IROM
during SDMMC boot.
Old-Change-Id: Ic4adef80c28262d084a53c28ec59aa7ac3af50c8
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66154
(cherry picked from commit 08de13b72432c076e3327c048df93d89d52b0ecc)
snow and pit: turn on FET4 (for SD card) at bootup
Explictly enable FET4 on Snow and Pit.
Historically we haven't needed to do this because:
* On snow there's a bypass around FET4 which effectively eliminates
it. Even if we don't turn on FET4 the SD card is still powered.
Turning on FET4 doesn't hurt though and is technically correct.
* On pit the EC turns on FET4 on cold bootup.
On pit we run into a problem if the kernel turns off FET4 like in
<https://gerrit.chromium.org/gerrit/#/c/65332/> and then we get a
software reset or warm reset. In this case the EC won't know to turn
it back on.
This was ported from: https://gerrit.chromium.org/gerrit/#/c/65673
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Old-Change-Id: I57337f12b38889e6afee8577cf8807ec4c41e91c
Reviewed-on: https://gerrit.chromium.org/gerrit/66786
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org>
(cherry picked from commit e910117047d898b6b1d0dc965ef2ec0237d17646)
Squashed three commits for alternate cbfs SD support.
Change-Id: Idbd1fd4776cbf8cb20d03e6b691104cd8540a1ec
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/cpu/samsung/exynos5250/alternate_cbfs.c | 72 ++++++++++++++++++++++++--
src/cpu/samsung/exynos5250/alternate_cbfs.h | 6 +++
src/cpu/samsung/exynos5250/power.h | 3 +-
src/cpu/samsung/exynos5420/alternate_cbfs.c | 79 +++++++++++++++++++++++++++--
src/cpu/samsung/exynos5420/alternate_cbfs.h | 6 +++
src/cpu/samsung/exynos5420/bootblock.c | 1 -
src/cpu/samsung/exynos5420/power.h | 3 +-
src/mainboard/google/pit/mainboard.c | 22 ++++++++
src/mainboard/google/pit/romstage.c | 15 ------
src/mainboard/google/snow/mainboard.c | 30 +++++++++++
src/mainboard/google/snow/romstage.c | 19 -------
11 files changed, 209 insertions(+), 47 deletions(-)
diff --git a/src/cpu/samsung/exynos5250/alternate_cbfs.c b/src/cpu/samsung/exynos5250/alternate_cbfs.c
index 49c9d4c..59843fb 100644
--- a/src/cpu/samsung/exynos5250/alternate_cbfs.c
+++ b/src/cpu/samsung/exynos5250/alternate_cbfs.c
@@ -24,6 +24,8 @@
#include <string.h>
#include <console/console.h>
#include "alternate_cbfs.h"
+#include "cpu.h"
+#include "power.h"
#include "spi.h"
/* This allows USB A-A firmware upload from a compatible host in four parts:
@@ -53,7 +55,7 @@ static int usb_cbfs_open(struct cbfs_media *media)
return 0;
if (!irom_load_usb()) {
- printk(BIOS_ERR, "Unable to load CBFS image via USB!\n");
+ printk(BIOS_EMERG, "Unable to load CBFS image via USB!\n");
return -1;
}
@@ -70,6 +72,45 @@ static int usb_cbfs_open(struct cbfs_media *media)
return 0;
}
+/*
+ * SDMMC works very similar to USB A-A: we copy the CBFS image into memory
+ * and read it from there. While SDMMC would also allow direct block by block
+ * on-demand reading, we might run into problems if we call back into the IROM
+ * in very late boot stages (e.g. after initializing/changing MMC clocks)... so
+ * this seems like a safer approach. It also makes it easy to pass our image
+ * down to payloads.
+ */
+static int sdmmc_cbfs_open(struct cbfs_media *media)
+{
+#ifdef __PRE_RAM__
+ /*
+ * In the bootblock, we just copy the small part that fits in the buffer
+ * and hope that it's enough (since the romstage is currently always the
+ * first component in the image, this should work out). In the romstage,
+ * we copy until our buffer is full (currently 12M) to avoid the pain of
+ * figuring out the true image size from in here. Since this is mainly a
+ * developer/debug boot mode, those shortcomings should be bearable.
+ */
+ const u32 count = alternate_cbfs_size / 512;
+ static int first_run = 1;
+ int (*irom_load_sdmmc)(u32 start, u32 count, void *dst) =
+ *irom_sdmmc_read_blocks_ptr;
+
+ if (!first_run)
+ return 0;
+
+ if (!irom_load_sdmmc(1, count, alternate_cbfs_buffer)) {
+ printk(BIOS_EMERG, "Unable to load CBFS image from SDMMC!\n");
+ return -1;
+ }
+
+ printk(BIOS_DEBUG, "SDMMC read successful, CBFS image should now be"
+ " at %p\n", alternate_cbfs_buffer);
+ first_run = 0;
+#endif
+ return 0;
+}
+
static int alternate_cbfs_close(struct cbfs_media *media) { return 0; }
static size_t alternate_cbfs_read(struct cbfs_media *media, void *dest,
@@ -90,6 +131,19 @@ static void *alternate_cbfs_map(struct cbfs_media *media, size_t offset,
static void *alternate_cbfs_unmap(struct cbfs_media *media,
const void *buffer) { return 0; }
+static int initialize_exynos_sdmmc_cbfs_media(struct cbfs_media *media)
+{
+ printk(BIOS_DEBUG, "Using Exynos alternate boot mode SDMMC\n");
+
+ media->open = sdmmc_cbfs_open;
+ media->close = alternate_cbfs_close;
+ media->read = alternate_cbfs_read;
+ media->map = alternate_cbfs_map;
+ media->unmap = alternate_cbfs_unmap;
+
+ return 0;
+}
+
static int initialize_exynos_usb_cbfs_media(struct cbfs_media *media)
{
printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n");
@@ -108,8 +162,16 @@ int init_default_cbfs_media(struct cbfs_media *media)
if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB)
return initialize_exynos_usb_cbfs_media(media);
- /* TODO: implement SDMMC (and possibly other) boot mode */
-
- return initialize_exynos_spi_cbfs_media(media,
- (void*)CONFIG_CBFS_CACHE_ADDRESS, CONFIG_CBFS_CACHE_SIZE);
+ switch (samsung_get_base_power()->om_stat & OM_STAT_MASK) {
+ case OM_STAT_SDMMC:
+ return initialize_exynos_sdmmc_cbfs_media(media);
+ case OM_STAT_SPI:
+ return initialize_exynos_spi_cbfs_media(media,
+ (void*)CONFIG_CBFS_CACHE_ADDRESS,
+ CONFIG_CBFS_CACHE_SIZE);
+ default:
+ printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n",
+ samsung_get_base_power()->om_stat);
+ return 0;
+ }
}
diff --git a/src/cpu/samsung/exynos5250/alternate_cbfs.h b/src/cpu/samsung/exynos5250/alternate_cbfs.h
index a26fe61..8a87279 100644
--- a/src/cpu/samsung/exynos5250/alternate_cbfs.h
+++ b/src/cpu/samsung/exynos5250/alternate_cbfs.h
@@ -30,6 +30,12 @@ void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070;
#define SECONDARY_BASE_BOOT_USB 0xfeed0002
u32 * const iram_secondary_base = (u32 *)0x02020018;
+/* Values pulled from U-Boot, I think the manual is wrong here (for SPI) */
+#define OM_STAT_SDMMC 0x4
+#define OM_STAT_EMMC 0x8
+#define OM_STAT_SPI 0x14
+#define OM_STAT_MASK 0x7f
+
#if defined(__BOOT_BLOCK__)
/* A small space in IRAM to hold the romstage-only image */
void * const alternate_cbfs_buffer = (void *)CONFIG_CBFS_CACHE_ADDRESS;
diff --git a/src/cpu/samsung/exynos5250/power.h b/src/cpu/samsung/exynos5250/power.h
index f349e53..5483d92 100644
--- a/src/cpu/samsung/exynos5250/power.h
+++ b/src/cpu/samsung/exynos5250/power.h
@@ -42,7 +42,8 @@ void power_enable_hw_thermal_trip(void);
/* Power Management Unit register map */
struct exynos5_power {
/* Add registers as and when required */
- uint8_t reserved1[0x0400];
+ uint32_t om_stat; /* 0x0000 */
+ uint8_t reserved1[0x03fc];
uint32_t sw_reset; /* 0x0400 */
uint8_t reserved2[0x0304];
uint32_t usb_host_phy_ctrl; /* 0x0708 */
diff --git a/src/cpu/samsung/exynos5420/alternate_cbfs.c b/src/cpu/samsung/exynos5420/alternate_cbfs.c
index 49c9d4c..4161303 100644
--- a/src/cpu/samsung/exynos5420/alternate_cbfs.c
+++ b/src/cpu/samsung/exynos5420/alternate_cbfs.c
@@ -22,8 +22,11 @@
#include <cbfs.h> /* This driver serves as a CBFS media source. */
#include <stdlib.h>
#include <string.h>
+#include <arch/cache.h>
#include <console/console.h>
#include "alternate_cbfs.h"
+#include "cpu.h"
+#include "power.h"
#include "spi.h"
/* This allows USB A-A firmware upload from a compatible host in four parts:
@@ -52,10 +55,13 @@ static int usb_cbfs_open(struct cbfs_media *media)
if (!first_run)
return 0;
+ dcache_mmu_disable();
if (!irom_load_usb()) {
- printk(BIOS_ERR, "Unable to load CBFS image via USB!\n");
+ dcache_mmu_enable();
+ printk(BIOS_EMERG, "Unable to load CBFS image via USB!\n");
return -1;
}
+ dcache_mmu_enable();
/*
* We need to trust the host/irom to copy the image to our
@@ -70,6 +76,48 @@ static int usb_cbfs_open(struct cbfs_media *media)
return 0;
}
+/*
+ * SDMMC works very similar to USB A-A: we copy the CBFS image into memory
+ * and read it from there. While SDMMC would also allow direct block by block
+ * on-demand reading, we might run into problems if we call back into the IROM
+ * in very late boot stages (e.g. after initializing/changing MMC clocks)... so
+ * this seems like a safer approach. It also makes it easy to pass our image
+ * down to payloads.
+ */
+static int sdmmc_cbfs_open(struct cbfs_media *media)
+{
+#ifdef __PRE_RAM__
+ /*
+ * In the bootblock, we just copy the small part that fits in the buffer
+ * and hope that it's enough (since the romstage is currently always the
+ * first component in the image, this should work out). In the romstage,
+ * we copy until our buffer is full (currently 12M) to avoid the pain of
+ * figuring out the true image size from in here. Since this is mainly a
+ * developer/debug boot mode, those shortcomings should be bearable.
+ */
+ const u32 count = alternate_cbfs_size / 512;
+ static int first_run = 1;
+ int (*irom_load_sdmmc)(u32 start, u32 count, void *dst) =
+ *irom_sdmmc_read_blocks_ptr;
+
+ if (!first_run)
+ return 0;
+
+ dcache_mmu_disable();
+ if (!irom_load_sdmmc(1, count, alternate_cbfs_buffer)) {
+ dcache_mmu_enable();
+ printk(BIOS_EMERG, "Unable to load CBFS image from SDMMC!\n");
+ return -1;
+ }
+ dcache_mmu_enable();
+
+ printk(BIOS_DEBUG, "SDMMC read successful, CBFS image should now be"
+ " at %p\n", alternate_cbfs_buffer);
+ first_run = 0;
+#endif
+ return 0;
+}
+
static int alternate_cbfs_close(struct cbfs_media *media) { return 0; }
static size_t alternate_cbfs_read(struct cbfs_media *media, void *dest,
@@ -90,6 +138,19 @@ static void *alternate_cbfs_map(struct cbfs_media *media, size_t offset,
static void *alternate_cbfs_unmap(struct cbfs_media *media,
const void *buffer) { return 0; }
+static int initialize_exynos_sdmmc_cbfs_media(struct cbfs_media *media)
+{
+ printk(BIOS_DEBUG, "Using Exynos alternate boot mode SDMMC\n");
+
+ media->open = sdmmc_cbfs_open;
+ media->close = alternate_cbfs_close;
+ media->read = alternate_cbfs_read;
+ media->map = alternate_cbfs_map;
+ media->unmap = alternate_cbfs_unmap;
+
+ return 0;
+}
+
static int initialize_exynos_usb_cbfs_media(struct cbfs_media *media)
{
printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n");
@@ -108,8 +169,16 @@ int init_default_cbfs_media(struct cbfs_media *media)
if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB)
return initialize_exynos_usb_cbfs_media(media);
- /* TODO: implement SDMMC (and possibly other) boot mode */
-
- return initialize_exynos_spi_cbfs_media(media,
- (void*)CONFIG_CBFS_CACHE_ADDRESS, CONFIG_CBFS_CACHE_SIZE);
+ switch (samsung_get_base_power()->om_stat & OM_STAT_MASK) {
+ case OM_STAT_SDMMC:
+ return initialize_exynos_sdmmc_cbfs_media(media);
+ case OM_STAT_SPI:
+ return initialize_exynos_spi_cbfs_media(media,
+ (void*)CONFIG_CBFS_CACHE_ADDRESS,
+ CONFIG_CBFS_CACHE_SIZE);
+ default:
+ printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n",
+ samsung_get_base_power()->om_stat);
+ return 0;
+ }
}
diff --git a/src/cpu/samsung/exynos5420/alternate_cbfs.h b/src/cpu/samsung/exynos5420/alternate_cbfs.h
index 4e9dff9..3bb9c76 100644
--- a/src/cpu/samsung/exynos5420/alternate_cbfs.h
+++ b/src/cpu/samsung/exynos5420/alternate_cbfs.h
@@ -30,6 +30,12 @@ void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070;
#define SECONDARY_BASE_BOOT_USB 0xfeed0002
u32 * const iram_secondary_base = (u32 *)0x02020018;
+/* Values pulled from U-Boot, I think the manual is wrong here (for SPI) */
+#define OM_STAT_SDMMC 0x4
+#define OM_STAT_EMMC 0x8
+#define OM_STAT_SPI 0x14
+#define OM_STAT_MASK 0x7f
+
#if defined(__BOOT_BLOCK__)
/* A small space in IRAM to hold the romstage-only image */
void * const alternate_cbfs_buffer = (void *)CONFIG_CBFS_CACHE_ADDRESS;
diff --git a/src/cpu/samsung/exynos5420/bootblock.c b/src/cpu/samsung/exynos5420/bootblock.c
index 3df51a7..1ad75ef 100644
--- a/src/cpu/samsung/exynos5420/bootblock.c
+++ b/src/cpu/samsung/exynos5420/bootblock.c
@@ -63,7 +63,6 @@ void bootblock_cpu_init(void)
mmu_config_range(0, SRAM_START, DCACHE_OFF);
mmu_config_range(SRAM_START, SRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range(SRAM_END, 4096 - SRAM_END, DCACHE_OFF);
- dcache_invalidate_all();
dcache_mmu_enable();
/* For most ARM systems, we have to initialize firmware media source
diff --git a/src/cpu/samsung/exynos5420/power.h b/src/cpu/samsung/exynos5420/power.h
index 665e94c..4efc84e 100644
--- a/src/cpu/samsung/exynos5420/power.h
+++ b/src/cpu/samsung/exynos5420/power.h
@@ -42,7 +42,8 @@ void power_enable_hw_thermal_trip(void);
/* Power Management Unit register map */
struct exynos5_power {
/* Add registers as and when required */
- uint8_t reserved1[0x0400];
+ uint32_t om_stat; /* 0x0000 */
+ uint8_t reserved1[0x03fc];
uint32_t sw_reset; /* 0x0400 */
uint8_t reserved2[0x0304];
uint32_t usb_host_phy_ctrl; /* 0x0708 */
diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c
index 3ffb824..9aa8d5c 100644
--- a/src/mainboard/google/pit/mainboard.c
+++ b/src/mainboard/google/pit/mainboard.c
@@ -330,6 +330,19 @@ static void disable_usb30_pll(void)
gpio_direction_output(usb3_pll_l, 0);
}
+static void setup_storage(void)
+{
+ /* MMC0: Fixed, 8 bit mode, connected with GPIO. */
+ if (clock_set_dwmci(PERIPH_ID_SDMMC0))
+ printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__);
+ exynos_pinmux_sdmmc0();
+
+ /* MMC2: Removable, 4 bit mode, no GPIO. */
+ /* (Must be after romstage to avoid breaking SDMMC boot.) */
+ clock_set_dwmci(PERIPH_ID_SDMMC2);
+ exynos_pinmux_sdmmc2();
+}
+
static void gpio_init(void)
{
/* Set up the I2C busses. */
@@ -370,6 +383,12 @@ static void backlight_vdd(void)
tps65090_thru_ec_fet_set(1);
}
+static void sdmmc_vdd(void)
+{
+ /* Enable FET4, P3.3V_SDCARD */
+ tps65090_thru_ec_fet_set(4);
+}
+
/* this happens after cpu_init where exynos resources are set */
static void mainboard_init(device_t dev)
{
@@ -380,6 +399,7 @@ static void mainboard_init(device_t dev)
void *fb_addr = (void *)(get_fb_base_kb() * KiB);
gpio_init();
+ setup_storage();
tmu_init(&exynos5420_tmu_info);
/* Clock Gating all the unused IP's to save power */
@@ -388,6 +408,8 @@ static void mainboard_init(device_t dev)
/* Disable USB3.0 PLL to save 250mW of power */
disable_usb30_pll();
+ sdmmc_vdd();
+
set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr);
/*
diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c
index 319ebf9..7967a55 100644
--- a/src/mainboard/google/pit/romstage.c
+++ b/src/mainboard/google/pit/romstage.c
@@ -40,8 +40,6 @@
#include <drivers/maxim/max77802/max77802.h>
#include <device/i2c.h>
-#define MMC0_GPIO_PIN (58)
-
#define PMIC_I2C_BUS 4
struct pmic_write
@@ -109,18 +107,6 @@ static int setup_power(int is_resume)
return error;
}
-static void setup_storage(void)
-{
- /* MMC0: Fixed, 8 bit mode, connected with GPIO. */
- if (clock_set_dwmci(PERIPH_ID_SDMMC0))
- printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__);
- exynos_pinmux_sdmmc0();
-
- /* MMC2: Removable, 4 bit mode, no GPIO. */
- clock_set_dwmci(PERIPH_ID_SDMMC2);
- exynos_pinmux_sdmmc2();
-}
-
static void setup_ec(void)
{
/* SPI2 (EC) is slower and needs to work in half-duplex mode with
@@ -270,7 +256,6 @@ void main(void)
wakeup();
}
- setup_storage();
setup_gpio();
setup_ec();
diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c
index 23b7072..9fc2fe6 100644
--- a/src/mainboard/google/snow/mainboard.c
+++ b/src/mainboard/google/snow/mainboard.c
@@ -38,6 +38,8 @@
#include "exynos5250.h"
+#define MMC0_GPIO_PIN (58)
+
/* convenient shorthand (in MB) */
#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
@@ -132,6 +134,7 @@ static void backlight_en(void)
#define TPS65090_BUS 4 /* Snow-specific */
#define FET1_CTRL 0x0f
+#define FET4_CTRL 0x12
#define FET6_CTRL 0x14
static void lcd_vdd(void)
@@ -147,6 +150,12 @@ static void backlight_vdd(void)
udelay(LCD_T5_DELAY_MS * 1000);
}
+static void sdmmc_vdd(void)
+{
+ /* Enable FET4, P3.3V_SDCARD */
+ tps65090_fet_enable(TPS65090_BUS, FET4_CTRL);
+}
+
//static struct video_info smdk5250_dp_config = {
static struct video_info dp_video_info = {
/* FIXME: fix video_info struct to use const for name */
@@ -179,6 +188,24 @@ static void disable_usb30_pll(void)
gpio_direction_output(usb3_pll_l, 0);
}
+static void setup_storage(void)
+{
+ /* MMC0: Fixed, 8 bit mode, connected with GPIO. */
+ if (clock_set_mshci(PERIPH_ID_SDMMC0))
+ printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__);
+ if (gpio_direction_output(MMC0_GPIO_PIN, 1)) {
+ printk(BIOS_CRIT, "%s: Unable to power on MMC0.\n", __func__);
+ }
+ gpio_set_pull(MMC0_GPIO_PIN, GPIO_PULL_NONE);
+ gpio_set_drv(MMC0_GPIO_PIN, GPIO_DRV_4X);
+ exynos_pinmux_sdmmc0();
+
+ /* MMC2: Removable, 4 bit mode, no GPIO. */
+ /* (Must be after romstage to avoid breaking SDMMC boot.) */
+ clock_set_mshci(PERIPH_ID_SDMMC2);
+ exynos_pinmux_sdmmc2();
+}
+
static void gpio_init(void)
{
/* Set up the I2C busses. */
@@ -217,6 +244,7 @@ static void mainboard_init(device_t dev)
void *fb_addr = (void *)(get_fb_base_kb() * KiB);
gpio_init();
+ setup_storage();
i2c_init(TPS65090_BUS, I2C_0_SPEED, I2C_SLAVE);
i2c_init(7, I2C_0_SPEED, I2C_SLAVE);
@@ -229,6 +257,8 @@ static void mainboard_init(device_t dev)
/* Disable USB3.0 PLL to save 250mW of power */
disable_usb30_pll();
+ sdmmc_vdd();
+
set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr);
lcd_vdd();
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index 3a8b5e8..44074c5 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -42,7 +42,6 @@
#include "exynos5250.h"
#define PMIC_BUS 0
-#define MMC0_GPIO_PIN (58)
static void setup_power(int is_resume)
{
@@ -96,23 +95,6 @@ static void setup_power(int is_resume)
}
}
-static void setup_storage(void)
-{
- /* MMC0: Fixed, 8 bit mode, connected with GPIO. */
- if (clock_set_mshci(PERIPH_ID_SDMMC0))
- printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__);
- if (gpio_direction_output(MMC0_GPIO_PIN, 1)) {
- printk(BIOS_CRIT, "%s: Unable to power on MMC0.\n", __func__);
- }
- gpio_set_pull(MMC0_GPIO_PIN, GPIO_PULL_NONE);
- gpio_set_drv(MMC0_GPIO_PIN, GPIO_DRV_4X);
- exynos_pinmux_sdmmc0();
-
- /* MMC2: Removable, 4 bit mode, no GPIO. */
- clock_set_mshci(PERIPH_ID_SDMMC2);
- exynos_pinmux_sdmmc2();
-}
-
static void setup_graphics(void)
{
exynos_pinmux_dphpd();
@@ -176,7 +158,6 @@ void main(void)
wakeup();
}
- setup_storage();
setup_gpio();
setup_graphics();
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6602
-gerrit
commit 7d17f640e7f46afdc35bd5429bb82fa0d7361b38
Author: Furquan Shaikh <furquan(a)google.com>
Date: Tue Aug 6 13:48:12 2013 -0700
Falco: Patch to enable correct port clock selection for dp
This is required only for haswell since the register configs have changed.
Also, created mainboard specific header file
Original-Change-Id: I61bf8d7cef1f204735a2f72225c48d6e44a99945
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Conflicts:
src/mainboard/google/slippy/gma.c
src/mainboard/google/slippy/i915io.c
Conflicts:
src/mainboard/google/slippy/gma.c
Change-Id: I77f2542ca8228358f59aafd99c0d13168ab47fb5
Reviewed-on: https://gerrit.chromium.org/gerrit/66853
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Commit-Queue: Furquan Shaikh <furquan(a)chromium.org>
Tested-by: Furquan Shaikh <furquan(a)chromium.org>
(cherry picked from commit 77f9d1ddd4376e2a290d466f0669a43997492c8e)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/mainboard/google/slippy/gma.c | 25 ++++++++++++++++++++++++-
src/mainboard/google/slippy/i915io.c | 5 ++---
src/mainboard/google/slippy/mainboard.h | 25 +++++++++++++++++++++++++
3 files changed, 51 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c
index 7c95e40..839fa4d 100644
--- a/src/mainboard/google/slippy/gma.c
+++ b/src/mainboard/google/slippy/gma.c
@@ -43,6 +43,7 @@
#include <cpu/x86/msr.h>
#include <edid.h>
#include <drivers/intel/gma/i915.h>
+#include "mainboard.h"
/*
* Here is the rough outline of how we bring up the display:
@@ -228,7 +229,6 @@ int intel_dp_bw_code_to_link_rate(u8 link_bw)
}
}
-void mainboard_train_link(struct intel_dp *intel_dp);
void mainboard_train_link(struct intel_dp *intel_dp)
{
u8 read_val;
@@ -281,6 +281,29 @@ static void test_gfx(struct intel_dp *dp)
static void test_gfx(struct intel_dp *dp) {}
#endif
+
+void mainboard_set_port_clk_dp(struct intel_dp *intel_dp)
+{
+ u32 ddi_pll_sel = 0;
+
+ switch (intel_dp->link_bw) {
+ case DP_LINK_BW_1_62:
+ ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
+ break;
+ case DP_LINK_BW_2_7:
+ ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
+ break;
+ case DP_LINK_BW_5_4:
+ ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
+ break;
+ default:
+ printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw);
+ return;
+ }
+
+ gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel);
+}
+
int i915lightup(unsigned int pphysbase, unsigned int pmmio,
unsigned int pgfx, unsigned int init_fb)
{
diff --git a/src/mainboard/google/slippy/i915io.c b/src/mainboard/google/slippy/i915io.c
index 7fbffb6..aae7f29 100644
--- a/src/mainboard/google/slippy/i915io.c
+++ b/src/mainboard/google/slippy/i915io.c
@@ -26,6 +26,7 @@
#include <delay.h>
#include <drivers/intel/gma/i915.h>
#include <arch/io.h>
+#include "mainboard.h"
/* these variables will be removed when the proper support is finished in src/drivers/intel/gma/intel_dp.c */
int index;
@@ -33,8 +34,6 @@ u32 auxout;
u8 auxin[20];
u8 msg[32];
-extern void mainboard_train_link(struct intel_dp *intel_dp);
-
/* this function will either be renamed or subsumed into ./gma.c:i915_lightup */
void runio(struct intel_dp *dp);
@@ -71,7 +70,7 @@ void runio(struct intel_dp *dp)
gtt_write(PIPECONF(dp->transcoder),0x00000000);
gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000);
- gtt_write(PORT_CLK_SEL(dp->port),PORT_CLK_SEL_LCPLL_1350);
+ mainboard_set_port_clk_dp(dp);
gtt_write(DSPSTRIDE(dp->plane),dp->stride);
gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_RGBX888);
gtt_write(DEIIR,0x00000080);
diff --git a/src/mainboard/google/slippy/mainboard.h b/src/mainboard/google/slippy/mainboard.h
new file mode 100644
index 0000000..f47fffd
--- /dev/null
+++ b/src/mainboard/google/slippy/mainboard.h
@@ -0,0 +1,25 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright 2013 Google Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; version 2 of the License.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef __MAINBOARD_H_
+#define __MAINBOARD_H_
+void mainboard_train_link(struct intel_dp *intel_dp);
+void mainboard_set_port_clk_dp(struct intel_dp *intel_dp);
+
+#endif
the following patch was just integrated into master:
commit 3ab015cddd49475df4509c99564236f828af7027
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Thu Jun 12 12:08:26 2014 -0600
bayleybay_fsp: Add bakersport board variant
The Bakersport board is a variant of the Bayley Bay mainboard that uses
one ECC DIMM instead of two non-ECC dimms.
This commit uses the Bayley Bay mainboard directory and modifies the
required pieces to add the Bakersport board variant. It disables the
second DIMM, points to an ECC version of the FSP, and sets the board
name to be Bakersport instead of Bayley Bay.
All of the code is still contained in the bayleybay_fsp directory. It
seems like duplicating the whole directory for the one line of code
that's actually different between the two platforms.
Change-Id: Ia31e9ee927a6810a01a1ae143fcb00cfb7d8a7aa
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/5983
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
See http://review.coreboot.org/5983 for details.
-gerrit