the following patch was just integrated into master:
commit 9944b28cc478914233d9e555df6b9ab0cc46d097
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Mon Aug 11 11:24:55 2014 -0600
cpu/intel/XXX/acpi.c: Fix coding style violation
Clean up a coding style violation as requested in the review of
commit 09670265.
Change-Id: I2815635efbb70a1e5841ca79cf2b4845bc6c23f2
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6598
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/6598 for details.
-gerrit
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6613
-gerrit
commit 9cb9c47b271e6833ff548c9729f39367c8bad7c7
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Thu Aug 29 14:05:21 2013 -0700
exynos5420/pit/kirby: re-factor membaseconfig0/1 usage
membaseconfig0/1 are utterly dependent on the mainboard's particular
DRAM setup. This defines their values in the mem_timings struct for
pit and kirby.
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Old-Change-Id: Ifd782d1229b2418f8ddbf0bcb3f45cc828ac34b0
Reviewed-on: https://chromium-review.googlesource.com/167488
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-by: ron minnich <rminnich(a)chromium.org>
(cherry picked from commit 80eebd5bc0dbb9fabf81f46c25dcd5c5d5747579)
exynos5420: necessary updates for DRAM
This updates DRAM usage for Exynos5420 so that we can actually
use 3.5GB:
- Memory chips used with Exynos5420 may have 16 row address lines.
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Old-Change-Id: I86d1a96d0d1a028587f7655f8de5a2e52165e9d2
Reviewed-on: https://chromium-review.googlesource.com/167489
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-by: ron minnich <rminnich(a)chromium.org>
(cherry picked from commit 04bbaf5d8e125166dd689f656d5b37776be01fb1)
Squashed two related commits.
Change-Id: I4e45bc8a446715897ec21b0160701152fa6b226b
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/cpu/samsung/exynos5420/dmc_init_ddr3.c | 24 +++++++++---------------
src/cpu/samsung/exynos5420/setup.h | 16 +++++++---------
src/mainboard/google/pit/memory.c | 7 +++++++
3 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
index 1126dca..1d7b8a8 100644
--- a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
+++ b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
@@ -145,21 +145,15 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
update_reset_dll(drex0, DDR_MODE_DDR3);
update_reset_dll(drex1, DDR_MODE_DDR3);
- /* Set Base Address:
- * 0x2000_0000 ~ 0x5FFF_FFFF
- * 0x6000_0000 ~ 0x9FFF_FFFF
- */
- /* MEMBASECONFIG0 */
- val = DMC_MEMBASECONFIGx_CHIP_BASE(DMC_CHIP_BASE_0) |
- DMC_MEMBASECONFIGx_CHIP_MASK(DMC_CHIP_MASK);
- writel(val, &tzasc0->membaseconfig0);
- writel(val, &tzasc1->membaseconfig0);
-
- /* MEMBASECONFIG1 */
- val = DMC_MEMBASECONFIGx_CHIP_BASE(DMC_CHIP_BASE_1) |
- DMC_MEMBASECONFIGx_CHIP_MASK(DMC_CHIP_MASK);
- writel(val, &tzasc0->membaseconfig1);
- writel(val, &tzasc1->membaseconfig1);
+ /* MEMBASECONFIG0 (CS0) */
+ writel(mem->membaseconfig0, &tzasc0->membaseconfig0);
+ writel(mem->membaseconfig0, &tzasc1->membaseconfig0);
+
+ /* MEMBASECONFIG1 (CS1) */
+ if (mem->chips_per_channel == 2) {
+ writel(mem->membaseconfig1, &tzasc0->membaseconfig1);
+ writel(mem->membaseconfig1, &tzasc1->membaseconfig1);
+ }
/* Memory Channel Inteleaving Size
* Exynos5420 Channel interleaving = 128 bytes
diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h
index 3bd36b2..950c2c6 100644
--- a/src/cpu/samsung/exynos5420/setup.h
+++ b/src/cpu/samsung/exynos5420/setup.h
@@ -136,6 +136,7 @@ struct exynos5_phy_control;
#define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8)
#define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4)
#define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4)
+#define DMC_MEMCONFIGx_CHIP_ROW_16 (4 << 4)
#define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0)
#define DMC_MEMBASECONFIGx_CHIP_BASE(x) (x << 16)
@@ -767,15 +768,12 @@ struct exynos5_phy_control;
#define DPWRDN_EN (1 << 1)
#define DSREF_EN (1 << 5)
-/* As we use channel interleaving, therefore value of the base address
- * register must be set as half of the bus base address
- * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
- * we need to set half 0x10 to the membaseconfigx registers
- * see exynos5420 UM section 17.17.3.21 for more
- */
-#define DMC_CHIP_BASE_0 0x10
-#define DMC_CHIP_BASE_1 0x50
-#define DMC_CHIP_MASK 0x7C0
+/* AXI base address mask */
+#define DMC_CHIP_MASK_256MB 0x7f0
+#define DMC_CHIP_MASK_512MB 0x7e0
+#define DMC_CHIP_MASK_1GB 0x7c0
+#define DMC_CHIP_MASK_2GB 0x780
+#define DMC_CHIP_MASK_4GB 0x700
#define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0
#define MEMBASECONFIG_CHIP_MASK_OFFSET 0
diff --git a/src/mainboard/google/pit/memory.c b/src/mainboard/google/pit/memory.c
index 4ac3d0c..0c30773 100644
--- a/src/mainboard/google/pit/memory.c
+++ b/src/mainboard/google/pit/memory.c
@@ -90,6 +90,13 @@ const struct mem_timings mem_timings = {
DMC_MEMCONTROL_BL_8 |
DMC_MEMCONTROL_PZQ_DISABLE |
DMC_MEMCONTROL_MRR_BYTE_7_0,
+ /*
+ * For channel interleaving, the chip_base needs to be set to
+ * half the bus address. So for a base address of 0x2000_0000,
+ * the chip_base value is 0x20 without interleaving and 0x10
+ * with channel interleaving. See note in section 17.14.
+ */
+ .membaseconfig0 = (0x10 << 16) | DMC_CHIP_MASK_1GB,
.memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
DMC_MEMCONFIGx_CHIP_COL_10 |
DMC_MEMCONFIGx_CHIP_ROW_15 |
the following patch was just integrated into master:
commit 6481e1052fa88a4dcfb7220775ff67ecd3c70384
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sun Aug 10 23:48:11 2014 +0200
gm45: Ensure that brightness register in gma contains sane value.
Change-Id: Ia66c71c3adf2ae0d413750b5e59e3eaba3888a0b
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6587
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/6587 for details.
-gerrit
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6530
-gerrit
commit dfab483320e8c4fbd08f9d939527fdfc471ed5da
Author: Julius Werner <jwerner(a)chromium.org>
Date: Wed Aug 21 17:33:31 2013 -0700
exynos5420: Make USB A-A booting work with early data cache
Apparently the IROM doesn't like data caches... the recently added
dcache-in-bootblock makes A-A booting fail, and flushes/invalidations
alone don't seem to fix it. It's pretty fast anyway, so we just disable
the cache again for the duration of the IROM call.
Also removes a superfluous invalidation line from the bootblock code...
dcache_mmu_enable/disable already take care of that.
Old-Change-Id: I35580d15664c7b4197d4ed14028720147adbf918
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66602
Reviewed-by: Gabe Black <gabeblack(a)chromium.org>
Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
(cherry picked from commit e9c28a6a7a88c8286e62764ee5ad2694da2e822f)
exynos5: Implement booting from SDMMC media
This patch augments the alternative CBFS media source implementation for
Exynos5250 and Exynos5420 to allow booting from SDMMC devices (such as
an SD or uSD card reader, if available). It also moves MMC
initialization for the Snow, Pit and Kirby boards from romstage to
ramstage (mainboard_init) to prevent it from interfering with the IROM
during SDMMC boot.
Old-Change-Id: Ic4adef80c28262d084a53c28ec59aa7ac3af50c8
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66154
(cherry picked from commit 08de13b72432c076e3327c048df93d89d52b0ecc)
snow and pit: turn on FET4 (for SD card) at bootup
Explictly enable FET4 on Snow and Pit.
Historically we haven't needed to do this because:
* On snow there's a bypass around FET4 which effectively eliminates
it. Even if we don't turn on FET4 the SD card is still powered.
Turning on FET4 doesn't hurt though and is technically correct.
* On pit the EC turns on FET4 on cold bootup.
On pit we run into a problem if the kernel turns off FET4 like in
<https://gerrit.chromium.org/gerrit/#/c/65332/> and then we get a
software reset or warm reset. In this case the EC won't know to turn
it back on.
This was ported from: https://gerrit.chromium.org/gerrit/#/c/65673
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Old-Change-Id: I57337f12b38889e6afee8577cf8807ec4c41e91c
Reviewed-on: https://gerrit.chromium.org/gerrit/66786
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org>
(cherry picked from commit e910117047d898b6b1d0dc965ef2ec0237d17646)
Squashed three commits for alternate cbfs SD support.
Change-Id: Idbd1fd4776cbf8cb20d03e6b691104cd8540a1ec
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/cpu/samsung/exynos5250/alternate_cbfs.c | 72 ++++++++++++++++++++++++--
src/cpu/samsung/exynos5250/alternate_cbfs.h | 6 +++
src/cpu/samsung/exynos5250/power.h | 3 +-
src/cpu/samsung/exynos5420/alternate_cbfs.c | 79 +++++++++++++++++++++++++++--
src/cpu/samsung/exynos5420/alternate_cbfs.h | 6 +++
src/cpu/samsung/exynos5420/bootblock.c | 1 -
src/cpu/samsung/exynos5420/power.h | 3 +-
src/mainboard/google/pit/mainboard.c | 22 ++++++++
src/mainboard/google/pit/romstage.c | 15 ------
src/mainboard/google/snow/mainboard.c | 30 +++++++++++
src/mainboard/google/snow/romstage.c | 19 -------
11 files changed, 209 insertions(+), 47 deletions(-)
diff --git a/src/cpu/samsung/exynos5250/alternate_cbfs.c b/src/cpu/samsung/exynos5250/alternate_cbfs.c
index 49c9d4c..59843fb 100644
--- a/src/cpu/samsung/exynos5250/alternate_cbfs.c
+++ b/src/cpu/samsung/exynos5250/alternate_cbfs.c
@@ -24,6 +24,8 @@
#include <string.h>
#include <console/console.h>
#include "alternate_cbfs.h"
+#include "cpu.h"
+#include "power.h"
#include "spi.h"
/* This allows USB A-A firmware upload from a compatible host in four parts:
@@ -53,7 +55,7 @@ static int usb_cbfs_open(struct cbfs_media *media)
return 0;
if (!irom_load_usb()) {
- printk(BIOS_ERR, "Unable to load CBFS image via USB!\n");
+ printk(BIOS_EMERG, "Unable to load CBFS image via USB!\n");
return -1;
}
@@ -70,6 +72,45 @@ static int usb_cbfs_open(struct cbfs_media *media)
return 0;
}
+/*
+ * SDMMC works very similar to USB A-A: we copy the CBFS image into memory
+ * and read it from there. While SDMMC would also allow direct block by block
+ * on-demand reading, we might run into problems if we call back into the IROM
+ * in very late boot stages (e.g. after initializing/changing MMC clocks)... so
+ * this seems like a safer approach. It also makes it easy to pass our image
+ * down to payloads.
+ */
+static int sdmmc_cbfs_open(struct cbfs_media *media)
+{
+#ifdef __PRE_RAM__
+ /*
+ * In the bootblock, we just copy the small part that fits in the buffer
+ * and hope that it's enough (since the romstage is currently always the
+ * first component in the image, this should work out). In the romstage,
+ * we copy until our buffer is full (currently 12M) to avoid the pain of
+ * figuring out the true image size from in here. Since this is mainly a
+ * developer/debug boot mode, those shortcomings should be bearable.
+ */
+ const u32 count = alternate_cbfs_size / 512;
+ static int first_run = 1;
+ int (*irom_load_sdmmc)(u32 start, u32 count, void *dst) =
+ *irom_sdmmc_read_blocks_ptr;
+
+ if (!first_run)
+ return 0;
+
+ if (!irom_load_sdmmc(1, count, alternate_cbfs_buffer)) {
+ printk(BIOS_EMERG, "Unable to load CBFS image from SDMMC!\n");
+ return -1;
+ }
+
+ printk(BIOS_DEBUG, "SDMMC read successful, CBFS image should now be"
+ " at %p\n", alternate_cbfs_buffer);
+ first_run = 0;
+#endif
+ return 0;
+}
+
static int alternate_cbfs_close(struct cbfs_media *media) { return 0; }
static size_t alternate_cbfs_read(struct cbfs_media *media, void *dest,
@@ -90,6 +131,19 @@ static void *alternate_cbfs_map(struct cbfs_media *media, size_t offset,
static void *alternate_cbfs_unmap(struct cbfs_media *media,
const void *buffer) { return 0; }
+static int initialize_exynos_sdmmc_cbfs_media(struct cbfs_media *media)
+{
+ printk(BIOS_DEBUG, "Using Exynos alternate boot mode SDMMC\n");
+
+ media->open = sdmmc_cbfs_open;
+ media->close = alternate_cbfs_close;
+ media->read = alternate_cbfs_read;
+ media->map = alternate_cbfs_map;
+ media->unmap = alternate_cbfs_unmap;
+
+ return 0;
+}
+
static int initialize_exynos_usb_cbfs_media(struct cbfs_media *media)
{
printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n");
@@ -108,8 +162,16 @@ int init_default_cbfs_media(struct cbfs_media *media)
if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB)
return initialize_exynos_usb_cbfs_media(media);
- /* TODO: implement SDMMC (and possibly other) boot mode */
-
- return initialize_exynos_spi_cbfs_media(media,
- (void*)CONFIG_CBFS_CACHE_ADDRESS, CONFIG_CBFS_CACHE_SIZE);
+ switch (samsung_get_base_power()->om_stat & OM_STAT_MASK) {
+ case OM_STAT_SDMMC:
+ return initialize_exynos_sdmmc_cbfs_media(media);
+ case OM_STAT_SPI:
+ return initialize_exynos_spi_cbfs_media(media,
+ (void*)CONFIG_CBFS_CACHE_ADDRESS,
+ CONFIG_CBFS_CACHE_SIZE);
+ default:
+ printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n",
+ samsung_get_base_power()->om_stat);
+ return 0;
+ }
}
diff --git a/src/cpu/samsung/exynos5250/alternate_cbfs.h b/src/cpu/samsung/exynos5250/alternate_cbfs.h
index a26fe61..8a87279 100644
--- a/src/cpu/samsung/exynos5250/alternate_cbfs.h
+++ b/src/cpu/samsung/exynos5250/alternate_cbfs.h
@@ -30,6 +30,12 @@ void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070;
#define SECONDARY_BASE_BOOT_USB 0xfeed0002
u32 * const iram_secondary_base = (u32 *)0x02020018;
+/* Values pulled from U-Boot, I think the manual is wrong here (for SPI) */
+#define OM_STAT_SDMMC 0x4
+#define OM_STAT_EMMC 0x8
+#define OM_STAT_SPI 0x14
+#define OM_STAT_MASK 0x7f
+
#if defined(__BOOT_BLOCK__)
/* A small space in IRAM to hold the romstage-only image */
void * const alternate_cbfs_buffer = (void *)CONFIG_CBFS_CACHE_ADDRESS;
diff --git a/src/cpu/samsung/exynos5250/power.h b/src/cpu/samsung/exynos5250/power.h
index f349e53..5483d92 100644
--- a/src/cpu/samsung/exynos5250/power.h
+++ b/src/cpu/samsung/exynos5250/power.h
@@ -42,7 +42,8 @@ void power_enable_hw_thermal_trip(void);
/* Power Management Unit register map */
struct exynos5_power {
/* Add registers as and when required */
- uint8_t reserved1[0x0400];
+ uint32_t om_stat; /* 0x0000 */
+ uint8_t reserved1[0x03fc];
uint32_t sw_reset; /* 0x0400 */
uint8_t reserved2[0x0304];
uint32_t usb_host_phy_ctrl; /* 0x0708 */
diff --git a/src/cpu/samsung/exynos5420/alternate_cbfs.c b/src/cpu/samsung/exynos5420/alternate_cbfs.c
index 49c9d4c..4161303 100644
--- a/src/cpu/samsung/exynos5420/alternate_cbfs.c
+++ b/src/cpu/samsung/exynos5420/alternate_cbfs.c
@@ -22,8 +22,11 @@
#include <cbfs.h> /* This driver serves as a CBFS media source. */
#include <stdlib.h>
#include <string.h>
+#include <arch/cache.h>
#include <console/console.h>
#include "alternate_cbfs.h"
+#include "cpu.h"
+#include "power.h"
#include "spi.h"
/* This allows USB A-A firmware upload from a compatible host in four parts:
@@ -52,10 +55,13 @@ static int usb_cbfs_open(struct cbfs_media *media)
if (!first_run)
return 0;
+ dcache_mmu_disable();
if (!irom_load_usb()) {
- printk(BIOS_ERR, "Unable to load CBFS image via USB!\n");
+ dcache_mmu_enable();
+ printk(BIOS_EMERG, "Unable to load CBFS image via USB!\n");
return -1;
}
+ dcache_mmu_enable();
/*
* We need to trust the host/irom to copy the image to our
@@ -70,6 +76,48 @@ static int usb_cbfs_open(struct cbfs_media *media)
return 0;
}
+/*
+ * SDMMC works very similar to USB A-A: we copy the CBFS image into memory
+ * and read it from there. While SDMMC would also allow direct block by block
+ * on-demand reading, we might run into problems if we call back into the IROM
+ * in very late boot stages (e.g. after initializing/changing MMC clocks)... so
+ * this seems like a safer approach. It also makes it easy to pass our image
+ * down to payloads.
+ */
+static int sdmmc_cbfs_open(struct cbfs_media *media)
+{
+#ifdef __PRE_RAM__
+ /*
+ * In the bootblock, we just copy the small part that fits in the buffer
+ * and hope that it's enough (since the romstage is currently always the
+ * first component in the image, this should work out). In the romstage,
+ * we copy until our buffer is full (currently 12M) to avoid the pain of
+ * figuring out the true image size from in here. Since this is mainly a
+ * developer/debug boot mode, those shortcomings should be bearable.
+ */
+ const u32 count = alternate_cbfs_size / 512;
+ static int first_run = 1;
+ int (*irom_load_sdmmc)(u32 start, u32 count, void *dst) =
+ *irom_sdmmc_read_blocks_ptr;
+
+ if (!first_run)
+ return 0;
+
+ dcache_mmu_disable();
+ if (!irom_load_sdmmc(1, count, alternate_cbfs_buffer)) {
+ dcache_mmu_enable();
+ printk(BIOS_EMERG, "Unable to load CBFS image from SDMMC!\n");
+ return -1;
+ }
+ dcache_mmu_enable();
+
+ printk(BIOS_DEBUG, "SDMMC read successful, CBFS image should now be"
+ " at %p\n", alternate_cbfs_buffer);
+ first_run = 0;
+#endif
+ return 0;
+}
+
static int alternate_cbfs_close(struct cbfs_media *media) { return 0; }
static size_t alternate_cbfs_read(struct cbfs_media *media, void *dest,
@@ -90,6 +138,19 @@ static void *alternate_cbfs_map(struct cbfs_media *media, size_t offset,
static void *alternate_cbfs_unmap(struct cbfs_media *media,
const void *buffer) { return 0; }
+static int initialize_exynos_sdmmc_cbfs_media(struct cbfs_media *media)
+{
+ printk(BIOS_DEBUG, "Using Exynos alternate boot mode SDMMC\n");
+
+ media->open = sdmmc_cbfs_open;
+ media->close = alternate_cbfs_close;
+ media->read = alternate_cbfs_read;
+ media->map = alternate_cbfs_map;
+ media->unmap = alternate_cbfs_unmap;
+
+ return 0;
+}
+
static int initialize_exynos_usb_cbfs_media(struct cbfs_media *media)
{
printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n");
@@ -108,8 +169,16 @@ int init_default_cbfs_media(struct cbfs_media *media)
if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB)
return initialize_exynos_usb_cbfs_media(media);
- /* TODO: implement SDMMC (and possibly other) boot mode */
-
- return initialize_exynos_spi_cbfs_media(media,
- (void*)CONFIG_CBFS_CACHE_ADDRESS, CONFIG_CBFS_CACHE_SIZE);
+ switch (samsung_get_base_power()->om_stat & OM_STAT_MASK) {
+ case OM_STAT_SDMMC:
+ return initialize_exynos_sdmmc_cbfs_media(media);
+ case OM_STAT_SPI:
+ return initialize_exynos_spi_cbfs_media(media,
+ (void*)CONFIG_CBFS_CACHE_ADDRESS,
+ CONFIG_CBFS_CACHE_SIZE);
+ default:
+ printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n",
+ samsung_get_base_power()->om_stat);
+ return 0;
+ }
}
diff --git a/src/cpu/samsung/exynos5420/alternate_cbfs.h b/src/cpu/samsung/exynos5420/alternate_cbfs.h
index 4e9dff9..3bb9c76 100644
--- a/src/cpu/samsung/exynos5420/alternate_cbfs.h
+++ b/src/cpu/samsung/exynos5420/alternate_cbfs.h
@@ -30,6 +30,12 @@ void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070;
#define SECONDARY_BASE_BOOT_USB 0xfeed0002
u32 * const iram_secondary_base = (u32 *)0x02020018;
+/* Values pulled from U-Boot, I think the manual is wrong here (for SPI) */
+#define OM_STAT_SDMMC 0x4
+#define OM_STAT_EMMC 0x8
+#define OM_STAT_SPI 0x14
+#define OM_STAT_MASK 0x7f
+
#if defined(__BOOT_BLOCK__)
/* A small space in IRAM to hold the romstage-only image */
void * const alternate_cbfs_buffer = (void *)CONFIG_CBFS_CACHE_ADDRESS;
diff --git a/src/cpu/samsung/exynos5420/bootblock.c b/src/cpu/samsung/exynos5420/bootblock.c
index 3df51a7..1ad75ef 100644
--- a/src/cpu/samsung/exynos5420/bootblock.c
+++ b/src/cpu/samsung/exynos5420/bootblock.c
@@ -63,7 +63,6 @@ void bootblock_cpu_init(void)
mmu_config_range(0, SRAM_START, DCACHE_OFF);
mmu_config_range(SRAM_START, SRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range(SRAM_END, 4096 - SRAM_END, DCACHE_OFF);
- dcache_invalidate_all();
dcache_mmu_enable();
/* For most ARM systems, we have to initialize firmware media source
diff --git a/src/cpu/samsung/exynos5420/power.h b/src/cpu/samsung/exynos5420/power.h
index 665e94c..4efc84e 100644
--- a/src/cpu/samsung/exynos5420/power.h
+++ b/src/cpu/samsung/exynos5420/power.h
@@ -42,7 +42,8 @@ void power_enable_hw_thermal_trip(void);
/* Power Management Unit register map */
struct exynos5_power {
/* Add registers as and when required */
- uint8_t reserved1[0x0400];
+ uint32_t om_stat; /* 0x0000 */
+ uint8_t reserved1[0x03fc];
uint32_t sw_reset; /* 0x0400 */
uint8_t reserved2[0x0304];
uint32_t usb_host_phy_ctrl; /* 0x0708 */
diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c
index 3ffb824..9aa8d5c 100644
--- a/src/mainboard/google/pit/mainboard.c
+++ b/src/mainboard/google/pit/mainboard.c
@@ -330,6 +330,19 @@ static void disable_usb30_pll(void)
gpio_direction_output(usb3_pll_l, 0);
}
+static void setup_storage(void)
+{
+ /* MMC0: Fixed, 8 bit mode, connected with GPIO. */
+ if (clock_set_dwmci(PERIPH_ID_SDMMC0))
+ printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__);
+ exynos_pinmux_sdmmc0();
+
+ /* MMC2: Removable, 4 bit mode, no GPIO. */
+ /* (Must be after romstage to avoid breaking SDMMC boot.) */
+ clock_set_dwmci(PERIPH_ID_SDMMC2);
+ exynos_pinmux_sdmmc2();
+}
+
static void gpio_init(void)
{
/* Set up the I2C busses. */
@@ -370,6 +383,12 @@ static void backlight_vdd(void)
tps65090_thru_ec_fet_set(1);
}
+static void sdmmc_vdd(void)
+{
+ /* Enable FET4, P3.3V_SDCARD */
+ tps65090_thru_ec_fet_set(4);
+}
+
/* this happens after cpu_init where exynos resources are set */
static void mainboard_init(device_t dev)
{
@@ -380,6 +399,7 @@ static void mainboard_init(device_t dev)
void *fb_addr = (void *)(get_fb_base_kb() * KiB);
gpio_init();
+ setup_storage();
tmu_init(&exynos5420_tmu_info);
/* Clock Gating all the unused IP's to save power */
@@ -388,6 +408,8 @@ static void mainboard_init(device_t dev)
/* Disable USB3.0 PLL to save 250mW of power */
disable_usb30_pll();
+ sdmmc_vdd();
+
set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr);
/*
diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c
index 319ebf9..7967a55 100644
--- a/src/mainboard/google/pit/romstage.c
+++ b/src/mainboard/google/pit/romstage.c
@@ -40,8 +40,6 @@
#include <drivers/maxim/max77802/max77802.h>
#include <device/i2c.h>
-#define MMC0_GPIO_PIN (58)
-
#define PMIC_I2C_BUS 4
struct pmic_write
@@ -109,18 +107,6 @@ static int setup_power(int is_resume)
return error;
}
-static void setup_storage(void)
-{
- /* MMC0: Fixed, 8 bit mode, connected with GPIO. */
- if (clock_set_dwmci(PERIPH_ID_SDMMC0))
- printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__);
- exynos_pinmux_sdmmc0();
-
- /* MMC2: Removable, 4 bit mode, no GPIO. */
- clock_set_dwmci(PERIPH_ID_SDMMC2);
- exynos_pinmux_sdmmc2();
-}
-
static void setup_ec(void)
{
/* SPI2 (EC) is slower and needs to work in half-duplex mode with
@@ -270,7 +256,6 @@ void main(void)
wakeup();
}
- setup_storage();
setup_gpio();
setup_ec();
diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c
index 23b7072..9fc2fe6 100644
--- a/src/mainboard/google/snow/mainboard.c
+++ b/src/mainboard/google/snow/mainboard.c
@@ -38,6 +38,8 @@
#include "exynos5250.h"
+#define MMC0_GPIO_PIN (58)
+
/* convenient shorthand (in MB) */
#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
@@ -132,6 +134,7 @@ static void backlight_en(void)
#define TPS65090_BUS 4 /* Snow-specific */
#define FET1_CTRL 0x0f
+#define FET4_CTRL 0x12
#define FET6_CTRL 0x14
static void lcd_vdd(void)
@@ -147,6 +150,12 @@ static void backlight_vdd(void)
udelay(LCD_T5_DELAY_MS * 1000);
}
+static void sdmmc_vdd(void)
+{
+ /* Enable FET4, P3.3V_SDCARD */
+ tps65090_fet_enable(TPS65090_BUS, FET4_CTRL);
+}
+
//static struct video_info smdk5250_dp_config = {
static struct video_info dp_video_info = {
/* FIXME: fix video_info struct to use const for name */
@@ -179,6 +188,24 @@ static void disable_usb30_pll(void)
gpio_direction_output(usb3_pll_l, 0);
}
+static void setup_storage(void)
+{
+ /* MMC0: Fixed, 8 bit mode, connected with GPIO. */
+ if (clock_set_mshci(PERIPH_ID_SDMMC0))
+ printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__);
+ if (gpio_direction_output(MMC0_GPIO_PIN, 1)) {
+ printk(BIOS_CRIT, "%s: Unable to power on MMC0.\n", __func__);
+ }
+ gpio_set_pull(MMC0_GPIO_PIN, GPIO_PULL_NONE);
+ gpio_set_drv(MMC0_GPIO_PIN, GPIO_DRV_4X);
+ exynos_pinmux_sdmmc0();
+
+ /* MMC2: Removable, 4 bit mode, no GPIO. */
+ /* (Must be after romstage to avoid breaking SDMMC boot.) */
+ clock_set_mshci(PERIPH_ID_SDMMC2);
+ exynos_pinmux_sdmmc2();
+}
+
static void gpio_init(void)
{
/* Set up the I2C busses. */
@@ -217,6 +244,7 @@ static void mainboard_init(device_t dev)
void *fb_addr = (void *)(get_fb_base_kb() * KiB);
gpio_init();
+ setup_storage();
i2c_init(TPS65090_BUS, I2C_0_SPEED, I2C_SLAVE);
i2c_init(7, I2C_0_SPEED, I2C_SLAVE);
@@ -229,6 +257,8 @@ static void mainboard_init(device_t dev)
/* Disable USB3.0 PLL to save 250mW of power */
disable_usb30_pll();
+ sdmmc_vdd();
+
set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr);
lcd_vdd();
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index 3a8b5e8..44074c5 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -42,7 +42,6 @@
#include "exynos5250.h"
#define PMIC_BUS 0
-#define MMC0_GPIO_PIN (58)
static void setup_power(int is_resume)
{
@@ -96,23 +95,6 @@ static void setup_power(int is_resume)
}
}
-static void setup_storage(void)
-{
- /* MMC0: Fixed, 8 bit mode, connected with GPIO. */
- if (clock_set_mshci(PERIPH_ID_SDMMC0))
- printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__);
- if (gpio_direction_output(MMC0_GPIO_PIN, 1)) {
- printk(BIOS_CRIT, "%s: Unable to power on MMC0.\n", __func__);
- }
- gpio_set_pull(MMC0_GPIO_PIN, GPIO_PULL_NONE);
- gpio_set_drv(MMC0_GPIO_PIN, GPIO_DRV_4X);
- exynos_pinmux_sdmmc0();
-
- /* MMC2: Removable, 4 bit mode, no GPIO. */
- clock_set_mshci(PERIPH_ID_SDMMC2);
- exynos_pinmux_sdmmc2();
-}
-
static void setup_graphics(void)
{
exynos_pinmux_dphpd();
@@ -176,7 +158,6 @@ void main(void)
wakeup();
}
- setup_storage();
setup_gpio();
setup_graphics();
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6604
-gerrit
commit 04b441b4e341f0cdb68f2fd42153cdde77b6b9b4
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Tue Aug 20 17:13:01 2013 -0700
exynos5420: Alter init sequence as per recommendation
As per hardware recommendation, CKE PAD retention release must
happen just before gate leveling enable and only in case of resume.
Hence, this patch moves pad retention release from dmc_common.c to
dmc_init_ddr3_exynos5420.c. In addition to this we are providing
125 (+3 extra being safe) times auto refresh to DRAM by sending
REFA direct command. This is required because when CKE PAD retention
release happens, self refresh mode of DDR3 is disabled.
Hence, auto refresh 125 times.
This is ported from https://gerrit.chromium.org/gerrit/#/c/65573
Note: Since WAKEUP_DIRECT does not go thru memory init, it should be
safe to move CKE PAD retention out of bootblock.c.
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Change-Id: Idec5d6fbbe3c6344d47401ba7203079c52a9b866
Reviewed-on: https://gerrit.chromium.org/gerrit/66788
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org>
(cherry picked from commit 96cbcb09245d4df92d3e1998704ab440be42df25)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/cpu/samsung/exynos5420/bootblock.c | 17 -------------
src/cpu/samsung/exynos5420/dmc_init_ddr3.c | 39 ++++++++++++++++++++++++++----
src/cpu/samsung/exynos5420/setup.h | 1 +
3 files changed, 35 insertions(+), 22 deletions(-)
diff --git a/src/cpu/samsung/exynos5420/bootblock.c b/src/cpu/samsung/exynos5420/bootblock.c
index 1ad75ef..2c42b03 100644
--- a/src/cpu/samsung/exynos5420/bootblock.c
+++ b/src/cpu/samsung/exynos5420/bootblock.c
@@ -31,23 +31,6 @@
void bootblock_cpu_init(void);
void bootblock_cpu_init(void)
{
- u32 ret;
- /*
- * During Suspend-Resume & S/W-Reset, as soon as PMU releases
- * pad retention, CKE goes high. This causes memory contents
- * not to be retained during DRAM initialization. Therfore,
- * there is a new control register(0x100431e8[28]) which lets us
- * release pad retention and retain the memory content until the
- * initialization is complete.
- */
- if (read32(((void *)INF_REG_BASE + INF_REG1_OFFSET)) == S5P_CHECK_SLEEP) {
- write32(PAD_RETENTION_DRAM_COREBLK_VAL,
- (void *)PAD_RETENTION_DRAM_COREBLK_OPTION);
- do {
- ret = read32((void *)PAD_RETENTION_DRAM_STATUS);
- } while (ret != 0x1);
- }
-
/* kick off the multi-core timer.
* We want to do this as early as we can.
*/
diff --git a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
index 6c431f3..0a4edc8 100644
--- a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
+++ b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
@@ -184,14 +184,43 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
writel(mem->timing_power, &drex0->timingpower);
writel(mem->timing_power, &drex1->timingpower);
- /* Send NOP, MRS and ZQINIT commands.
- * Sending MRS command will reset the DRAM. We should not be
- * reseting the DRAM after resume, this will lead to memory
- * corruption as DRAM content is lost after DRAM reset.
- */
if (reset) {
+ /* Send NOP, MRS and ZQINIT commands.
+ * Sending MRS command will reset the DRAM. We should not be
+ * reseting the DRAM after resume, this will lead to memory
+ * corruption as DRAM content is lost after DRAM reset.
+ */
dmc_config_mrs(mem, drex0);
dmc_config_mrs(mem, drex1);
+ } else {
+ u32 ret;
+
+ /*
+ * During Suspend-Resume & S/W-Reset, as soon as PMU releases
+ * pad retention, CKE goes high. This causes memory contents
+ * not to be retained during DRAM initialization. Therfore,
+ * there is a new control register(0x100431e8[28]) which lets us
+ * release pad retention and retain the memory content until the
+ * initialization is complete.
+ */
+ write32(PAD_RETENTION_DRAM_COREBLK_VAL,
+ (void *)PAD_RETENTION_DRAM_COREBLK_OPTION);
+ do {
+ ret = read32((void *)PAD_RETENTION_DRAM_STATUS);
+ } while (ret != 0x1);
+
+ /*
+ * CKE PAD retention disables DRAM self-refresh mode.
+ * Send auto refresh command for DRAM refresh.
+ */
+ for (i = 0; i < 128; i++) {
+ writel(DIRECT_CMD_REFA, &drex0->directcmd);
+ writel(DIRECT_CMD_REFA | (0x1 << DIRECT_CMD_CHIP_SHIFT),
+ &drex0->directcmd);
+ writel(DIRECT_CMD_REFA, &drex1->directcmd);
+ writel(DIRECT_CMD_REFA | (0x1 << DIRECT_CMD_CHIP_SHIFT),
+ &drex1->directcmd);
+ }
}
if (mem->gate_leveling_enable) {
diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h
index ca7281d..9dc49d8 100644
--- a/src/cpu/samsung/exynos5420/setup.h
+++ b/src/cpu/samsung/exynos5420/setup.h
@@ -715,6 +715,7 @@ struct exynos5_phy_control;
#define DIRECT_CMD_ZQINIT 0x0a000000
#define DIRECT_CMD_CHANNEL_SHIFT 28
#define DIRECT_CMD_CHIP_SHIFT 20
+#define DIRECT_CMD_BANK_SHIFT 16
#define DIRECT_CMD_REFA (5 << 24)
#define DIRECT_CMD_MRS1 0x71C00
#define DIRECT_CMD_MRS2 0x10BFC