Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6613
-gerrit
commit 5f21d037a51eaf1d310a544286029aa4fce040cb
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Thu Aug 29 14:05:21 2013 -0700
exynos5420/pit: re-factor membaseconfig0/1 usage
membaseconfig0/1 are utterly dependent on the mainboard's particular
DRAM setup. This defines their values in the mem_timings struct for
pit.
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Old-Change-Id: Ifd782d1229b2418f8ddbf0bcb3f45cc828ac34b0
Reviewed-on: https://chromium-review.googlesource.com/167488
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-by: ron minnich <rminnich(a)chromium.org>
(cherry picked from commit 80eebd5bc0dbb9fabf81f46c25dcd5c5d5747579)
exynos5420: necessary updates for DRAM
This updates DRAM usage for Exynos5420 so that we can actually
use 3.5GB:
- Memory chips used with Exynos5420 may have 16 row address lines.
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Old-Change-Id: I86d1a96d0d1a028587f7655f8de5a2e52165e9d2
Reviewed-on: https://chromium-review.googlesource.com/167489
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-by: ron minnich <rminnich(a)chromium.org>
(cherry picked from commit 04bbaf5d8e125166dd689f656d5b37776be01fb1)
Squashed two related commits.
Change-Id: I4e45bc8a446715897ec21b0160701152fa6b226b
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/cpu/samsung/exynos5420/dmc_init_ddr3.c | 24 +++++++++---------------
src/cpu/samsung/exynos5420/setup.h | 16 +++++++---------
src/mainboard/google/pit/memory.c | 7 +++++++
3 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
index 1126dca..1d7b8a8 100644
--- a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
+++ b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
@@ -145,21 +145,15 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
update_reset_dll(drex0, DDR_MODE_DDR3);
update_reset_dll(drex1, DDR_MODE_DDR3);
- /* Set Base Address:
- * 0x2000_0000 ~ 0x5FFF_FFFF
- * 0x6000_0000 ~ 0x9FFF_FFFF
- */
- /* MEMBASECONFIG0 */
- val = DMC_MEMBASECONFIGx_CHIP_BASE(DMC_CHIP_BASE_0) |
- DMC_MEMBASECONFIGx_CHIP_MASK(DMC_CHIP_MASK);
- writel(val, &tzasc0->membaseconfig0);
- writel(val, &tzasc1->membaseconfig0);
-
- /* MEMBASECONFIG1 */
- val = DMC_MEMBASECONFIGx_CHIP_BASE(DMC_CHIP_BASE_1) |
- DMC_MEMBASECONFIGx_CHIP_MASK(DMC_CHIP_MASK);
- writel(val, &tzasc0->membaseconfig1);
- writel(val, &tzasc1->membaseconfig1);
+ /* MEMBASECONFIG0 (CS0) */
+ writel(mem->membaseconfig0, &tzasc0->membaseconfig0);
+ writel(mem->membaseconfig0, &tzasc1->membaseconfig0);
+
+ /* MEMBASECONFIG1 (CS1) */
+ if (mem->chips_per_channel == 2) {
+ writel(mem->membaseconfig1, &tzasc0->membaseconfig1);
+ writel(mem->membaseconfig1, &tzasc1->membaseconfig1);
+ }
/* Memory Channel Inteleaving Size
* Exynos5420 Channel interleaving = 128 bytes
diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h
index 3bd36b2..950c2c6 100644
--- a/src/cpu/samsung/exynos5420/setup.h
+++ b/src/cpu/samsung/exynos5420/setup.h
@@ -136,6 +136,7 @@ struct exynos5_phy_control;
#define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8)
#define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4)
#define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4)
+#define DMC_MEMCONFIGx_CHIP_ROW_16 (4 << 4)
#define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0)
#define DMC_MEMBASECONFIGx_CHIP_BASE(x) (x << 16)
@@ -767,15 +768,12 @@ struct exynos5_phy_control;
#define DPWRDN_EN (1 << 1)
#define DSREF_EN (1 << 5)
-/* As we use channel interleaving, therefore value of the base address
- * register must be set as half of the bus base address
- * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
- * we need to set half 0x10 to the membaseconfigx registers
- * see exynos5420 UM section 17.17.3.21 for more
- */
-#define DMC_CHIP_BASE_0 0x10
-#define DMC_CHIP_BASE_1 0x50
-#define DMC_CHIP_MASK 0x7C0
+/* AXI base address mask */
+#define DMC_CHIP_MASK_256MB 0x7f0
+#define DMC_CHIP_MASK_512MB 0x7e0
+#define DMC_CHIP_MASK_1GB 0x7c0
+#define DMC_CHIP_MASK_2GB 0x780
+#define DMC_CHIP_MASK_4GB 0x700
#define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0
#define MEMBASECONFIG_CHIP_MASK_OFFSET 0
diff --git a/src/mainboard/google/pit/memory.c b/src/mainboard/google/pit/memory.c
index 4ac3d0c..0c30773 100644
--- a/src/mainboard/google/pit/memory.c
+++ b/src/mainboard/google/pit/memory.c
@@ -90,6 +90,13 @@ const struct mem_timings mem_timings = {
DMC_MEMCONTROL_BL_8 |
DMC_MEMCONTROL_PZQ_DISABLE |
DMC_MEMCONTROL_MRR_BYTE_7_0,
+ /*
+ * For channel interleaving, the chip_base needs to be set to
+ * half the bus address. So for a base address of 0x2000_0000,
+ * the chip_base value is 0x20 without interleaving and 0x10
+ * with channel interleaving. See note in section 17.14.
+ */
+ .membaseconfig0 = (0x10 << 16) | DMC_CHIP_MASK_1GB,
.memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
DMC_MEMCONFIGx_CHIP_COL_10 |
DMC_MEMCONFIGx_CHIP_ROW_15 |
the following patch was just integrated into master:
commit 32eeff4b6eaf5e0bf1979cc9d08ac60d8d011354
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Mon Aug 11 09:27:18 2014 +0200
util: replace fseek/ftell/rewind with fstat
It's a more direct approach to get the file size.
Change-Id: If49df26bf4996bd556c675f3a673d0003b4adf89
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6594
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/6594 for details.
-gerrit
the following patch was just integrated into master:
commit 77b182a31a17e237da2350b0290301f5ce51d9d8
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Sun Aug 10 15:18:22 2014 +0200
board-status: be protocol agnostic on upload
Generate the board-status repo URL by replacing the
last occurrence of "/coreboot" by "/board-status",
which works across repo URL schemes (gerrit provides
several).
Change-Id: Iccb53bde994be619c1436815e13741d63738edf7
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6574
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/6574 for details.
-gerrit
the following patch was just integrated into master:
commit 8f15f4715a8627c032c78636798fe9bf8d23c6e1
Author: Daniele Forsi <dforsi(a)gmail.com>
Date: Sun Aug 10 16:58:23 2014 +0200
Kconfig: do not set SB_HT_CHAIN_ON_BUS0 twice to the same value
Change-Id: If7286abf91f758cfbac2c85dcad336f38f70d843
Signed-off-by: Daniele Forsi <dforsi(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6579
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/6579 for details.
-gerrit
the following patch was just integrated into master:
commit ea70a5068fb6df4adcdb43142e77fdb2e9ccac1e
Author: Daniele Forsi <dforsi(a)gmail.com>
Date: Sun Aug 3 13:47:58 2014 +0200
util/genprof: improve handling of command line arguments
Accept only one command line argument (the input file name); close input
stream both on error and on success; print more informative error messages
when files could not be opened.
Change-Id: Ib2f0622a332317d7a13f33f1e5787381804c43a9
Found-by: missing fclose()'s found by Cppcheck 1.65
Signed-off-by: Daniele Forsi <dforsi(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6573
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
See http://review.coreboot.org/6573 for details.
-gerrit
the following patch was just integrated into master:
commit 21fbc08d4b3f99ca606dc1b9e12bcffef65bfb50
Author: Daniele Forsi <dforsi(a)gmail.com>
Date: Sun Aug 10 15:18:42 2014 +0200
armv7/Makefile.inc, cpu/Makefile.inc: align output of printf
Fix whitespace.
Change-Id: I9e28b819d685851a84cee6c5a71458e07d0ec808
Signed-off-by: Daniele Forsi <dforsi(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6577
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
See http://review.coreboot.org/6577 for details.
-gerrit
the following patch was just integrated into master:
commit b40c345947d7891070f46f67e9ded65d74d58f7a
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Mon Aug 11 11:10:29 2014 -0600
mainboard/intel/minnowmax: clean up includes & whitespace
Clean up as requested in commit e6df041b.
No functional changes.
Change-Id: Iec3f7ee25fd8351c7e13d660e2df6461f7745478
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6597
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/6597 for details.
-gerrit