the following patch was just integrated into master:
commit b25a9e9d3035c6e3c6969fed97a5193b95df249f
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Tue Aug 12 20:39:28 2014 +0200
gm45: Allow coexistance with ME firmware.
Change-Id: I08ca5eec94c70b43789122266d68af149772385c
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6626
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
See http://review.coreboot.org/6626 for details.
-gerrit
the following patch was just integrated into master:
commit 32193e1f208191c908a1f8c601291541e86667a2
Author: ChromeOS Developer <dparker(a)chromium.org>
Date: Mon Dec 16 23:41:11 2013 -0800
Haswell: Lower TJ_MAX to 100C. Adjust critical temps to match.
Change-Id: I3326b6e3c412b6360af37030cefd13d95b704e70
Signed-off-by: Dave Parker <dparker(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180750
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit 1978b0f91b2e91d2251721c7c6981d51a6930b61)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6615
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
See http://review.coreboot.org/6615 for details.
-gerrit
the following patch was just integrated into master:
commit 5a0fdb4565dc6baf89155268dd0f52e6885197d8
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Thu Aug 29 13:12:56 2013 -0700
exynos5420: minor clean-up memory related stuff
This cleans up a few minor things (mostly #defines) of the memory code
for exynos5420, pit, and kirby. Specifically:
- CONCONTROL.empty is read-only, so don't try to set it and also
get rid of the unneeded DMC_CONCONTROL_EMPTY_ENABLE #define.
- MEMBASECONFIG* overlaps members of the mem_timings struct and
are mainboard-dependent anyway, so get rid of 'em.
- DMC_MEMCONTROL_TP_DISABLE corresponds to a reserved bit. It may
have been deprecated.
- Same with TIMING* #defines.
- Clarify DDR_MODE_* usage and use mem->mem_type when appropriate.
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Change-Id: Ideb21efcc97b24f7e115e90051c20daef4480f17
Reviewed-on: https://chromium-review.googlesource.com/167500
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-by: ron minnich <rminnich(a)chromium.org>
(cherry picked from commit 650dba32cb217414c422907398f68e784e5720e8)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6614
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
See http://review.coreboot.org/6614 for details.
-gerrit
the following patch was just integrated into master:
commit 122b6d6ce694cd55087b4956780b2bbde8ccc6fe
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Thu Aug 29 14:05:21 2013 -0700
exynos5420/pit: re-factor membaseconfig0/1 usage
membaseconfig0/1 are utterly dependent on the mainboard's particular
DRAM setup. This defines their values in the mem_timings struct for
pit.
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Old-Change-Id: Ifd782d1229b2418f8ddbf0bcb3f45cc828ac34b0
Reviewed-on: https://chromium-review.googlesource.com/167488
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-by: ron minnich <rminnich(a)chromium.org>
(cherry picked from commit 80eebd5bc0dbb9fabf81f46c25dcd5c5d5747579)
exynos5420: necessary updates for DRAM
This updates DRAM usage for Exynos5420 so that we can actually
use 3.5GB:
- Memory chips used with Exynos5420 may have 16 row address lines.
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Old-Change-Id: I86d1a96d0d1a028587f7655f8de5a2e52165e9d2
Reviewed-on: https://chromium-review.googlesource.com/167489
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-by: ron minnich <rminnich(a)chromium.org>
(cherry picked from commit 04bbaf5d8e125166dd689f656d5b37776be01fb1)
Squashed two related commits.
Change-Id: I4e45bc8a446715897ec21b0160701152fa6b226b
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6613
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/6613 for details.
-gerrit
the following patch was just integrated into master:
commit 72a42886505f54e81f437b618af1ab57e95c4b71
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Fri Aug 23 15:25:07 2013 -0700
exynos5420: ddr3: Switch from 4G setup to 2G setup on exynos5420
This changes the number of chip selects that we configure from 2 to 1.
On current setups with (x16 memory 4Gbit chips) that means that we're
at 2GByte.
Technically we should add a second setting in the ares_ddr3_timings
and select between the two of the based on board strappings. That
would make the CONFIG_RUN_TIME_BANK_NUMBER work properly. I've
changed the ddr3_mem_ctrl_init() so it should handle that, but I'm not
actually doing the board strapping read right now.
This change means that accesses to 0xA0000000 - 0xFFFFFFFF on 2G
systems will no longer put the system in a messed up state (leading to
a hang). It also prevents some of the weird boot behavior that we've
seen that comes and goes depending on U-Boot alignment. See
<http://crosbug.com/p/20577>.
This patch was ported from: https://gerrit.chromium.org/gerrit/66117
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Change-Id: Ib4cfe420aac30bd817438f06d01e8671afc4a27d
Reviewed-on: https://chromium-review.googlesource.com/167210
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-by: ron minnich <rminnich(a)chromium.org>
(cherry picked from commit 0ea574243058068702e3f6bc7355098745d16880)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6612
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/6612 for details.
-gerrit
the following patch was just integrated into master:
commit dd1aab95a6eb74eac7ea0463f7933d186dbd0efb
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Sat Aug 9 17:06:20 2014 +0200
nvramtool: plug some memory leaks
Change-Id: I8f672b872862d3448ccd2cf28fd3c05b0108ff8b
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6561
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/6561 for details.
-gerrit
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6612
-gerrit
commit 1a1b1cb890d171dda759c97f9de6d49f03f85a59
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Fri Aug 23 15:25:07 2013 -0700
exynos5420: ddr3: Switch from 4G setup to 2G setup on exynos5420
This changes the number of chip selects that we configure from 2 to 1.
On current setups with (x16 memory 4Gbit chips) that means that we're
at 2GByte.
Technically we should add a second setting in the ares_ddr3_timings
and select between the two of the based on board strappings. That
would make the CONFIG_RUN_TIME_BANK_NUMBER work properly. I've
changed the ddr3_mem_ctrl_init() so it should handle that, but I'm not
actually doing the board strapping read right now.
This change means that accesses to 0xA0000000 - 0xFFFFFFFF on 2G
systems will no longer put the system in a messed up state (leading to
a hang). It also prevents some of the weird boot behavior that we've
seen that comes and goes depending on U-Boot alignment. See
<http://crosbug.com/p/20577>.
This patch was ported from: https://gerrit.chromium.org/gerrit/66117
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Change-Id: Ib4cfe420aac30bd817438f06d01e8671afc4a27d
Reviewed-on: https://chromium-review.googlesource.com/167210
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-by: ron minnich <rminnich(a)chromium.org>
(cherry picked from commit 0ea574243058068702e3f6bc7355098745d16880)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/cpu/samsung/exynos5420/dmc_init_ddr3.c | 36 +++++++++++++++++-------------
src/mainboard/google/pit/memory.c | 6 ++---
2 files changed, 24 insertions(+), 18 deletions(-)
diff --git a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
index a758433..1126dca 100644
--- a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
+++ b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
@@ -44,7 +44,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
struct exynos5_dmc *drex0, *drex1;
struct exynos5_tzasc *tzasc0, *tzasc1;
u32 val, nLockR, nLockW_phy0, nLockW_phy1;
- int i;
+ int i, chip;
phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
@@ -218,12 +218,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
* Send auto refresh command for DRAM refresh.
*/
for (i = 0; i < 128; i++) {
- writel(DIRECT_CMD_REFA, &drex0->directcmd);
- writel(DIRECT_CMD_REFA | (0x1 << DIRECT_CMD_CHIP_SHIFT),
- &drex0->directcmd);
- writel(DIRECT_CMD_REFA, &drex1->directcmd);
- writel(DIRECT_CMD_REFA | (0x1 << DIRECT_CMD_CHIP_SHIFT),
- &drex1->directcmd);
+ for (chip = 0; chip < mem->chips_to_configure; chip++) {
+ writel(DIRECT_CMD_REFA |
+ (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex0->directcmd);
+ writel(DIRECT_CMD_REFA |
+ (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex1->directcmd);
+ }
}
}
@@ -263,10 +265,12 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
writel(nLockR, &phy1_ctrl->phy_con12);
val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
- writel(val, &drex0->directcmd);
- writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex0->directcmd);
- writel(val, &drex1->directcmd);
- writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex1->directcmd);
+ for (chip = 0; chip < mem->chips_to_configure; chip++) {
+ writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex0->directcmd);
+ writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex1->directcmd);
+ }
setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN);
setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN);
@@ -316,10 +320,12 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
writel(0, &phy1_ctrl->phy_con14);
val = (0x3 << DIRECT_CMD_BANK_SHIFT);
- writel(val, &drex0->directcmd);
- writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex0->directcmd);
- writel(val, &drex1->directcmd);
- writel(val | (0x1 << DIRECT_CMD_CHIP_SHIFT), &drex1->directcmd);
+ for (chip = 0; chip < mem->chips_to_configure; chip++) {
+ writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex0->directcmd);
+ writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
+ &drex1->directcmd);
+ }
/* Common Settings for Leveling */
val = PHY_CON12_RESET_VAL;
diff --git a/src/mainboard/google/pit/memory.c b/src/mainboard/google/pit/memory.c
index ddd7aa0..4ac3d0c 100644
--- a/src/mainboard/google/pit/memory.c
+++ b/src/mainboard/google/pit/memory.c
@@ -86,7 +86,7 @@ const struct mem_timings mem_timings = {
DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
DMC_MEMCONTROL_MEM_TYPE_DDR3 |
DMC_MEMCONTROL_MEM_WIDTH_32BIT |
- DMC_MEMCONTROL_NUM_CHIP_2 |
+ DMC_MEMCONTROL_NUM_CHIP_1 |
DMC_MEMCONTROL_BL_8 |
DMC_MEMCONTROL_PZQ_DISABLE |
DMC_MEMCONTROL_MRR_BYTE_7_0,
@@ -104,8 +104,8 @@ const struct mem_timings mem_timings = {
DMC_CONCONTROL_AREF_EN_DISABLE |
DMC_CONCONTROL_IO_PD_CON_DISABLE,
.dmc_channels = 1,
- .chips_per_channel = 2,
- .chips_to_configure = 2,
+ .chips_per_channel = 1,
+ .chips_to_configure = 1,
.send_zq_init = 1,
.gate_leveling_enable = 1,
};
the following patch was just integrated into master:
commit 42b1b8069c35a4e86772b600ea0264503bf20470
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Mon Aug 26 15:12:12 2013 -0700
Exynos5420: ddr3: fine tuning the DDR3 timing values
Fine tuning DDR timings value for better stability
* Changed Data Driver Strength from 34 ohms to 30 ohms, expected to
enhance signal integrity.
* Changed DQ signal from 0xf to 0x1f000f, to keep default value safe.
* Changed mrs[2] and added new mrs direct command for setting WL/RL
without resetting DLL.
* Added explicit reset value write in phy_con0 instead of just setting
a bit, to ensure that reset happens.
* Added DREX automatic control for ctrl_pd in none read memory state.
This is ported from: https://gerrit.chromium.org/gerrit/61405
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Change-Id: I59e96e6dede7b49c6572548aca664d82ad110bb1
Reviewed-on: https://chromium-review.googlesource.com/66995
Reviewed-by: ron minnich <rminnich(a)chromium.org>
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
(cherry picked from commit ec34b711c6d270672c56d45c370ca14c0aa27ca3)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6611
Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See http://review.coreboot.org/6611 for details.
-gerrit
the following patch was just integrated into master:
commit 4610f0e64f92639e6992dc242dabbfbfc1cb7453
Author: Julius Werner <jwerner(a)chromium.org>
Date: Thu Aug 22 16:24:09 2013 -0700
libpayload: ehci: Set explicit terminate bits in dummy_qh next pointers.
The EHCI host controllers in Samsung Exynos SoC seem to be a little more
picky than Intel ones. When they reach the dummy_qh in the periodic
frame list, they try to access the next qTD pointer even though it's
NULL, and run into a HostSystemError. This patch explicitly sets the
Terminate bit on those pointers to mark them invalid.
Change-Id: I50fa79bbf1c5fab306d7885c01efd66b13e279b8
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66884
Reviewed-by: Vincent Palatin <vpalatin(a)chromium.org>
(cherry picked from commit c575a5c958ce88732d28044352c89418bcd5ea86)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6608
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
See http://review.coreboot.org/6608 for details.
-gerrit
the following patch was just integrated into master:
commit 3ffdafdfa4cabdae4828638c402a6a81780bc275
Author: David Hendricks <dhendrix(a)chromium.org>
Date: Fri Aug 23 15:47:06 2013 -0700
Exynos5420: Remove code for enabling read leveling
This patch intends to remove all code which enables hardware read
leveling. We need to disable h/w read leveling because new ASV table
is merged in kernel (which is based on the new characterization
condition) and new characterization environment has h/w read leveling
disabled, so we should also disable this. Also, disabling h/w read
leveling improves the MIF LVcc value (LVcc value is the value at which
DDR will fail to work properly), improve LVcc means we have enough
voltage margin for MIF. When h/w leveling is enabled, we have almost
zero volatge margin.
This was ported from: https://gerrit.chromium.org/gerrit/66070
Signed-off-by: David Hendricks <dhendrix(a)chromium.org>
Change-Id: Id0a2d77e6214325f226d51ae08464b39424cea83
Reviewed-on: https://chromium-review.googlesource.com/66994
Reviewed-by: Gabe Black <gabeblack(a)chromium.org>
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
(cherry picked from commit d29add98f52876aaed4fee2b76edf6b4591e66e8)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6610
Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See http://review.coreboot.org/6610 for details.
-gerrit