Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6635
-gerrit
commit c5d373a2822a49d8a88feef1fa841943db6063e6
Author: Gabe Black <gabeblack(a)google.com>
Date: Thu Sep 12 06:23:51 2013 -0700
pit: snow: Fix snow, fix up pit write protect.
A recent change to support early firmware selection on ARM broke snow and was
incompletely implemented on pit. This change fixes snow by applying
the remaining part of the change that had been applied to pit,
and also hooks up real values in the get_write_protect_state function.
Change-Id: Ifef7ad1bf399f79353daec3dd46973f2b2022e37
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/169120
Reviewed-by: David Hendrix <dhendrix(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit 841773e048cd9cfbb64782059c24e29c467f17c8)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/mainboard/google/pit/chromeos.c | 2 +-
src/mainboard/google/snow/chromeos.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/google/pit/chromeos.c b/src/mainboard/google/pit/chromeos.c
index c2db165..2933a35 100644
--- a/src/mainboard/google/pit/chromeos.c
+++ b/src/mainboard/google/pit/chromeos.c
@@ -97,5 +97,5 @@ int get_recovery_mode_switch(void)
int get_write_protect_state(void)
{
- return 0; // FIXME what GPIO? // WP hard coded to disabled
+ return !gpio_get_value(GPIO_X30);
}
diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c
index de882ab..5310a4d 100644
--- a/src/mainboard/google/snow/chromeos.c
+++ b/src/mainboard/google/snow/chromeos.c
@@ -95,7 +95,7 @@ int get_recovery_mode_switch(void)
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
}
-int get_recovery_mode_from_vbnv(void)
+int get_write_protect_state(void)
{
- return 0;
+ return !gpio_get_value(GPIO_D16);
}
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6634
-gerrit
commit f69ca0495fea41a3278e025a91236c8722ccff9f
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon Sep 9 14:37:03 2013 -0700
ARMv7/Exynos: Fix memory location assumptions
This patch cleans out a lot of unused variables in the
ARM Kconfig files and introduces CONFIG_RAMSTAGE_BASE
which is similar to CONFIG_RAMBASE on x86.
This gets rid of the hard coded assumption that on ARM
coreboot is always executed at the lowest DRAM address.
But in fact, this might not be true because we might want
coreboot to live at the end of RAM, or in SRAM
Change-Id: I03e992645f9eb730e39a521aa21f702959311f74
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/168645
Reviewed-by: David Hendrix <dhendrix(a)chromium.org>
Tested-by: David Hendrix <dhendrix(a)chromium.org>
(cherry picked from commit 15b87892eb2d5e27759c49dc6c8c7e626f651d77)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/arch/armv7/ramstage.ld | 13 ++++++++-----
src/arch/armv7/romstage.ld | 2 +-
src/cpu/samsung/exynos5250/Kconfig | 15 +++++----------
src/cpu/samsung/exynos5420/Kconfig | 20 +++++---------------
src/mainboard/emulation/qemu-armv7/Kconfig | 18 +++++++-----------
5 files changed, 26 insertions(+), 42 deletions(-)
diff --git a/src/arch/armv7/ramstage.ld b/src/arch/armv7/ramstage.ld
index 42090f4..91efe2c 100644
--- a/src/arch/armv7/ramstage.ld
+++ b/src/arch/armv7/ramstage.ld
@@ -1,7 +1,7 @@
/*
* Memory map:
*
- * CONFIG_RAMBASE : text segment
+ * CONFIG_RAMSTAGE_BASE : text segment
* : rodata segment
* : data segment
* : bss segment
@@ -31,7 +31,7 @@ PHDRS
SECTIONS
{
- . = CONFIG_SYS_SDRAM_BASE;
+ . = CONFIG_RAMSTAGE_BASE;
/* First we place the code and read only data (typically const declared).
* This could theoretically be placed in rom.
*/
@@ -111,9 +111,6 @@ SECTIONS
}
_eheap = .;
- _stack = CONFIG_STACK_BOTTOM;
- _estack = CONFIG_STACK_TOP;
-
/* The ram segment. This includes all memory used by the memory
* resident copy of coreboot, except the tables that are produced on
* the fly, but including stack and heap.
@@ -121,6 +118,12 @@ SECTIONS
_ram_seg = _text;
_eram_seg = _eheap;
+ /* The stack lives in SRAM in a different location, so keep
+ * it out of ram_seg
+ */
+ _stack = CONFIG_STACK_BOTTOM;
+ _estack = CONFIG_STACK_TOP;
+
/* Discard the sections we don't need/want */
/DISCARD/ : {
diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld
index 0203efb..0ebcd53 100644
--- a/src/arch/armv7/romstage.ld
+++ b/src/arch/armv7/romstage.ld
@@ -1,7 +1,7 @@
/*
* Memory map:
*
- * CONFIG_RAMBASE : text segment
+ * CONFIG_ROMSTAGE_BASE : text segment
* : rodata segment
* : data segment
* : bss segment
diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig
index f937e7b..116f568 100644
--- a/src/cpu/samsung/exynos5250/Kconfig
+++ b/src/cpu/samsung/exynos5250/Kconfig
@@ -38,6 +38,9 @@ config CBFS_ROM_OFFSET
hex "offset of CBFS data in ROM"
default 0x0A000
+config SYS_SDRAM_BASE
+ hex
+ default 0x40000000
# Example SRAM/iRAM map for Exynos5250 platform:
#
@@ -54,9 +57,9 @@ config ROMSTAGE_BASE
hex
default 0x02030000
-config ROMSTAGE_SIZE
+config RAMSTAGE_BASE
hex
- default 0x10000
+ default SYS_SDRAM_BASE
# Stack may reside in either IRAM or DRAM. We will define it to live
# at the top of IRAM for now.
@@ -90,12 +93,4 @@ config TTB_BUFFER
hex "memory address of the TTB buffer"
default 0x02058000
-config TTB_SIZE
- hex "size of the TTB buffer"
- default 0x4000
-
-config SYS_SDRAM_BASE
- hex
- default 0x40000000
-
endif
diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig
index fe475ab..6871097 100644
--- a/src/cpu/samsung/exynos5420/Kconfig
+++ b/src/cpu/samsung/exynos5420/Kconfig
@@ -39,6 +39,9 @@ config CBFS_ROM_OFFSET
hex "offset of CBFS data in ROM"
default 0x0A000
+config SYS_SDRAM_BASE
+ hex
+ default 0x20000000
# Example SRAM/iRAM map for Exynos5420 platform:
#
@@ -62,9 +65,9 @@ config ROMSTAGE_BASE
hex
default 0x02030000
-config ROMSTAGE_SIZE
+config RAMSTAGE_BASE
hex
- default 0x20000
+ default SYS_SDRAM_BASE
# Stack may reside in either IRAM or DRAM. We will define it to live
# at the top of IRAM for now.
@@ -89,11 +92,6 @@ config STACK_BOTTOM
hex
default 0x0206f000
-# The romstage stack must be large enough to contain the lzma buffer
-config ROMSTAGE_STACK_SIZE
- hex
- default 0x4000
-
# STACK_SIZE is for the ramstage core and thread stacks.
# It must be a power of 2, to make the cpu_info computation work,
# and cpu_info needs to work to make SMP startup and threads work.
@@ -115,12 +113,4 @@ config TTB_BUFFER
hex "memory address of the TTB buffer"
default 0x02058000
-config TTB_SIZE
- hex "size of the TTB buffer"
- default 0x4000
-
-config SYS_SDRAM_BASE
- hex
- default 0x20000000
-
endif
diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig
index 01f3baa..fad20c6 100644
--- a/src/mainboard/emulation/qemu-armv7/Kconfig
+++ b/src/mainboard/emulation/qemu-armv7/Kconfig
@@ -33,7 +33,7 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER
string
- default "QEMU ARMV7"
+ default "QEMU ARMv7"
config MAX_CPUS
int
@@ -43,6 +43,10 @@ config MAINBOARD_VENDOR
string
default "ARM Ltd."
+config SYS_SDRAM_BASE
+ hex "SDRAM base address"
+ default 0x01000000
+
config DRAM_SIZE_MB
int
default 1024
@@ -62,17 +66,13 @@ config BOOTBLOCK_BASE
hex
default 0x00010000
-config ID_SECTION_BASE
- hex
- default 0x0001f000
-
config ROMSTAGE_BASE
hex
default 0x00020000
-config ROMSTAGE_SIZE
+config RAMSTAGE_BASE
hex
- default 0x20000
+ default SYS_SDRAM_BASE
config BOOTBLOCK_ROM_OFFSET
hex
@@ -98,8 +98,4 @@ config STACK_SIZE
hex
default 0x0003ff00
-config SYS_SDRAM_BASE
- hex "SDRAM base address"
- default 0x01000000
-
endif # BOARD_EMULATION_QEMU_ARMV7
the following patch was just integrated into master:
commit aaaf689007cb6d80d326e5a297899e6719bdac30
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Thu Aug 29 15:57:11 2013 -0700
chromeos: On ARM platforms VBNV lives in the EC
This patch renames the x86 way of doing things to
explicitly mention CMOS (which is not available on
our ARM platforms) and adds an implementation to
get VBNV through the Chrome EC. We might want to
refine this further in the future to allow VBNV
in the EC even on x86 platforms. Will be fixed when
that appears. Also, not all ARM platforms running
ChromeOS might use the Google EC in the future, in
which case this code will need additional work.
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Change-Id: Ice09d0e277dbb131f9ad763e762e8877007db901
Reviewed-on: https://chromium-review.googlesource.com/167540
Reviewed-by: David Hendrix <dhendrix(a)chromium.org>
Tested-by: Stefan Reinauer <reinauer(a)google.com>
Commit-Queue: Stefan Reinauer <reinauer(a)google.com>
(cherry picked from commit 8df6cdbcacb082af88c069ef8b542b44ff21d97a)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6616
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
See http://review.coreboot.org/6616 for details.
-gerrit
the following patch was just integrated into master:
commit b8fad3d02986222fa162d455eca2ffe807b6a15a
Author: Julius Werner <jwerner(a)chromium.org>
Date: Tue Aug 27 15:48:32 2013 -0700
arm: libpayload: Add cache coherent DMA memory definition and management
This patch adds a mechanism to set aside a region of cache-coherent
(i.e. usually uncached) virtual memory, which can be used to communicate
with DMA devices without automatic cache snooping (common on ARM)
without the need of explicit flush/invalidation instructions in the
driver code.
This works by setting aside said region in the (board-specific) page
table setup, as exemplary done in this patch for the Snow and Pit
boards. It uses a new mechanism for adding board-specific Coreboot table
entries to describe this region in an entry with the LB_DMA tag.
Libpayload's memory allocator is enhanced to be able to operate on
distinct types/regions of memory. It provides dma_malloc() and
dma_memalign() functions for use in drivers, which by default just
operate on the same heap as their traditional counterparts. However, if
the Coreboot table parsing code finds a CB_DMA section, further requests
through the dma_xxx() functions will return memory from the region
described therein instead.
Change-Id: Ia9c249249e936bbc3eb76e7b4822af2230ffb186
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167155
(cherry picked from commit d142ccdcd902a9d6ab4d495fbe6cbe85c61a5f01)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6622
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/6622 for details.
-gerrit
the following patch was just integrated into master:
commit 4498f6a6e57aa3bc1ed9449e3ad153b1a60c4eb6
Author: Julius Werner <jwerner(a)chromium.org>
Date: Tue Sep 3 16:44:15 2013 -0700
libpayload: usbhub: Don't clear PSC unless it was set
The current USB hub code always clears the port status change after
checking it, regardless of whether it was set in the first place. Since
this check runs on every poll, it might create a race condition where
the port status changes right between the GET_PORT_STATUS and the
CLEAR_FEATURE(C_PORT_CONNECT), thus clearing the statrus change flag
before it was ever read. Let's add one extra if() to avoid that possible
headache.
Change-Id: Idd46c2199dc6c240bd9ef068fbe70cccc88bac42
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/168098
(cherry picked from commit f7f6f008f701ab3e4a4f785032d8024d676e11cb)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6617
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
See http://review.coreboot.org/6617 for details.
-gerrit
the following patch was just integrated into master:
commit eb623ab2044f77648658f4b0763616f5e1bea57a
Author: Gabe Black <gabeblack(a)google.com>
Date: Sun Oct 6 10:54:53 2013 -0700
tegra124: Implement the monotonic timer by reading the 1us timer register.
It turns out there's a register in tegra which automatically counts at 1us
increments. It's primarily intended for hardware to use (I think to drive
other timers) but we can read it ourselves since a 1us timer is exactly what
we need to support the monotonic timer API.
Change-Id: I68e947944acec7b460e61f42dbb325643a9739e8
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/172044
Reviewed-by: Ronald Minnich <rminnich(a)chromium.org>
Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit 161a39c53404ea0125221bbd54e54996967d6855)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6620
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/6620 for details.
-gerrit
the following patch was just integrated into master:
commit 59ebc6e919b22595a0047d63d70db915f41ae871
Author: Gabe Black <gabeblack(a)google.com>
Date: Sat Sep 28 20:39:21 2013 -0700
tegra124: Add stack related config options to the Kconfig.
Otherwise the stack ends up down at 0 and has 0 bytes.
Change-Id: I0e3c80a0c5b0180d95819ab44829c2a0b527a54d
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/171015
Reviewed-by: Ronald Minnich <rminnich(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit 3e69a477474697bcbc40762ec166e8a515d8b0c2)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6619
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/6619 for details.
-gerrit
the following patch was just integrated into master:
commit 7980b08405d8c3f2c0b3edf6af482c679f2560b2
Author: Gabe Black <gabeblack(a)google.com>
Date: Fri Sep 27 03:06:34 2013 -0700
tegra124: Add some make rules which will wrap the bootblock in the BCT.
These rules slip into the normal bootblock preperation process and use the
cbootimage utility to wrap it in a BCT.
Change-Id: I8cf2a3fb6e9f1d792d536c533d4813acfb550cea
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/170924
Reviewed-by: Gabe Black <gabeblack(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit cf4a9b0712c21b885bb59310671fb87e38abb665)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6618
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/6618 for details.
-gerrit