Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5957
-gerrit
commit fca1674e2df9779981ef46334a1cd24d086a898c
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Sat Jun 7 21:50:21 2014 +0200
[NOTFORMERGE] device/Kconfig: Select native graphics init by default
Just for build testing the native graphics patches.
Change-Id: I47ed328ce8ce3516ad3997978a01d2359d9b1ca8
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
src/device/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 58dcc1b..3d47602 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -32,7 +32,7 @@ config MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
config MAINBOARD_DO_NATIVE_VGA_INIT
bool "Use native graphics initialization"
depends on MAINBOARD_HAS_NATIVE_VGA_INIT
- default n
+ default y
help
Some mainboards, such as the Google Link, allow initializing the display
without the need of a binary only VGA OPROM. Enabling this option may be
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5927
-gerrit
commit 29b8d0f413ba9096463286541c8ed90e9b05ccc8
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Thu Jun 5 22:45:35 2014 +0200
lenovo/x60/i915.c: Place GTT below top of memory
Since commit 17fec8a0 [1]
drm/i915: Use Graphics Base of Stolen Memory on all gen3+
present in the Linux kernel since version 3.12, 3D does not work
anymore [2].
Comparing the graphics registers, in this case that means output of
`intel_reg_dumper`, the vendor Video BIOS is setting the register
PGTBL_CTL/PGETBL_CTL, only documented in the i965 datasheet [3], to
`0x3ffc0001` on a system with 1 GB of RAM, while native graphics init
sets it to `0x3f800001`.
Currently native graphis init sets the GTT right above the base
address of stolen memory. The Video BIOS sets it below the top of
memory. The Linux Intel driver expects it to be below top of memory, so
do it this way, by setting the address to TOM minus the size of the GTT,
which is hardcoded to 256 KiB.
As `PGETBL_CTL` is zero by default, reading its value in the beginning
is not necessary and is only confusing. Make it clear that the code
calculates the value.
There is still an error PTE error reported during boot, but 3D works
with Linux 3.12+ and no user visible problems are shown.
[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=…
[2] https://bugs.freedesktop.org/show_bug.cgi?id=79038
[3] https://01.org/linuxgraphics/sites/default/files/documentation/965_g35_vol_…
Intel ® 965 Express Chipset Family and
Intel ® G35 Express Chipset Graphics Controller
Programmer’s Reference Manual
Volume 1: Graphics Core
Revision 1.0a
Change-Id: I0a5b04c2c5300f5056cb48075aa5804984bc9948
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
src/mainboard/lenovo/x60/i915.c | 16 ++++++++++++----
src/mainboard/lenovo/x60/i915_reg.h | 2 ++
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c
index 529b262..129b89c 100644
--- a/src/mainboard/lenovo/x60/i915.c
+++ b/src/mainboard/lenovo/x60/i915.c
@@ -135,11 +135,19 @@ int gtt_setup(unsigned int mmiobase);
int gtt_setup(unsigned int mmiobase)
{
unsigned long PGETBL_save;
-
- PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED;
+ unsigned long tom;
+
+ /*
+ * The Video BIOS places the GTT right below top of memory.
+ * It is not documented in the Intel 945 datasheet, but the Intel
+ * developers said that it is normally placed there.
+ *
+ * TODO: Add option table value to make the GTT size runtime
+ * configurable.
+ */
+ tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24;
+ PGETBL_save = tom - 256 * KiB;
PGETBL_save |= PGETBL_ENABLED;
-
- PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfffff000;
PGETBL_save |= 2; /* set GTT to 256kb */
write32(mmiobase + GFX_FLSH_CNTL, 0);
diff --git a/src/mainboard/lenovo/x60/i915_reg.h b/src/mainboard/lenovo/x60/i915_reg.h
index 382b822..a12ba55 100644
--- a/src/mainboard/lenovo/x60/i915_reg.h
+++ b/src/mainboard/lenovo/x60/i915_reg.h
@@ -27,6 +27,8 @@
#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
+#define TOLUD 0x9c
+
/*
* The Bridge device's PCI config space has information about the
* fb aperture size and the amount of pre-reserved memory.
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6671
-gerrit
commit 6d0b9c6b18388dd4671ba91229ffec87db913c2a
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Fri Aug 15 07:28:44 2014 +0200
soc/intel/baytrail/Kconfig: Remove empty line at top file
Change-Id: I932e4566ec6313a7f2dbd58784bde71bca12abd7
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
src/soc/intel/baytrail/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 28658dc..f36394e 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -1,4 +1,3 @@
-
config SOC_INTEL_BAYTRAIL
bool
help
the following patch was just integrated into master:
commit a0a3727dbbd7f3ae9f9021e0797ce2fc61d1b79e
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Aug 14 08:35:11 2014 -0500
intel/cpu: rename car.h to romstage.h
This header has nothing to do with cache-as-ram. Therefore, 'car'
is the wrong term to use. It is about providing a prototype for
*romstage*.
Change-Id: Ibc5bc6f3c38e74d6337c12f246846853ceae4743
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/6661
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/6661 for details.
-gerrit
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6670
-gerrit
commit 6bd841cecbd86ef0133396f746ca27253b7c82de
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Fri Aug 15 02:06:00 2014 +0200
lint-stable: Check that modified boards conatin meaningful board_info.txt.
Change-Id: Idd3ff029e16b4b963f13d341dabdc1949c4e9275
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
util/lint/lint-stable-005-board-status | 49 ++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/util/lint/lint-stable-005-board-status b/util/lint/lint-stable-005-board-status
new file mode 100755
index 0000000..33f5a63
--- /dev/null
+++ b/util/lint/lint-stable-005-board-status
@@ -0,0 +1,49 @@
+#!/bin/sh
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Vladimir Serbinenko <phcoder(a)gmail.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+# DESCR: Check that every board has a meaningful board_info.txt
+
+LC_ALL=C export LC_ALL
+for mobodir in $(git diff --name-status |grep -v "^D" |cut -c3- | sed -n 's,^\(src/mainboard/[^/]*/[^/]*\).*$,\1,p'|sort|uniq); do
+ board_info="$mobodir/board_info.txt"
+ if ! [ -f "$board_info" ]; then
+ echo "No $board_info found" >&2
+ exit 1
+ fi
+ clone_of="$(sed -n 's#^Clone of: \(.*\)$#\1#p' < "$board_info")"
+ if [ -s "$clone_of" ] && [ -f "src/mainboard/$clone_of/board_info.txt" ]; then
+ continue
+ fi
+ category="$(sed -n 's#^Category: \(.*\)$#\1#p' < "$board_info")"
+ case "$category" in
+ desktop|server|laptop|half|mini|settop|"eval"|sbc|emulation|misc)
+ ;;
+ "")
+ echo "$board_info contains neither Clone of nor Category" >&2
+ exit 1
+ ;;
+ *)
+ echo "$board_info specifies unknown category '$category'" >&2
+ exit 1
+ ;;
+ esac
+done
+
+exit 0
+
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6669
-gerrit
commit b9a5ea7ebde37d8bfe4ded7386b396a23ffdcb1f
Author: Gabe Black <gabeblack(a)google.com>
Date: Thu Sep 26 16:27:55 2013 -0700
nyan: Add a stub mainboard.
Old-Change-Id: Icdde4cf5e1abb3ae1ad14279ebc129919ba30074
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/170837
Reviewed-by: Gabe Black <gabeblack(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit e9d87534ccacb42d508f1902786470798a2dbaea)
nyan: Add a "special-class" for aggregating BCT files into bct.cfg.
The config file which cbootimage processes to create a BCT could come from
multiple different files, individually selected based on config options,
and/or split up into different files for organizational purposes. This change
adds a special-class which collects those files and concatenates them all
together in a bct.cfg which can be processed more easily by other parts of the
build.
While the BCT files themselves are potentially very board specific, for
instance ones that hold memory timing information, this bit of code which
collects them is not. It has to be in each board file instead of alongside the
CPU, however, to ensure that the special class is set up before another
Makefile tries to use it. If we end up with lots of Tegra based boards which
duplicate this code over and over, we might want to revisit how this works.
Old-Change-Id: I58e1373434f89e69298990ea4643a19d8afdc309
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/170922
Reviewed-by: Gabe Black <gabeblack(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit 3ae44178b7084037a75e16ce161b1432abf4246a)
nyan: Add bct files for nyan.
There's a config option which selects between the emmc and spi config files
depending on what the firmware is intended to boot from. These are copied from
the files installed by the tegra-bct-nyan ebuild, except that the spi config
file has been modified so that there's only one copy of the BCT and so that it
only has one configuration. This is to save space in the final image.
Old-Change-Id: Ibf1b895bb3ed060d394fc6ffcec67b6972bb21e3
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/170923
Reviewed-by: Gabe Black <gabeblack(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit 6bbcffe04e8ae73c86bc05c577a67f909857e1c0)
Squashed three commits required to get nyan building since some patches
were out of order. Added a select to the nyan mainboard Kconfig to have
a rom size of 1024K to match the saved config on the chromium side.
Change-Id: I346dbb02d216adfea9707e40adf0a4d1e0fabf36
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/mainboard/google/Kconfig | 3 +
src/mainboard/google/nyan/Kconfig | 57 +++++
src/mainboard/google/nyan/Makefile.inc | 32 +++
src/mainboard/google/nyan/bct/Makefile.inc | 23 ++
src/mainboard/google/nyan/bct/emmc.cfg | 13 ++
src/mainboard/google/nyan/bct/odmdata.cfg | 1 +
src/mainboard/google/nyan/bct/sdram.cfg | 346 +++++++++++++++++++++++++++++
src/mainboard/google/nyan/bct/spi.cfg | 16 ++
src/mainboard/google/nyan/devicetree.cb | 22 ++
src/mainboard/google/nyan/mainboard.c | 36 +++
src/mainboard/google/nyan/romstage.c | 30 +++
11 files changed, 579 insertions(+)
diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig
index c456b5a..c205f56 100644
--- a/src/mainboard/google/Kconfig
+++ b/src/mainboard/google/Kconfig
@@ -29,6 +29,8 @@ config BOARD_GOOGLE_FALCO
bool "Falco"
config BOARD_GOOGLE_LINK
bool "Link"
+config BOARD_GOOGLE_NYAN
+ bool "Nyan"
config BOARD_GOOGLE_PANTHER
bool "Panther"
config BOARD_GOOGLE_PARROT
@@ -52,6 +54,7 @@ source "src/mainboard/google/bolt/Kconfig"
source "src/mainboard/google/butterfly/Kconfig"
source "src/mainboard/google/falco/Kconfig"
source "src/mainboard/google/link/Kconfig"
+source "src/mainboard/google/nyan/Kconfig"
source "src/mainboard/google/panther/Kconfig"
source "src/mainboard/google/parrot/Kconfig"
source "src/mainboard/google/peppy/Kconfig"
diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig
new file mode 100644
index 0000000..5ac58d3
--- /dev/null
+++ b/src/mainboard/google/nyan/Kconfig
@@ -0,0 +1,57 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+if BOARD_GOOGLE_NYAN
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select SOC_NVIDIA_TEGRA124
+ select BOARD_ROMSIZE_KB_1024
+
+config MAINBOARD_DIR
+ string
+ default google/nyan
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Nyan"
+
+config DRAM_SIZE_MB
+ int
+ default 2048
+
+choice
+ prompt "BCT boot media"
+ default BCT_CFG_SPI
+ help
+ Which boot media to configure the BCT for.
+
+config BCT_CFG_SPI
+ bool "SPI"
+ help
+ Configure the BCT for booting from SPI.
+
+config BCT_CFG_EMMC
+ bool "eMMC"
+ help
+ Configure the BCT for booting from eMMC.
+
+endchoice
+
+endif # BOARD_GOOGLE_NYAN
diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc
new file mode 100644
index 0000000..3cf7dd2
--- /dev/null
+++ b/src/mainboard/google/nyan/Makefile.inc
@@ -0,0 +1,32 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# Add a handler for BCT config files
+$(call add-special-class,bct-cfg)
+bct-cfg-handler= $(eval $(obj)/generated/bct.cfg: $(1)$(2))
+
+$(obj)/generated/bct.cfg:
+ @printf " CAT $(subst $(obj)/,,$(@))\n"
+ cat $^ > $@
+
+subdirs-y += bct
+
+romstage-y += romstage.c
+
+ramstage-y += mainboard.c
diff --git a/src/mainboard/google/nyan/bct/Makefile.inc b/src/mainboard/google/nyan/bct/Makefile.inc
new file mode 100644
index 0000000..2442c53
--- /dev/null
+++ b/src/mainboard/google/nyan/bct/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+bct-cfg-$(CONFIG_BCT_CFG_EMMC) += emmc.cfg
+bct-cfg-$(CONFIG_BCT_CFG_SPI) += spi.cfg
+bct-cfg-y += odmdata.cfg
+bct-cfg-y += sdram.cfg
diff --git a/src/mainboard/google/nyan/bct/emmc.cfg b/src/mainboard/google/nyan/bct/emmc.cfg
new file mode 100644
index 0000000..be8f79f
--- /dev/null
+++ b/src/mainboard/google/nyan/bct/emmc.cfg
@@ -0,0 +1,13 @@
+# Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
+# Distributed under the terms of the GNU General Public License v2
+
+Version = 0x00350001;
+BlockSize = 0x00004000;
+PageSize = 0x00000200;
+PartitionSize = 0x01000000;
+
+DevType[0] = NvBootDevType_Sdmmc;
+DeviceParam[0].SdmmcParams.ClockDivider = 0x00000009;
+DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit;
+DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000;
+DeviceParam[0].SdmmcParams.MultiPageSupport = 0x00000000;
diff --git a/src/mainboard/google/nyan/bct/odmdata.cfg b/src/mainboard/google/nyan/bct/odmdata.cfg
new file mode 100644
index 0000000..d0ab2bf
--- /dev/null
+++ b/src/mainboard/google/nyan/bct/odmdata.cfg
@@ -0,0 +1 @@
+OdmData = 0x80080000;
diff --git a/src/mainboard/google/nyan/bct/sdram.cfg b/src/mainboard/google/nyan/bct/sdram.cfg
new file mode 100644
index 0000000..fa3271a
--- /dev/null
+++ b/src/mainboard/google/nyan/bct/sdram.cfg
@@ -0,0 +1,346 @@
+# CFG Version 11
+# Do not edit. Generated by gen_sdram_cfg V5.0.1. Command:
+# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.082 -dram_board_cfg 10 -fly_by_time_ps 1650
+# -b PM358/PM358_924MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_924Mhz.cfg
+# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.08 ns (924.21 MHz)
+# bkv file: PM358/PM358_924MHz_emc_reg.txt
+SDRAM[0].MemoryType = NvBootMemoryType_Ddr3;
+SDRAM[0].PllMInputDivider = 0x00000001;
+SDRAM[0].PllMFeedbackDivider = 0x0000004d;
+SDRAM[0].PllMStableTime = 0x0000012c;
+SDRAM[0].PllMSetupControl = 0x00000000;
+SDRAM[0].PllMSelectDiv2 = 0x00000000;
+SDRAM[0].PllMPDLshiftPh45 = 0x00000001;
+SDRAM[0].PllMPDLshiftPh90 = 0x00000001;
+SDRAM[0].PllMPDLshiftPh135 = 0x00000001;
+SDRAM[0].PllMKCP = 0x00000000;
+SDRAM[0].PllMKVCO = 0x00000000;
+SDRAM[0].EmcBctSpare0 = 0x00000000;
+SDRAM[0].EmcBctSpare1 = 0x00000000;
+SDRAM[0].EmcBctSpare2 = 0x00000000;
+SDRAM[0].EmcBctSpare3 = 0x00000000;
+SDRAM[0].EmcBctSpare4 = 0x00000000;
+SDRAM[0].EmcBctSpare5 = 0x00000000;
+SDRAM[0].EmcBctSpare6 = 0x00000000;
+SDRAM[0].EmcBctSpare7 = 0x00000000;
+SDRAM[0].EmcBctSpare8 = 0x00000000;
+SDRAM[0].EmcBctSpare9 = 0x00000000;
+SDRAM[0].EmcBctSpare10 = 0x00000000;
+SDRAM[0].EmcBctSpare11 = 0x00000000;
+SDRAM[0].EmcClockSource = 0x80000000;
+SDRAM[0].EmcAutoCalInterval = 0x001fffff;
+SDRAM[0].EmcAutoCalConfig = 0xa1430404;
+SDRAM[0].EmcAutoCalConfig2 = 0x00000000;
+SDRAM[0].EmcAutoCalConfig3 = 0x00000000;
+SDRAM[0].EmcAutoCalWait = 0x00000190;
+SDRAM[0].EmcAdrCfg = 0x00000000;
+SDRAM[0].EmcPinProgramWait = 0x00000001;
+SDRAM[0].EmcPinExtraWait = 0x00000000;
+SDRAM[0].EmcTimingControlWait = 0x00000000;
+SDRAM[0].EmcRc = 0x0000002b;
+SDRAM[0].EmcRfc = 0x000000ef;
+SDRAM[0].EmcRfcSlr = 0x00000000;
+SDRAM[0].EmcRas = 0x0000001e;
+SDRAM[0].EmcRp = 0x0000000b;
+SDRAM[0].EmcR2r = 0x00000000;
+SDRAM[0].EmcW2w = 0x00000000;
+SDRAM[0].EmcR2w = 0x00000008;
+SDRAM[0].EmcW2r = 0x0000000f;
+SDRAM[0].EmcR2p = 0x00000005;
+SDRAM[0].EmcW2p = 0x00000016;
+SDRAM[0].EmcRdRcd = 0x0000000b;
+SDRAM[0].EmcWrRcd = 0x0000000b;
+SDRAM[0].EmcRrd = 0x00000004;
+SDRAM[0].EmcRext = 0x00000002;
+SDRAM[0].EmcWext = 0x00000000;
+SDRAM[0].EmcWdv = 0x00000006;
+SDRAM[0].EmcWdvMask = 0x00000006;
+SDRAM[0].EmcQUse = 0x0000000c;
+SDRAM[0].EmcQuseWidth = 0x00000002;
+SDRAM[0].EmcIbdly = 0x00000000;
+SDRAM[0].EmcEInput = 0x00000002;
+SDRAM[0].EmcEInputDuration = 0x0000000e;
+SDRAM[0].EmcPutermExtra = 0x000a0000;
+SDRAM[0].EmcPutermWidth = 0x00000004;
+SDRAM[0].EmcPutermAdj = 0x00000000;
+SDRAM[0].EmcCdbCntl1 = 0x00000000;
+SDRAM[0].EmcCdbCntl2 = 0x00000000;
+SDRAM[0].EmcCdbCntl3 = 0x00000000;
+SDRAM[0].EmcQRst = 0x00000001;
+SDRAM[0].EmcQSafe = 0x00000015;
+SDRAM[0].EmcRdv = 0x0000001b;
+SDRAM[0].EmcRdvMask = 0x0000001d;
+SDRAM[0].EmcQpop = 0x00000010;
+SDRAM[0].EmcCtt = 0x00000000;
+SDRAM[0].EmcCttDuration = 0x00000004;
+SDRAM[0].EmcRefresh = 0x00001be9;
+SDRAM[0].EmcBurstRefreshNum = 0x00000000;
+SDRAM[0].EmcPreRefreshReqCnt = 0x000006fa;
+SDRAM[0].EmcPdEx2Wr = 0x00000004;
+SDRAM[0].EmcPdEx2Rd = 0x00000015;
+SDRAM[0].EmcPChg2Pden = 0x00000001;
+SDRAM[0].EmcAct2Pden = 0x00000000;
+SDRAM[0].EmcAr2Pden = 0x000000e6;
+SDRAM[0].EmcRw2Pden = 0x0000001b;
+SDRAM[0].EmcTxsr = 0x000000fa;
+SDRAM[0].EmcTxsrDll = 0x00000200;
+SDRAM[0].EmcTcke = 0x00000006;
+SDRAM[0].EmcTckesr = 0x00000007;
+SDRAM[0].EmcTpd = 0x00000006;
+SDRAM[0].EmcTfaw = 0x00000022;
+SDRAM[0].EmcTrpab = 0x00000000;
+SDRAM[0].EmcTClkStable = 0x0000000a;
+SDRAM[0].EmcTClkStop = 0x0000000a;
+SDRAM[0].EmcTRefBw = 0x00001c29;
+SDRAM[0].EmcFbioCfg5 = 0x104ab898;
+SDRAM[0].EmcFbioCfg6 = 0x00000002;
+SDRAM[0].EmcFbioSpare = 0x00000000;
+SDRAM[0].EmcCfgRsv = 0xff00ff00;
+SDRAM[0].EmcMrs = 0x80000f15;
+SDRAM[0].EmcEmrs = 0x80100002;
+SDRAM[0].EmcEmrs2 = 0x80200020;
+SDRAM[0].EmcEmrs3 = 0x80300000;
+SDRAM[0].EmcMrw1 = 0x00000000;
+SDRAM[0].EmcMrw2 = 0x00000000;
+SDRAM[0].EmcMrw3 = 0x00000000;
+SDRAM[0].EmcMrw4 = 0x00000000;
+SDRAM[0].EmcMrwExtra = 0x00000000;
+SDRAM[0].EmcWarmBootMrwExtra = 0x00000000;
+SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000;
+SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000;
+SDRAM[0].EmcMrwResetCommand = 0x00000000;
+SDRAM[0].EmcMrwResetNInitWait = 0x00000000;
+SDRAM[0].EmcMrsWaitCnt = 0x00ce000e;
+SDRAM[0].EmcMrsWaitCnt2 = 0x00ce000e;
+SDRAM[0].EmcCfg = 0x73300000;
+SDRAM[0].EmcCfg2 = 0x000008a5;
+SDRAM[0].EmcCfgPipe = 0x00000000;
+SDRAM[0].EmcDbg = 0x01000c00;
+SDRAM[0].EmcCmdQ = 0x10004408;
+SDRAM[0].EmcMc2EmcQ = 0x06000404;
+SDRAM[0].EmcDynSelfRefControl = 0x800037ed;
+SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001;
+SDRAM[0].EmcCfgDigDll = 0xe00401b1;
+SDRAM[0].EmcCfgDigDllPeriod = 0x00008000;
+SDRAM[0].EmcDevSelect = 0x00000002;
+SDRAM[0].EmcSelDpdCtrl = 0x00040000;
+SDRAM[0].EmcDllXformDqs0 = 0x00000005;
+SDRAM[0].EmcDllXformDqs1 = 0x00000005;
+SDRAM[0].EmcDllXformDqs2 = 0x00000005;
+SDRAM[0].EmcDllXformDqs3 = 0x00000005;
+SDRAM[0].EmcDllXformDqs4 = 0x00000005;
+SDRAM[0].EmcDllXformDqs5 = 0x00000005;
+SDRAM[0].EmcDllXformDqs6 = 0x00000005;
+SDRAM[0].EmcDllXformDqs7 = 0x00000005;
+SDRAM[0].EmcDllXformDqs8 = 0x00000005;
+SDRAM[0].EmcDllXformDqs9 = 0x00000005;
+SDRAM[0].EmcDllXformDqs10 = 0x00000005;
+SDRAM[0].EmcDllXformDqs11 = 0x00000005;
+SDRAM[0].EmcDllXformDqs12 = 0x00000005;
+SDRAM[0].EmcDllXformDqs13 = 0x00000005;
+SDRAM[0].EmcDllXformDqs14 = 0x00000005;
+SDRAM[0].EmcDllXformDqs15 = 0x00000005;
+SDRAM[0].EmcDllXformQUse0 = 0x00000000;
+SDRAM[0].EmcDllXformQUse1 = 0x00000000;
+SDRAM[0].EmcDllXformQUse2 = 0x00000000;
+SDRAM[0].EmcDllXformQUse3 = 0x00000000;
+SDRAM[0].EmcDllXformQUse4 = 0x00000000;
+SDRAM[0].EmcDllXformQUse5 = 0x00000000;
+SDRAM[0].EmcDllXformQUse6 = 0x00000000;
+SDRAM[0].EmcDllXformQUse7 = 0x00000000;
+SDRAM[0].EmcDllXformAddr0 = 0x0000400e;
+SDRAM[0].EmcDllXformAddr1 = 0x0000400e;
+SDRAM[0].EmcDllXformAddr2 = 0x00000000;
+SDRAM[0].EmcDllXformAddr3 = 0x0000400e;
+SDRAM[0].EmcDllXformAddr4 = 0x0000400e;
+SDRAM[0].EmcDllXformAddr5 = 0x00000000;
+SDRAM[0].EmcDllXformQUse8 = 0x00000000;
+SDRAM[0].EmcDllXformQUse9 = 0x00000000;
+SDRAM[0].EmcDllXformQUse10 = 0x00000000;
+SDRAM[0].EmcDllXformQUse11 = 0x00000000;
+SDRAM[0].EmcDllXformQUse12 = 0x00000000;
+SDRAM[0].EmcDllXformQUse13 = 0x00000000;
+SDRAM[0].EmcDllXformQUse14 = 0x00000000;
+SDRAM[0].EmcDllXformQUse15 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000;
+SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000;
+SDRAM[0].EmcDllXformDq0 = 0x00000006;
+SDRAM[0].EmcDllXformDq1 = 0x00000006;
+SDRAM[0].EmcDllXformDq2 = 0x00000006;
+SDRAM[0].EmcDllXformDq3 = 0x00000006;
+SDRAM[0].EmcDllXformDq4 = 0x00000006;
+SDRAM[0].EmcDllXformDq5 = 0x00000006;
+SDRAM[0].EmcDllXformDq6 = 0x00000006;
+SDRAM[0].EmcDllXformDq7 = 0x00000006;
+SDRAM[0].WarmBootWait = 0x00000002;
+SDRAM[0].EmcCttTermCtrl = 0x00000802;
+SDRAM[0].EmcOdtWrite = 0x00000000;
+SDRAM[0].EmcOdtRead = 0x00000000;
+SDRAM[0].EmcZcalInterval = 0x00020000;
+SDRAM[0].EmcZcalWaitCnt = 0x0000004c;
+SDRAM[0].EmcZcalMrwCmd = 0x80000000;
+SDRAM[0].EmcMrsResetDll = 0x00000000;
+SDRAM[0].EmcZcalInitDev0 = 0x80000011;
+SDRAM[0].EmcZcalInitDev1 = 0x00000000;
+SDRAM[0].EmcZcalInitWait = 0x00000001;
+SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003;
+SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab;
+SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000;
+SDRAM[0].EmcZcalWarmBootWait = 0x00000001;
+SDRAM[0].EmcMrsWarmBootEnable = 0x00000001;
+SDRAM[0].EmcMrsResetDllWait = 0x00000000;
+SDRAM[0].EmcMrsExtra = 0x80000f15;
+SDRAM[0].EmcWarmBootMrsExtra = 0x80100002;
+SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000;
+SDRAM[0].EmcMrsDdr2DllReset = 0x00000000;
+SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000;
+SDRAM[0].EmcDdr2Wait = 0x00000000;
+SDRAM[0].EmcClkenOverride = 0x00000000;
+SDRAM[0].McDisExtraSnapLevels = 0x00000000;
+SDRAM[0].EmcExtraRefreshNum = 0x00000002;
+SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000;
+SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003;
+SDRAM[0].PmcVddpSel = 0x00000002;
+SDRAM[0].PmcVddpSelWait = 0x00000002;
+SDRAM[0].PmcDdrPwr = 0x00000003;
+SDRAM[0].PmcDdrCfg = 0x00002002;
+SDRAM[0].PmcIoDpd3Req = 0x4fff2f97;
+SDRAM[0].PmcIoDpd3ReqWait = 0x00000000;
+SDRAM[0].PmcRegShort = 0x00000000;
+SDRAM[0].PmcNoIoPower = 0x00000000;
+SDRAM[0].PmcPorDpdCtrlWait = 0x00000000;
+SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0;
+SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000;
+SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000;
+SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000;
+SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111;
+SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414;
+SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d;
+SDRAM[0].EmcXm2DqsPadCtrl3 = 0x55555520;
+SDRAM[0].EmcXm2DqsPadCtrl4 = 0x003cf3cf;
+SDRAM[0].EmcXm2DqsPadCtrl5 = 0x003cf3cf;
+SDRAM[0].EmcXm2DqsPadCtrl6 = 0x55555500;
+SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990;
+SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000;
+SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000;
+SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085;
+SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000303;
+SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108;
+SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004;
+SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000;
+SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x016eeeee;
+SDRAM[0].EmcAcpdControl = 0x00000000;
+SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120;
+SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067;
+SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102;
+SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253;
+SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175;
+SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120;
+SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032;
+SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276;
+SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615;
+SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145;
+SDRAM[0].EmcDsrVttgenDrv = 0x0606003f;
+SDRAM[0].EmcTxdsrvttgen = 0x00000000;
+SDRAM[0].EmcBgbiasCtl0 = 0x00000000;
+SDRAM[0].McEmemAdrCfg = 0x00000000;
+SDRAM[0].McEmemAdrCfgDev0 = 0x00080303;
+SDRAM[0].McEmemAdrCfgDev1 = 0x00080303;
+SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248;
+SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490;
+SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920;
+SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001;
+SDRAM[0].McEmemCfg = 0x00000800;
+SDRAM[0].McEmemArbCfg = 0x0e00000d;
+SDRAM[0].McEmemArbOutstandingReq = 0x80000040;
+SDRAM[0].McEmemArbTimingRcd = 0x00000005;
+SDRAM[0].McEmemArbTimingRp = 0x00000006;
+SDRAM[0].McEmemArbTimingRc = 0x00000016;
+SDRAM[0].McEmemArbTimingRas = 0x0000000e;
+SDRAM[0].McEmemArbTimingFaw = 0x00000011;
+SDRAM[0].McEmemArbTimingRrd = 0x00000002;
+SDRAM[0].McEmemArbTimingRap2Pre = 0x00000004;
+SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000e;
+SDRAM[0].McEmemArbTimingR2R = 0x00000002;
+SDRAM[0].McEmemArbTimingW2W = 0x00000002;
+SDRAM[0].McEmemArbTimingR2W = 0x00000006;
+SDRAM[0].McEmemArbTimingW2R = 0x00000009;
+SDRAM[0].McEmemArbDaTurns = 0x09060202;
+SDRAM[0].McEmemArbDaCovers = 0x001a1016;
+SDRAM[0].McEmemArbMisc0 = 0x734e2a17;
+SDRAM[0].McEmemArbMisc1 = 0x70000f02;
+SDRAM[0].McEmemArbRing1Throttle = 0x001f0000;
+SDRAM[0].McEmemArbOverride = 0x10000000;
+SDRAM[0].McEmemArbOverride1 = 0x00000000;
+SDRAM[0].McEmemArbRsv = 0xff00ff00;
+SDRAM[0].McClkenOverride = 0x00000000;
+SDRAM[0].McStatControl = 0x00000000;
+SDRAM[0].McDisplaySnapRing = 0x00000003;
+SDRAM[0].McVideoProtectBom = 0xfff00000;
+SDRAM[0].McVideoProtectBomAdrHi = 0x00000000;
+SDRAM[0].McVideoProtectSizeMb = 0x00000000;
+SDRAM[0].McVideoProtectVprOverride = 0xe4bac743;
+SDRAM[0].McVideoProtectVprOverride1 = 0x00000013;
+SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000;
+SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000;
+SDRAM[0].McSecCarveoutBom = 0xfff00000;
+SDRAM[0].McSecCarveoutAdrHi = 0x00000000;
+SDRAM[0].McSecCarveoutSizeMb = 0x00000000;
+SDRAM[0].McVideoProtectWriteAccess = 0x00000000;
+SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000;
+SDRAM[0].EmcCaTrainingEnable = 0x00000000;
+SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df;
+SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f;
+SDRAM[0].SwizzleRankByteEncode = 0x0000006f;
+SDRAM[0].BootRomPatchControl = 0x00000000;
+SDRAM[0].BootRomPatchData = 0x00000000;
+SDRAM[0].McMtsCarveoutBom = 0xfff00000;
+SDRAM[0].McMtsCarveoutAdrHi = 0x00000000;
+SDRAM[0].McMtsCarveoutSizeMb = 0x00000000;
+SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000;
+#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000017;
+#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000001bb;
+#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x006e0038;
+#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x006e0038;
+#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x006e003c;
+#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x006e0090;
+#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x006e0041;
+#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x006e0090;
+#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x006e0041;
+#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049;
+#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x006e0080;
+#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x006e0004;
+#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x006e0004;
+#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016;
+#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x0000006e;
+#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x006e0004;
+#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x006e0019;
+#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x006e0018;
+#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x006e0024;
+#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x006e001b;
+#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x0000006e;
+#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036;
+#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x006e006e;
+#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036;
+#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x006e006e;
+#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff;
+#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029;
+#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x006e006e;
+#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x006e006e;
+#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x006e0065;
+#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x006e001c;
diff --git a/src/mainboard/google/nyan/bct/spi.cfg b/src/mainboard/google/nyan/bct/spi.cfg
new file mode 100644
index 0000000..b348ed8
--- /dev/null
+++ b/src/mainboard/google/nyan/bct/spi.cfg
@@ -0,0 +1,16 @@
+# Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
+# Distributed under the terms of the GNU General Public License v2
+
+Version = 0x00350001;
+BlockSize = 32768;
+PageSize = 2048;
+PartitionSize = 4194304;
+
+Bctcopy = 1;
+
+DevType[0] = NvBootDevType_Spi;
+DeviceParam[0].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
+DeviceParam[0].SpiFlashParams.ClockDivider = 0x16;
+DeviceParam[0].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
+DeviceParam[0].SpiFlashParams.PageSize2kor16k = 0;
+
diff --git a/src/mainboard/google/nyan/devicetree.cb b/src/mainboard/google/nyan/devicetree.cb
new file mode 100644
index 0000000..392a5ae
--- /dev/null
+++ b/src/mainboard/google/nyan/devicetree.cb
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+chip soc/nvidia/tegra124
+ device cpu_cluster 0 on end
+end
diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c
new file mode 100644
index 0000000..9e08021
--- /dev/null
+++ b/src/mainboard/google/nyan/mainboard.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <boot/coreboot_tables.h>
+
+/* this happens after cpu_init where exynos resources are set */
+static void mainboard_init(device_t dev)
+{
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = &mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+ .name = "nyan",
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
new file mode 100644
index 0000000..c52fbd2
--- /dev/null
+++ b/src/mainboard/google/nyan/romstage.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/stages.h>
+#include <cbfs.h>
+#include <console/console.h>
+
+void main(void)
+{
+ void *entry;
+
+ entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
+ stage_exit(entry);
+}
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6659
-gerrit
commit 1999040f9177a0d6d0ad1576ad66a12c2c420852
Author: Gabe Black <gabeblack(a)google.com>
Date: Sun Oct 6 06:13:24 2013 -0700
tegra: Change how tegra124 and tegra include files from each other.
A problem with including the tegra124 directory directly in the include path
is that it makes all headers in that directory first level headers available
everywhere including places that have nothing to do with the SOC, even headers
which were only intended for local use by tegra124 code. This change modifies
things a bit to be more like the way the arch headers are chosen. In the
tegra124 directory, there's an include directory which has an soc subdirectory
in it. That include directory is added to the include path, making it possible
to have headers private to the tegra124. When files specific to whatever tegra
is being built for are needed, you can include <soc/foo.h> and get the version
specific to that particular soc.
Also, the soc.h header file was overhauled to use enums instead of defines, to
consistently name things as far as their prefix (the less cryptic TEGRA instead
of NV_PA) and suffixes like "BASE", and to get rid of values which were
specific to U-Boot which we don't need. Since the only thing in the file were
address constants, I also renamed the file addressmap.h. It would be included
as:
<soc/addressmap.h>
which I think is easy to remember, does what you'd think it does from the
name, and won't conflict with other header files just minding their own
business in some other directory.
Change-Id: I6a1be1ba28417b7103ad8584e6ec5024a7ff4e55
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/172080
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-by: Ronald Minnich <rminnich(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit 2c554f58f9ee18e151e824f01c03eb3f0e907858)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/soc/nvidia/tegra124/Makefile.inc | 2 +-
src/soc/nvidia/tegra124/clock.c | 9 ++--
src/soc/nvidia/tegra124/include/soc/addressmap.h | 60 ++++++++++++++++++++++
src/soc/nvidia/tegra124/soc.h | 64 ------------------------
4 files changed, 66 insertions(+), 69 deletions(-)
diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc
index 0037a69..aa35b48 100644
--- a/src/soc/nvidia/tegra124/Makefile.inc
+++ b/src/soc/nvidia/tegra124/Makefile.inc
@@ -13,7 +13,7 @@ ramstage-y += cbfs.c
ramstage-y += monotonic_timer.c
ramstage-y += timer.c
-INCLUDES += -Isrc/soc/nvidia/tegra124 -Isrc/soc/nvidia
+CPPFLAGS_common += -Isrc/soc/nvidia/tegra124/include/
# We want to grab the bootblock right before it goes into the image and wrap
# it inside a BCT, but ideally we would do that without making special, one
diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c
index 691a6ee..af01b56 100644
--- a/src/soc/nvidia/tegra124/clock.c
+++ b/src/soc/nvidia/tegra124/clock.c
@@ -16,11 +16,12 @@
#include <delay.h>
#include <arch/io.h>
-#include <soc.h>
-#include <clk_rst.h>
-#include <clock.h>
+#include <soc/addressmap.h>
-static struct clk_rst_ctlr *clk_rst = (void *)NV_PA_CLK_RST_BASE;
+#include "clk_rst.h"
+#include "clock.h"
+
+static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
/*
* On poweron, AVP clock source (also called system clock) is set to PLLP_out0
* with frequency set at 1MHz. Before initializing PLLP, we need to move the
diff --git a/src/soc/nvidia/tegra124/include/soc/addressmap.h b/src/soc/nvidia/tegra124/include/soc/addressmap.h
new file mode 100644
index 0000000..edacf15
--- /dev/null
+++ b/src/soc/nvidia/tegra124/include/soc/addressmap.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright 2013 Google Inc.
+ *
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__
+#define __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__
+
+enum {
+ TEGRA_SRAM_BASE = 0x40000000,
+ TEGRA_SRAM_SIZE = 0x20000
+};
+
+enum {
+ TEGRA_ARM_PERIPHBASE = 0x50040000,
+ TEGRA_PG_UP_BASE = 0x60000000,
+ TEGRA_TMRUS_BASE = 0x60005010,
+ TEGRA_CLK_RST_BASE = 0x60006000,
+ TEGRA_FLOW_BASE = 0x60007000,
+ TEGRA_GPIO_BASE = 0x6000D000,
+ TEGRA_EVP_BASE = 0x6000F000,
+ TEGRA_APB_MISC_BASE = 0x70000000,
+ TEGRA_APB_MISC_GP_BASE = TEGRA_APB_MISC_BASE + 0x0800,
+ TEGRA_APB_UARTA_BASE = TEGRA_APB_MISC_BASE + 0x6000,
+ TEGRA_APB_UARTB_BASE = TEGRA_APB_MISC_BASE + 0x6040,
+ TEGRA_APB_UARTC_BASE = TEGRA_APB_MISC_BASE + 0x6200,
+ TEGRA_APB_UARTD_BASE = TEGRA_APB_MISC_BASE + 0x6300,
+ TEGRA_APB_UARTE_BASE = TEGRA_APB_MISC_BASE + 0x6400,
+ TEGRA_NAND_BASE = TEGRA_APB_MISC_BASE + 0x8000,
+ TEGRA_SPI_BASE = TEGRA_APB_MISC_BASE + 0xC380,
+ TEGRA_SLINK1_BASE = TEGRA_APB_MISC_BASE + 0xD400,
+ TEGRA_SLINK2_BASE = TEGRA_APB_MISC_BASE + 0xD600,
+ TEGRA_SLINK3_BASE = TEGRA_APB_MISC_BASE + 0xD800,
+ TEGRA_SLINK4_BASE = TEGRA_APB_MISC_BASE + 0xDA00,
+ TEGRA_SLINK5_BASE = TEGRA_APB_MISC_BASE + 0xDC00,
+ TEGRA_SLINK6_BASE = TEGRA_APB_MISC_BASE + 0xDE00,
+ TEGRA_DVC_BASE = TEGRA_APB_MISC_BASE + 0xD000,
+ TEGRA_PMC_BASE = TEGRA_APB_MISC_BASE + 0xE400,
+ TEGRA_EMC_BASE = TEGRA_APB_MISC_BASE + 0xF400,
+ TEGRA_FUSE_BASE = TEGRA_APB_MISC_BASE + 0xF800,
+ TEGRA_CSITE_BASE = 0x70040000,
+ TEGRA_USB_ADDR_MASK = 0xFFFFC000,
+};
+
+#endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ */
diff --git a/src/soc/nvidia/tegra124/soc.h b/src/soc/nvidia/tegra124/soc.h
deleted file mode 100644
index 7a164b0..0000000
--- a/src/soc/nvidia/tegra124/soc.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
- * Copyright 2013 Google Inc.
- *
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef _TEGRA124_SOC_H
-
-/* AP base physical address of internal SRAM */
-#define NV_PA_BASE_SRAM 0x40000000
-#define NV_PA_BASE_SRAM_SIZE 0x20000
-
-/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
-#define NV_WB_RUN_ADDRESS 0x40020000
-
-#define NV_PA_ARM_PERIPHBASE 0x50040000
-#define NV_PA_PG_UP_BASE 0x60000000
-#define NV_PA_TMRUS_BASE 0x60005010
-#define NV_PA_CLK_RST_BASE 0x60006000
-#define NV_PA_FLOW_BASE 0x60007000
-#define NV_PA_GPIO_BASE 0x6000D000
-#define NV_PA_EVP_BASE 0x6000F000
-#define NV_PA_APB_MISC_BASE 0x70000000
-#define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
-#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
-#define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040)
-#define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200)
-#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300)
-#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
-#define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000)
-#define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
-#define NV_PA_SLINK1_BASE (NV_PA_APB_MISC_BASE + 0xD400)
-#define NV_PA_SLINK2_BASE (NV_PA_APB_MISC_BASE + 0xD600)
-#define NV_PA_SLINK3_BASE (NV_PA_APB_MISC_BASE + 0xD800)
-#define NV_PA_SLINK4_BASE (NV_PA_APB_MISC_BASE + 0xDA00)
-#define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00)
-#define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00)
-#define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000)
-#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
-#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400)
-#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
-#define NV_PA_CSITE_BASE 0x70040000
-#define TEGRA_USB_ADDR_MASK 0xFFFFC000
-
-#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE
-
-#define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */
-#define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */
-
-#endif /* _TEGRA124_SOC_H_ */
the following patch was just integrated into master:
commit b7f1bfcf289f218f05dfb17561a5b868eea65b92
Author: Isaac Christensen <isaac.christensen(a)se-eng.com>
Date: Wed Aug 13 17:29:44 2014 -0600
tegra124: fix Kconfig ARCH settings
The initial commit for tegra124 (396b072) was not updated for the new ARCH settings.
Change-Id: I147bdf289e91031bd0c0a61e6da43e9c1a438f84
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6658
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/6658 for details.
-gerrit
the following patch was just integrated into master:
commit f1d6e7e2cb75c01ff547359c9e601eaeba7c4155
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sat Aug 9 07:16:10 2014 +0200
Move baytrail-specific config to baytrail.
Stop polluting first screen of all boards.
Change-Id: I1ab88075722f7f0d63550010e7c645281603c9c3
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6548
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/6548 for details.
-gerrit
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6657
-gerrit
commit 75a78f9f866c7a82f103485ed5853ea1b96d5344
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Thu Sep 19 16:45:22 2013 -0700
Peppy graphics
Peppy had some issues with FUI. We decided it was time to create
peppy-specific gma.c and i915io.c files. Using yabel and the i915tool,
we generated a replay attack, then interpolated against the slippy
i915io.c to get something working.
Also, in preparation for moving code out of the mainboard gma.c to
generic driver code, we got rid of some hardcodes in the mainboard
gma.c that have no business being there. The worst were the
computation of gmch_[m,n] and it turns out that we had some
long-standing bugs related to confusion about 'bpp'. I've killed the
word bpp everywhere I could because there are at least 3 things that
correspond to bpp. We now have framebuffer, pipe, and panel bpp. The
names are long because I want to avoid all the mistakes we've all been
making in the last year :-) Sadly, that means a lot of changes not just
peppy-related, but they are simple and in a good cause.
The test pattern generation is driven by a global variable in
mainboard/peppy/gma.c. I've found in the past that it's very useful
to have a function like this available, as one can activate it while
using a jtag debugger: halt at the right place in ramstage, set the
variable to 1, continue. It's not enough code to worry about always
including.
The last hard-codes for M and N registers are gone, and the function
to set from generic intel_dp.c code works. To avoid screen trash on a
dev mode boot, which we liked but nobody else did :-), we now take the
time to put a pleasing background color that sort of doubles as a
power LED.
Rough timing is ramstage start is at 2.2, and dev setup is done at
3.3. These new platforms are depressingly slow to boot. Rom init alone
is taking 1.9 seconds. 13 years ago it was 3 seconds from power on to bash
prompt. These CPUs are at least 10x faster and take much longer to get going.
Future work, once we get this through, is to move more functions to the
intel driver, and combine the mainboard i915io.c into the mainboard gma.c.
That separation only existed because i915io.c was generated by a tool, and it
had lots of ugliness. Most ugliness is gone.
Old-Change-Id: I6a6295b423a41e263f82cef33eacb92a14163321
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/170013
Reviewed-by: Stefan Reinauer <reinauer(a)google.com>
Commit-Queue: Ronald Minnich <rminnich(a)chromium.org>
Tested-by: Ronald Minnich <rminnich(a)chromium.org>
Reviewed-by: Furquan Shaikh <furquan.m.shaikh(a)gmail.com>
(cherry picked from commit 8cdaf73e3602e15925859866714db4d5ec6c947d)
snow: Fix a typo in devicetree.cb that was breaking the snow build.
A typo in a recent change broke the snow build.
Old-Change-Id: I93074e68eb3d21510d974fd8e9c63b3947285afd
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/171014
Reviewed-by: Ronald Minnich <rminnich(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit 154876c126a6690930141df178485658533096d2)
Squashed a fix into the initial patch and updated nehalem/gma.c
to have a non-static gtt_poll.
Change-Id: I2f4342c610d87335411da1d6d405171dc80c1f14
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/cpu/samsung/exynos5250/chip.h | 2 +-
src/cpu/samsung/exynos5420/chip.h | 2 +-
src/drivers/intel/gma/i915.h | 3 +-
src/drivers/intel/gma/intel_ddi.c | 4 +-
src/drivers/intel/gma/intel_dp.c | 68 ++---
src/include/edid.h | 22 +-
src/include/vbe.h | 2 +-
src/lib/edid.c | 23 +-
src/mainboard/google/link/i915.c | 2 +-
src/mainboard/google/peppy/Kconfig | 3 +
src/mainboard/google/peppy/Makefile.inc | 2 +
src/mainboard/google/peppy/gma.c | 434 ++++++++++++++++++++++++++++++++
src/mainboard/google/peppy/i915io.c | 144 +++++++++++
src/mainboard/google/peppy/mainboard.h | 25 ++
src/mainboard/google/pit/devicetree.cb | 2 +-
src/mainboard/google/pit/mainboard.c | 2 +-
src/mainboard/google/slippy/gma.c | 6 +-
src/mainboard/google/snow/devicetree.cb | 2 +-
src/mainboard/google/snow/mainboard.c | 2 +-
src/northbridge/intel/haswell/gma.c | 15 +-
src/northbridge/intel/nehalem/gma.c | 2 +-
21 files changed, 698 insertions(+), 69 deletions(-)
diff --git a/src/cpu/samsung/exynos5250/chip.h b/src/cpu/samsung/exynos5250/chip.h
index f244379..c2e7fb5 100644
--- a/src/cpu/samsung/exynos5250/chip.h
+++ b/src/cpu/samsung/exynos5250/chip.h
@@ -34,7 +34,7 @@ struct cpu_samsung_exynos5250_config {
int xres;
int yres;
- int bpp;
+ int framebuffer_bits_per_pixel;
int usb_vbus_gpio;
int usb_hsic_gpio;
diff --git a/src/cpu/samsung/exynos5420/chip.h b/src/cpu/samsung/exynos5420/chip.h
index f2c710d..220a315 100644
--- a/src/cpu/samsung/exynos5420/chip.h
+++ b/src/cpu/samsung/exynos5420/chip.h
@@ -34,7 +34,7 @@ struct cpu_samsung_exynos5420_config {
int xres;
int yres;
- int bpp;
+ int framebuffer_bits_per_pixel;
int usb_vbus_gpio;
int usb_hsic_gpio;
diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h
index 72301e1..e8940a3 100644
--- a/src/drivers/intel/gma/i915.h
+++ b/src/drivers/intel/gma/i915.h
@@ -139,7 +139,7 @@ struct intel_dp {
int port;
int pipe;
int plane;
- int bpp;
+ int pipe_bits_per_pixel;
/* i2c on aux is ... interesting.
* Before you do an i2c cycle, you need to set the address.
* This requires we remember it from one moment to the next.
@@ -272,6 +272,7 @@ int intel_dp_get_lane_align_status(struct intel_dp *intel_dp,
void intel_prepare_ddi(void);
void intel_ddi_set_pipe_settings(struct intel_dp *intel_dp);
+int gtt_poll(u32 reg, u32 mask, u32 value);
void gtt_write(u32 reg, u32 data);
u32 gtt_read(u32 reg);
diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c
index 2b27f6e..e51fb9c 100644
--- a/src/drivers/intel/gma/intel_ddi.c
+++ b/src/drivers/intel/gma/intel_ddi.c
@@ -253,7 +253,7 @@ void intel_ddi_set_pipe_settings(struct intel_dp *intel_dp)
{
u32 val = TRANS_MSA_SYNC_CLK;
- switch (intel_dp->bpp) {
+ switch (intel_dp->pipe_bits_per_pixel) {
case 18:
val |= TRANS_MSA_6_BPC;
break;
@@ -267,7 +267,7 @@ void intel_ddi_set_pipe_settings(struct intel_dp *intel_dp)
val |= TRANS_MSA_12_BPC;
break;
default:
- printk(BIOS_ERR, "Invalid bpp settings %d\n", intel_dp->bpp);
+ printk(BIOS_ERR, "Invalid bpp settings %d\n", intel_dp->pipe_bits_per_pixel);
}
gtt_write(TRANS_MSA_MISC(intel_dp->transcoder),val);
}
diff --git a/src/drivers/intel/gma/intel_dp.c b/src/drivers/intel/gma/intel_dp.c
index 833a4d6..55e57e6 100644
--- a/src/drivers/intel/gma/intel_dp.c
+++ b/src/drivers/intel/gma/intel_dp.c
@@ -260,7 +260,7 @@ int intel_dp_set_bw(struct intel_dp *intel_dp)
int intel_dp_set_lane_count(struct intel_dp *intel_dp)
{
- printk(BIOS_SPEW, "DP_LANE_COUNT_SET");
+ printk(BIOS_SPEW, "DP_LANE_COUNT_SET %d ", intel_dp->lane_count);
return intel_dp_aux_native_write_1(intel_dp,
DP_LANE_COUNT_SET,
intel_dp->lane_count);
@@ -471,7 +471,20 @@ unsigned int roundup_power_of_two(unsigned int n)
static void compute_m_n(unsigned int m, unsigned int n,
unsigned int *ret_m, unsigned int *ret_n)
{
- *ret_n = MIN(roundup_power_of_two(n), DATA_LINK_N_MAX);
+ /* We noticed in the IO operations that
+ * the VBIOS was setting N to DATA_LINK_N_MAX.
+ * This makes sense, actually: the bigger N is, i.e.
+ * the bigger the denominator is, the bigger
+ * the numerator can be, and the more
+ * bits of numerator you get, the better the result.
+ * So, first pick the max of the two powers of two.
+ * And, in the (unlikely) event that you end up with
+ * something bigger than DATA_LINK_N_MAX, catch that
+ * case with a MIN. Note the second case is unlikely,
+ * but we are best off being careful.
+ */
+ *ret_n = MAX(roundup_power_of_two(n), DATA_LINK_N_MAX);
+ *ret_n = MIN(*ret_n, DATA_LINK_N_MAX);
*ret_m = ( (unsigned long long)m * *ret_n) / n;
intel_reduce_m_n_ratio(ret_m, ret_n);
}
@@ -483,7 +496,6 @@ void intel_dp_compute_m_n(unsigned int bits_per_pixel,
struct intel_dp_m_n *m_n)
{
m_n->tu = 64;
-
compute_m_n(bits_per_pixel * pixel_clock,
link_clock * nlanes * 8,
&m_n->gmch_m, &m_n->gmch_n);
@@ -492,35 +504,6 @@ void intel_dp_compute_m_n(unsigned int bits_per_pixel,
&m_n->link_m, &m_n->link_n);
}
-/* not sure. */
-void intel_dp_set_m_n(struct intel_dp *intel_dp);
-
-void
-intel_dp_set_m_n(struct intel_dp *intel_dp)
-{
- int lane_count;
- struct intel_dp_m_n m_n;
- int pipe = intel_dp->pipe;
-
- lane_count = intel_dp->lane_count;
-
- /*
- * Compute the GMCH and Link ratios. The '3' here is
- * the number of bytes_per_pixel post-LUT, which we always
- * set up for 8-bits of R/G/B, or 3 bytes total.
- */
- intel_dp_compute_m_n(intel_dp->bpp, lane_count,
- intel_dp->clock, intel_dp->clock, &m_n);
-
- {
- gtt_write(TRANSDATA_M1(pipe),
- ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |m_n.gmch_m);
- gtt_write(TRANSDATA_N1(pipe),m_n.gmch_n);
- gtt_write(TRANSDPLINK_M1(pipe),m_n.link_m);
- gtt_write(TRANSDPLINK_N1(pipe),m_n.link_n);
- }
-}
-
static void ironlake_edp_pll_off(void);
void
@@ -1791,17 +1774,13 @@ intel_dp_get_max_downspread(struct intel_dp *intel_dp, u8 *max_downspread)
return 1;
}
-void intel_dp_set_m_n_regs(struct intel_dp *intel_dp)
+void intel_dp_set_m_n_regs(struct intel_dp *dp)
{
- gtt_write(PIPE_DATA_M1(intel_dp->transcoder),0x7e4a0000);
- /* gtt_write(0x6f034,0x00800000); */
- /* Write to 0x6f030 has to be 0x7e4ayyyy -- First four hex digits are important.
- However, with our formula we always see values 0x7e43yyyy (1366 panel) and
- 0x7e42yyy (1280 panel) */
- /* gtt_write(PIPE_DATA_M1(intel_dp->transcoder),TU_SIZE(intel_dp->m_n.tu) | intel_dp->m_n.gmch_m); */
- gtt_write(PIPE_DATA_N1(intel_dp->transcoder),intel_dp->m_n.gmch_n);
- gtt_write(PIPE_LINK_M1(intel_dp->transcoder),intel_dp->m_n.link_m);
- gtt_write(PIPE_LINK_N1(intel_dp->transcoder),intel_dp->m_n.link_n);
+ gtt_write(PIPE_DATA_M1(dp->transcoder),
+ TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m);
+ gtt_write(PIPE_DATA_N1(dp->transcoder),dp->m_n.gmch_n);
+ gtt_write(PIPE_LINK_M1(dp->transcoder),dp->m_n.link_m);
+ gtt_write(PIPE_LINK_N1(dp->transcoder),dp->m_n.link_n);
}
void intel_dp_set_resolution(struct intel_dp *intel_dp)
@@ -1826,10 +1805,13 @@ int intel_dp_get_training_pattern(struct intel_dp *intel_dp,
int intel_dp_get_lane_count(struct intel_dp *intel_dp,
u8 *recv)
{
- return intel_dp_aux_native_read_retry(intel_dp,
+ int val = intel_dp_aux_native_read_retry(intel_dp,
DP_LANE_COUNT_SET,
recv,
0);
+ *recv &= DP_LANE_COUNT_MASK;
+ printk(BIOS_SPEW, "Lane count %s:%d\n", val < 0 ? "fail" : "ok", *recv);
+ return val;
}
int intel_dp_get_lane_align_status(struct intel_dp *intel_dp,
diff --git a/src/include/edid.h b/src/include/edid.h
index 4a2f138..867a82f 100644
--- a/src/include/edid.h
+++ b/src/include/edid.h
@@ -35,7 +35,27 @@ struct edid {
unsigned int version[2];
unsigned int nonconformant;
unsigned int type;
- unsigned int bpp;
+ /* These next three things used to all be called bpp.
+ * Merriment ensued. The identifier
+ * 'bpp' is herewith banished from our
+ * Kingdom.
+ */
+ /* How many bits in the framebuffer per pixel.
+ * Under all reasonable circumstances, it's 32.
+ */
+ unsigned int framebuffer_bits_per_pixel;
+ /* On the panel, how many bits per color?
+ * In almost all cases, it's 6 or 8.
+ * The standard allows for much more!
+ */
+ unsigned int panel_bits_per_color;
+ /* On the panel, how many bits per pixel.
+ * On Planet Earth, there are three colors
+ * per pixel, but this is convenient to have here
+ * instead of having 3*panel_bits_per_color
+ * all over the place.
+ */
+ unsigned int panel_bits_per_pixel;
unsigned int xres;
unsigned int yres;
unsigned int voltage;
diff --git a/src/include/vbe.h b/src/include/vbe.h
index 8ad9d2e..009dabd 100644
--- a/src/include/vbe.h
+++ b/src/include/vbe.h
@@ -20,7 +20,7 @@ typedef struct {
u16 screen_width;
u16 screen_height;
u16 screen_linebytes; // bytes per line in framebuffer, may be more than screen_width
- u8 color_depth; // color depth in bpp
+ u8 color_depth; // color depth in bits per pixel
u32 framebuffer_address;
u8 edid_block_zero[128];
} __attribute__ ((__packed__)) screen_info_t;
diff --git a/src/lib/edid.c b/src/lib/edid.c
index 5c2d964..1ad9fea 100644
--- a/src/lib/edid.c
+++ b/src/lib/edid.c
@@ -473,12 +473,18 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension)
* rgb888 (i.e. no alpha, but pixels on 32-bit boundaries)
* The mainboard can modify these if needed, though
* we have yet to see a case where that will happen.
+ * The existing ARM mainboards don't even call this function
+ * so this will not affect them.
*/
- out->bpp = 32;
+ out->framebuffer_bits_per_pixel = 32;
- out->x_resolution = ALIGN(out->ha * ((out->bpp + 7) / 8),64) / (out->bpp/8);
+ out->x_resolution = ALIGN(out->ha *
+ ((out->framebuffer_bits_per_pixel + 7) / 8),
+ 64) / (out->framebuffer_bits_per_pixel/8);
out->y_resolution = out->va;
- out->bytes_per_line = ALIGN(out->ha * ((out->bpp + 7) / 8),64);
+ out->bytes_per_line = ALIGN(out->ha *
+ ((out->framebuffer_bits_per_pixel + 7)/8),
+ 64);
printk(BIOS_SPEW, "Did detailed timing\n");
}
did_detailed_timing = 1;
@@ -1064,7 +1070,8 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
else
printk(BIOS_SPEW, "%d bits per primary color channel\n",
((edid[0x14] & 0x70) >> 3) + 4);
- out->bpp = ((edid[0x14] & 0x70) >> 3) + 4;
+ out->panel_bits_per_color = ((edid[0x14] & 0x70) >> 3) + 4;
+ out->panel_bits_per_pixel = 3*out->panel_bits_per_color;
switch (edid[0x14] & 0x0f) {
case 0x00: printk(BIOS_SPEW, "Digital interface is not defined\n"); break;
@@ -1423,7 +1430,7 @@ void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr)
edid_fb.x_resolution = edid->x_resolution;
edid_fb.y_resolution = edid->y_resolution;
edid_fb.bytes_per_line = edid->bytes_per_line;
- /* In the case of (e.g.) 24bpp, the convention nowadays
+ /* In the case of (e.g.) 24 framebuffer bits per pixel, the convention nowadays
* seems to be to round it up to the nearest reasonable
* boundary, because otherwise the byte-packing is hideous.
* So, for example, in RGB with no alpha, the bytes are still
@@ -1434,8 +1441,8 @@ void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr)
* It's not clear we're covering all cases here, but
* I'm not sure with grahpics you ever can.
*/
- edid_fb.bits_per_pixel = edid->bpp;
- switch(edid->bpp){
+ edid_fb.bits_per_pixel = edid->framebuffer_bits_per_pixel;
+ switch(edid->framebuffer_bits_per_pixel){
case 32:
case 24:
/* packed into 4-byte words */
@@ -1457,7 +1464,7 @@ void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr)
break;
default:
printk(BIOS_SPEW, "%s: unsupported BPP %d\n", __func__,
- edid->bpp);
+ edid->framebuffer_bits_per_pixel);
return;
}
diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c
index 233148c..8d94d36 100644
--- a/src/mainboard/google/link/i915.c
+++ b/src/mainboard/google/link/i915.c
@@ -258,7 +258,7 @@ int i915lightup(const struct northbridge_intel_sandybridge_config *info,
edid_ok = decode_edid((unsigned char *)&link_edid_data,
sizeof(link_edid_data), &edid);
printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok);
- edid.bpp = 32;
+ edid.framebuffer_bits_per_pixel = 32;
htotal = (edid.ha - 1) | ((edid.ha + edid.hbl- 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(HTOTAL(pipe), %08x)\n", htotal);
diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig
index cae34ff..548cd17 100644
--- a/src/mainboard/google/peppy/Kconfig
+++ b/src/mainboard/google/peppy/Kconfig
@@ -18,6 +18,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_CHROMEOS
select EXTERNAL_MRC_BLOB
select MONOTONIC_TIMER_MSR
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select INTEL_DP
+ select INTEL_DDI
config VBOOT_RAMSTAGE_INDEX
hex
diff --git a/src/mainboard/google/peppy/Makefile.inc b/src/mainboard/google/peppy/Makefile.inc
index 21c4c96..193aa0f 100644
--- a/src/mainboard/google/peppy/Makefile.inc
+++ b/src/mainboard/google/peppy/Makefile.inc
@@ -21,6 +21,7 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
romstage-y += chromeos.c
ramstage-y += chromeos.c
+ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += gma.c i915io.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
@@ -49,3 +50,4 @@ $(SPD_BIN): $(SPD_DEPS)
cbfs-files-y += spd.bin
spd.bin-file := $(SPD_BIN)
spd.bin-type := 0xab
+spd.bin-position := 0xfffec000
diff --git a/src/mainboard/google/peppy/gma.c b/src/mainboard/google/peppy/gma.c
new file mode 100644
index 0000000..c03805e
--- /dev/null
+++ b/src/mainboard/google/peppy/gma.c
@@ -0,0 +1,434 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <stdlib.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#include <delay.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+#include "hda_verb.h"
+#include <smbios.h>
+#include <device/pci.h>
+#include <ec/google/chromeec/ec.h>
+#include <cbfs_core.h>
+
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <edid.h>
+#include <drivers/intel/gma/i915.h>
+#include "mainboard.h"
+
+/*
+ * Here is the rough outline of how we bring up the display:
+ * 1. Upon power-on Sink generates a hot plug detection pulse thru HPD
+ * 2. Source determines video mode by reading DPCD receiver capability field
+ * (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD
+ * 0000Dh).
+ * 3. Sink replies DPCD receiver capability field.
+ * 4. Source starts EDID read thru I2C-over-AUX.
+ * 5. Sink replies EDID thru I2C-over-AUX.
+ * 6. Source determines link configuration, such as MAX_LINK_RATE and
+ * MAX_LANE_COUNT. Source also determines which type of eDP Authentication
+ * method to use and writes DPCD link configuration field (DPCD 00100h to
+ * 0010Ah) including eDP configuration set (DPCD 0010Ah).
+ * 7. Source starts link training. Sink does clock recovery and equalization.
+ * 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh).
+ * 9. Sink replies DPCD link status field. If main link is not stable, Source
+ * repeats Step 7.
+ * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video
+ * parameters and recovers stream clock.
+ * 11. Source sends video data.
+ */
+
+/* how many bytes do we need for the framebuffer?
+ * Well, this gets messy. To get an exact answer, we have
+ * to ask the panel, but we'd rather zero the memory
+ * and set up the gtt while the panel powers up. So,
+ * we take a reasonable guess, secure in the knowledge that the
+ * MRC has to overestimate the number of bytes used.
+ * 8 MiB is a very safe guess. There may be a better way later, but
+ * fact is, the initial framebuffer is only very temporary. And taking
+ * a little long is ok; this is done much faster than the AUX
+ * channel is ready for IO.
+ */
+#define FRAME_BUFFER_BYTES (8*MiB)
+/* how many 4096-byte pages do we need for the framebuffer?
+ * There are hard ways to get this, and easy ways:
+ * there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096
+ * on this chip (and in fact every Intel graphics chip we've seen).
+ */
+#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
+
+static unsigned int *mmio;
+static unsigned int graphics;
+static unsigned int physbase;
+
+/* GTT is the Global Translation Table for the graphics pipeline.
+ * It is used to translate graphics addresses to physical
+ * memory addresses. As in the CPU, GTTs map 4K pages.
+ * The setgtt function adds a further bit of flexibility:
+ * it allows you to set a range (the first two parameters) to point
+ * to a physical address (third parameter);the physical address is
+ * incremented by a count (fourth parameter) for each GTT in the
+ * range.
+ * Why do it this way? For ultrafast startup,
+ * we can point all the GTT entries to point to one page,
+ * and set that page to 0s:
+ * memset(physbase, 0, 4096);
+ * setgtt(0, 4250, physbase, 0);
+ * this takes about 2 ms, and is a win because zeroing
+ * the page takes a up to 200 ms.
+ * This call sets the GTT to point to a linear range of pages
+ * starting at physbase.
+ */
+
+#define GTT_PTE_BASE (2 << 20)
+
+int intel_dp_bw_code_to_link_rate(u8 link_bw);
+
+static void
+setgtt(int start, int end, unsigned long base, int inc)
+{
+ int i;
+
+ for(i = start; i < end; i++){
+ u32 word = base + i*inc;
+ /* note: we've confirmed by checking
+ * the values that mrc does no
+ * useful setup before we run this.
+ */
+ gtt_write(GTT_PTE_BASE + i * 4, word|1);
+ gtt_read(GTT_PTE_BASE + i * 4);
+ }
+}
+
+static int i915_init_done = 0;
+
+/* fill the palette. */
+static void palette(void)
+{
+ int i;
+ unsigned long color = 0;
+
+ for(i = 0; i < 256; i++, color += 0x010101){
+ gtt_write(_LGC_PALETTE_A + (i<<2),color);
+ }
+}
+
+/* assumption: the dpcd in the dp is valid. The raw edid has been read
+ * and the translation has been done.
+ */
+void dp_init_dim_regs(struct intel_dp *dp);
+void dp_init_dim_regs(struct intel_dp *dp)
+{
+ struct edid *edid = &(dp->edid);
+
+ /* step 1: get the constants in the dp struct set up. */
+ dp->lane_count = dp->dpcd[DP_MAX_LANE_COUNT]&DP_LANE_COUNT_MASK;
+
+ dp->link_bw = dp->dpcd[DP_MAX_LINK_RATE];
+ dp->clock = intel_dp_bw_code_to_link_rate(dp->link_bw);
+ dp->edid.link_clock = intel_dp_bw_code_to_link_rate(dp->link_bw);
+
+ /* step 2. Do some computation of other stuff. */
+ dp->bytes_per_pixel = dp->pipe_bits_per_pixel/8;
+
+ dp->stride = edid->bytes_per_line;
+
+ dp->htotal = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
+
+ dp->hblank = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
+
+ dp->hsync = (edid->ha + edid->hso - 1) |
+ ((edid->ha + edid->hso + edid->hspw - 1) << 16);
+
+ dp->vtotal = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
+
+ dp->vblank = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
+
+ dp->vsync = (edid->va + edid->vso - 1) |
+ ((edid->va + edid->vso + edid->vspw - 1) << 16);
+
+ /* PIPEASRC is wid-1 x ht-1 */
+ dp->pipesrc = (edid->ha-1)<<16 | (edid->va-1);
+
+ dp->pfa_pos = 0;
+
+ /* XXXXXXXXXXXXXX hard code */
+ dp->pfa_ctl = 0x80800000;
+
+ dp->pfa_sz = (edid->ha << 16) | (edid->va);
+
+ /* step 3. Call the linux code we pulled in. */
+ dp->flags = intel_ddi_calc_transcoder_flags(edid->panel_bits_per_pixel,
+ dp->port,
+ dp->pipe,
+ dp->type,
+ dp->lane_count,
+ dp->pfa_sz,
+ dp->edid.phsync == '+'?1:0,
+ dp->edid.pvsync == '+'?1:0);
+
+ dp->transcoder = intel_ddi_get_transcoder(dp->port,
+ dp->pipe);
+
+ intel_dp_compute_m_n(edid->panel_bits_per_pixel,
+ dp->lane_count,
+ dp->edid.pixel_clock,
+ dp->edid.link_clock,
+ &dp->m_n);
+
+ printk(BIOS_SPEW, "dp->lane_count = 0x%08x\n",dp->lane_count);
+ printk(BIOS_SPEW, "dp->stride = 0x%08x\n",dp->stride);
+ printk(BIOS_SPEW, "dp->htotal = 0x%08x\n", dp->htotal);
+ printk(BIOS_SPEW, "dp->hblank = 0x%08x\n", dp->hblank);
+ printk(BIOS_SPEW, "dp->hsync = 0x%08x\n", dp->hsync);
+ printk(BIOS_SPEW, "dp->vtotal = 0x%08x\n", dp->vtotal);
+ printk(BIOS_SPEW, "dp->vblank = 0x%08x\n", dp->vblank);
+ printk(BIOS_SPEW, "dp->vsync = 0x%08x\n", dp->vsync);
+ printk(BIOS_SPEW, "dp->pipesrc = 0x%08x\n", dp->pipesrc);
+ printk(BIOS_SPEW, "dp->pfa_pos = 0x%08x\n", dp->pfa_pos);
+ printk(BIOS_SPEW, "dp->pfa_ctl = 0x%08x\n", dp->pfa_ctl);
+ printk(BIOS_SPEW, "dp->pfa_sz = 0x%08x\n", dp->pfa_sz);
+ printk(BIOS_SPEW, "dp->link_m = 0x%08x\n", dp->m_n.link_m);
+ printk(BIOS_SPEW, "dp->link_n = 0x%08x\n", dp->m_n.link_n);
+ printk(BIOS_SPEW, "0x6f030 = 0x%08x\n",
+ TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m);
+ printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", dp->m_n.gmch_m);
+ printk(BIOS_SPEW, "0x6f034 = 0x%08x\n", dp->m_n.gmch_n);
+ printk(BIOS_SPEW, "dp->flags = 0x%08x\n", dp->flags);
+}
+
+int intel_dp_bw_code_to_link_rate(u8 link_bw)
+{
+ switch (link_bw) {
+ default:
+ printk(BIOS_ERR,
+ "ERROR: link_bw(%d) is bogus; must be one of 6, 0xa, or 0x14\n",
+ link_bw);
+ case DP_LINK_BW_1_62:
+ return 162000;
+ case DP_LINK_BW_2_7:
+ return 270000;
+ case DP_LINK_BW_5_4:
+ return 540000;
+ }
+}
+
+void mainboard_train_link(struct intel_dp *intel_dp)
+{
+ u8 read_val;
+ u8 link_status[DP_LINK_STATUS_SIZE];
+
+ gtt_write(DP_TP_CTL(intel_dp->port),
+ DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE);
+ gtt_write(DDI_BUF_CTL_A,
+ DDI_BUF_CTL_ENABLE|
+ DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED|0x80000011);
+
+ intel_dp_get_training_pattern(intel_dp, &read_val);
+ intel_dp_set_training_pattern(intel_dp,
+ DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE |
+ DP_SYMBOL_ERROR_COUNT_BOTH);
+
+ intel_dp_set_training_lane0(intel_dp,
+ DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0);
+ intel_dp_get_link_status(intel_dp, link_status);
+
+ gtt_write(DP_TP_CTL(intel_dp->port),
+ DP_TP_CTL_ENABLE |
+ DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT2);
+
+ intel_dp_get_training_pattern(intel_dp, &read_val);
+ intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 |
+ DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
+ intel_dp_get_link_status(intel_dp, link_status);
+ intel_dp_get_lane_align_status(intel_dp, &read_val);
+ intel_dp_get_training_pattern(intel_dp, &read_val);
+ intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE |
+ DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
+}
+
+/* This variable controls whether the test_gfx function below puts up
+ * color bars or not. In previous revs we ifdef'd the test_gfx function out
+ * but it's handy, especially when using a JTAG debugger
+ * to be able to enable and disable a test graphics.
+ */
+int show_test = 0;
+
+static void test_gfx(struct intel_dp *dp)
+{
+ int i;
+
+ if (!show_test)
+ return;
+ /* This is a sanity test code which fills the screen with two bands --
+ green and blue. It is very useful to ensure all the initializations
+ are made right. Thus, to be used only for testing, not otherwise
+ */
+ printk(BIOS_SPEW, "TEST: graphics %p, va %d, ha %d, stride %d\n",
+ (u32 *)graphics, dp->edid.va, dp->edid.ha, dp->stride);
+
+ for (i = 0; i < (dp->edid.va - 4); i++) {
+ u32 *l;
+ int j;
+ u32 tcolor = 0x0ff;
+ for (j = 0; j < (dp->edid.ha-4); j++) {
+ if (j == (dp->edid.ha/2)) {
+ tcolor = 0xff00;
+ }
+ l = (u32*)(graphics + i * dp->stride + j * sizeof(tcolor));
+ memcpy(l,&tcolor,sizeof(tcolor));
+ }
+ }
+ printk(BIOS_SPEW, "sleep 10\n");
+ delay(10);
+}
+
+void mainboard_set_port_clk_dp(struct intel_dp *intel_dp)
+{
+ u32 ddi_pll_sel = 0;
+
+ switch (intel_dp->link_bw) {
+ case DP_LINK_BW_1_62:
+ ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
+ break;
+ case DP_LINK_BW_2_7:
+ ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
+ break;
+ case DP_LINK_BW_5_4:
+ ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
+ break;
+ default:
+ printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw);
+ return;
+ }
+
+ gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel);
+}
+
+int i915lightup(unsigned int pphysbase, unsigned int pmmio,
+ unsigned int pgfx, unsigned int init_fb)
+{
+ int must_cycle_power = 0;
+ struct intel_dp adp, *dp = &adp;
+ int i;
+ int edid_ok;
+ int pixels = FRAME_BUFFER_BYTES/64;
+
+ gtt_write(PCH_PP_CONTROL,0xabcd000f);
+ delay(1);
+ mmio = (void *)pmmio;
+ physbase = pphysbase;
+ graphics = pgfx;
+ printk(BIOS_SPEW,
+ "i915lightup: graphics %p mmio %p"
+ "physbase %08x\n",
+ (void *)graphics, mmio, physbase);
+
+ void runio(struct intel_dp *dp);
+ /* hard codes -- stuff you can only know from the mainboard */
+ dp->gen = 8; // This is gen 8 which we believe is Haswell
+ dp->is_haswell = 1;
+ dp->DP = 0x2;
+ dp->pipe = PIPE_A;
+ dp->port = PORT_A;
+ dp->plane = PLANE_A;
+ dp->pipe_bits_per_pixel = 24;
+ dp->type = INTEL_OUTPUT_EDP;
+ dp->output_reg = DP_A;
+ /* observed from YABEL. */
+ dp->aux_clock_divider = 0xe1;
+ dp->precharge = 3;
+
+ /* CRAP -- needs to be done elsewhere from the device tree. */
+ dp->panel_power_down_delay = 600;
+ dp->panel_power_up_delay = 200;
+ dp->panel_power_cycle_delay = 600;
+
+ /* 1. Normal mode: Set the first page to zero and make
+ all GTT entries point to the same page
+ 2. Developer/Recovery mode: Set up a tasteful color
+ so people know we are alive. */
+ if (init_fb || show_test) {
+ setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
+ memset((void *)graphics, 0x55, FRAME_BUFFER_PAGES*4096);
+ } else {
+ setgtt(0, FRAME_BUFFER_PAGES, physbase, 0);
+ memset((void*)graphics, 0, 4096);
+ }
+
+ dp->address = 0x50;
+
+ if ( !intel_dp_get_dpcd(dp) )
+ goto fail;
+
+ intel_dp_i2c_aux_ch(dp, MODE_I2C_WRITE, 0, NULL);
+ for(dp->edidlen = i = 0; i < sizeof(dp->rawedid); i++){
+ if (intel_dp_i2c_aux_ch(dp, MODE_I2C_READ,
+ 0x50, &dp->rawedid[i]) < 0)
+ break;
+ dp->edidlen++;
+ }
+
+ edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid);
+
+ printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok);
+
+ dp_init_dim_regs(dp);
+
+ printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n",
+ dp->edid.pixel_clock, dp->edid.link_clock);
+
+ intel_ddi_set_pipe_settings(dp);
+
+ runio(dp);
+
+ palette();
+
+ pixels = dp->edid.ha * (dp->edid.va-4) * 4;
+ printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.ha, dp->edid.va);
+ test_gfx(dp);
+
+ set_vbe_mode_info_valid(&dp->edid, graphics);
+ i915_init_done = 1;
+ return 1;
+
+fail:
+ printk(BIOS_SPEW, "Graphics could not be started;");
+ if (0 && must_cycle_power){
+ printk(BIOS_SPEW, "Turn off power and wait ...");
+ gtt_write(PCH_PP_CONTROL,0xabcd0000);
+ udelay(600000);
+ gtt_write(PCH_PP_CONTROL,0xabcd000f);
+ }
+ printk(BIOS_SPEW, "Returning.\n");
+ return 0;
+}
diff --git a/src/mainboard/google/peppy/i915io.c b/src/mainboard/google/peppy/i915io.c
new file mode 100644
index 0000000..693aed5
--- /dev/null
+++ b/src/mainboard/google/peppy/i915io.c
@@ -0,0 +1,144 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright 2013 Google Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; version 2 of the License.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <stdint.h>
+#include <console/console.h>
+#include <delay.h>
+#include <drivers/intel/gma/i915.h>
+#include <arch/io.h>
+#include "mainboard.h"
+
+void runio(struct intel_dp *dp, int verbose);
+void runio(struct intel_dp *dp, int verbose)
+{
+ u8 read_val;
+ gtt_write(DDI_BUF_CTL_A,
+ DDI_BUF_IS_IDLE|DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED
+ |0x00000091);
+
+ intel_prepare_ddi();
+
+ gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
+ gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
+ gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
+
+ gtt_write(DEIIR,0x00008000);
+ intel_dp_wait_reg(DEIIR, 0x00000000);
+ gtt_write(DSPSTRIDE(dp->plane), dp->stride);
+ gtt_write(DSPADDR(dp->plane), 0x00000000);
+
+ printk(BIOS_SPEW, "DP_SET_POWER");
+
+ intel_dp_sink_dpms(dp, 0);
+
+ intel_dp_set_m_n_regs(dp);
+
+ intel_dp_get_max_downspread(dp, &read_val);
+
+ intel_dp_set_resolution(dp);
+
+ gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
+ gtt_write(PIPECONF(dp->transcoder),0x00000000);
+ gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000);
+
+ mainboard_set_port_clk_dp(dp);
+
+ gtt_write(DSPSTRIDE(dp->plane),dp->stride);
+ gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_RGBX888);
+
+ gtt_write(DEIIR,0x00000080);
+ intel_dp_wait_reg(DEIIR, 0x00000000);
+
+ /* There is some reason we removed these three calls from
+ * slippy/gma.c -- I dont remember why!! */
+ gtt_write(PF_WIN_POS(dp->pipe),dp->pfa_pos);
+ gtt_write(PF_CTL(dp->pipe),dp->pfa_ctl);
+ gtt_write(PF_WIN_SZ(dp->pipe),dp->pfa_sz);
+
+ gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags);
+ gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN);
+
+ /* what is this doing? Not sure yet. But we don't seem to be
+ * able to live without it.*/
+ intel_dp_i2c_write(dp, 0x0);
+ intel_dp_i2c_read(dp, &read_val);
+ intel_dp_i2c_write(dp, 0x04);
+ intel_dp_i2c_read(dp, &read_val);
+ intel_dp_i2c_write(dp, 0x7e);
+ intel_dp_i2c_read(dp, &read_val);
+
+ gtt_write(DDI_BUF_CTL_A,
+ DDI_BUF_IS_IDLE|
+ DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED
+ |0x00000091);
+
+ gtt_write(TRANS_DDI_FUNC_CTL_EDP+0x10,0x00000001);
+ gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE |
+ DP_TP_CTL_ENHANCED_FRAME_ENABLE);
+
+ gtt_write(DDI_BUF_CTL_A,
+ DDI_BUF_CTL_ENABLE|
+ /* another undocumented setting. Surprised? */ 0x40000 |
+ DDI_BUF_IS_IDLE|DDI_A_4_LANES|
+ DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED|
+ 0x80040091);
+
+ intel_dp_set_bw(dp);
+
+ intel_dp_set_lane_count(dp);
+
+ mainboard_train_link(dp);
+
+ gtt_write(DP_TP_CTL(dp->port),
+ DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE |
+ DP_TP_CTL_LINK_TRAIN_IDLE);
+
+ gtt_write(DP_TP_CTL(dp->port),
+ DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE |
+ DP_TP_CTL_LINK_TRAIN_NORMAL);
+
+ gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
+ gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
+ gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
+
+ /* some of this is not needed. But with a total lack of docs, well ...*/
+ gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE );
+
+ gtt_write(SDEIIR,0x00000000);
+ gtt_write(DEIIR,0x00000000);
+ gtt_write(DEIIR,0x00008000);
+ intel_dp_wait_reg(DEIIR, 0x00000000);
+
+ gtt_write(DSPSTRIDE(dp->plane),dp->stride);
+ gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
+
+ gtt_write(DEIIR,0x00000080);
+ intel_dp_wait_reg(DEIIR, 0x00000000);
+
+ gtt_write(DSPSTRIDE(dp->plane),dp->stride);
+ gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_RGBX888);
+
+ gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | EDP_BLC_ENABLE | PANEL_POWER_ON);
+
+ gtt_write(SDEIIR,0x00000000);
+ gtt_write(SDEIIR,0x00000000);
+ gtt_write(DEIIR,0x00000000);
+
+}
+
diff --git a/src/mainboard/google/peppy/mainboard.h b/src/mainboard/google/peppy/mainboard.h
new file mode 100644
index 0000000..f47fffd
--- /dev/null
+++ b/src/mainboard/google/peppy/mainboard.h
@@ -0,0 +1,25 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright 2013 Google Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; version 2 of the License.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef __MAINBOARD_H_
+#define __MAINBOARD_H_
+void mainboard_train_link(struct intel_dp *intel_dp);
+void mainboard_set_port_clk_dp(struct intel_dp *intel_dp);
+
+#endif
diff --git a/src/mainboard/google/pit/devicetree.cb b/src/mainboard/google/pit/devicetree.cb
index 3b6cdb9..687b750 100644
--- a/src/mainboard/google/pit/devicetree.cb
+++ b/src/mainboard/google/pit/devicetree.cb
@@ -21,7 +21,7 @@ chip cpu/samsung/exynos5420
device cpu_cluster 0 on end
register "xres" = "1366"
register "yres" = "768"
- register "bpp" = "16"
+ register "framebuffer_bits_per_pixel" = "16"
# complex magic timing!
register "clkval_f" = "2"
register "upper_margin" = "14"
diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c
index 467b9d0..693857c 100644
--- a/src/mainboard/google/pit/mainboard.c
+++ b/src/mainboard/google/pit/mainboard.c
@@ -52,7 +52,7 @@
static struct edid edid = {
.ha = 1366,
.va = 768,
- .bpp = 16,
+ .framebuffer_bits_per_pixel = 16,
.x_resolution = 1366,
.y_resolution = 768,
.bytes_per_line = 2 * 1366
diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c
index 839fa4d..1e19912 100644
--- a/src/mainboard/google/slippy/gma.c
+++ b/src/mainboard/google/slippy/gma.c
@@ -150,7 +150,7 @@ void dp_init_dim_regs(struct intel_dp *dp)
{
struct edid *edid = &(dp->edid);
- dp->bytes_per_pixel = edid->bpp / 8;
+ dp->bytes_per_pixel = edid->framebuffer_bits_per_pixel / 8;
dp->stride = edid->bytes_per_line;
@@ -189,7 +189,7 @@ void dp_init_dim_regs(struct intel_dp *dp)
dp->transcoder = intel_ddi_get_transcoder(dp->port,
dp->pipe);
- intel_dp_compute_m_n(dp->bpp,
+ intel_dp_compute_m_n(dp->pipe_bits_per_pixel,
dp->lane_count,
dp->edid.pixel_clock,
dp->edid.link_clock,
@@ -336,7 +336,7 @@ int i915lightup(unsigned int pphysbase, unsigned int pmmio,
dp->port = PORT_A;
dp->plane = PLANE_A;
dp->clock = 160000;
- dp->bpp = 32;
+ dp->pipe_bits_per_pixel = 32;
dp->type = INTEL_OUTPUT_EDP;
dp->output_reg = DP_A;
/* observed from YABEL. */
diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb
index c14f374..e6ce49d 100644
--- a/src/mainboard/google/snow/devicetree.cb
+++ b/src/mainboard/google/snow/devicetree.cb
@@ -21,7 +21,7 @@ chip cpu/samsung/exynos5250
device cpu_cluster 0 on end
register "xres" = "1366"
register "yres" = "768"
- register "bpp" = "16"
+ register "framebuffer_bits_per_pixel" = "16"
# complex magic timing!
register "clkval_f" = "2"
register "upper_margin" = "14"
diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c
index dfaf81d..bcebac0 100644
--- a/src/mainboard/google/snow/mainboard.c
+++ b/src/mainboard/google/snow/mainboard.c
@@ -53,7 +53,7 @@
static struct edid edid = {
.ha = 1366,
.va = 768,
- .bpp = 16,
+ .framebuffer_bits_per_pixel = 16,
.x_resolution = 1366,
.y_resolution = 768,
.bytes_per_line = 2 * 1366
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 9dfba9a..057d65a 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -28,6 +28,7 @@
#include <drivers/intel/gma/i915.h>
#include <cpu/intel/haswell/haswell.h>
#include <stdlib.h>
+#include <string.h>
#include "chip.h"
#include "haswell.h"
@@ -130,7 +131,10 @@ static struct resource *gtt_res = NULL;
u32 gtt_read(u32 reg)
{
- return read32(gtt_res->base + reg);
+ u32 val;
+ val = read32(gtt_res->base + reg);
+ return val;
+
}
void gtt_write(u32 reg, u32 data)
@@ -157,7 +161,7 @@ static inline void gtt_write_regs(const struct gt_reg *gt)
}
#define GTT_RETRY 1000
-static int gtt_poll(u32 reg, u32 mask, u32 value)
+int gtt_poll(u32 reg, u32 mask, u32 value)
{
unsigned try = GTT_RETRY;
u32 data;
@@ -177,6 +181,13 @@ static void power_well_enable(void)
{
gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE);
gtt_poll(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_STATE, HSW_PWR_WELL_STATE);
+#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
+ /* In the native graphics case, we've got about 20 ms.
+ * after we power up the the AUX channel until we can talk to it.
+ * So get that going right now. We can't turn on the panel, yet, just VDD.
+ */
+ gtt_write(PCH_PP_CONTROL, PCH_PP_UNLOCK| EDP_FORCE_VDD | PANEL_POWER_RESET);
+#endif
}
static void gma_pm_init_pre_vbios(struct device *dev)
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index f76fbc4..a57bf6b 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -289,7 +289,7 @@ static inline void gtt_write_powermeter(const struct gt_powermeter *pm)
}
#define GTT_RETRY 1000
-static int gtt_poll(u32 reg, u32 mask, u32 value)
+int gtt_poll(u32 reg, u32 mask, u32 value)
{
unsigned try = GTT_RETRY;
u32 data;