the following patch was just integrated into master:
commit 5c715ac3c50dd50089ae4d8547e91444874a5a16
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Thu Aug 14 19:23:41 2014 +0200
bootstate: don't use header in romstage code
Change-Id: I0c2943bb0889552dc384d8efb5226cd6982a4d81
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6663
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See http://review.coreboot.org/6663 for details.
-gerrit
the following patch was just integrated into master:
commit 0ed7940c5d0d789ae1394b2a4ab70d8b6924b109
Author: Isaac Christensen <isaac.christensen(a)se-eng.com>
Date: Thu Aug 14 13:08:29 2014 -0600
libpayload: add march flag for armv7
The cache functions for armv7 require 'march=armv7-a' to use
the 'isb' and 'dsb' instructions.
Change-Id: I3b7ad8fc7da8c3167b38fd1a325090fe49e4ca42
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6668
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
See http://review.coreboot.org/6668 for details.
-gerrit
the following patch was just integrated into master:
commit 3efc52fc0801673ee578be825023bfd7ac32b30a
Author: Isaac Christensen <isaac.christensen(a)se-eng.com>
Date: Thu Aug 14 12:23:24 2014 -0600
libpayload: change cb_range to lb_range
Patch 'coreboot_tables: reduce redundant data structures' (1f5487a)
added a new lb_range structure to coreboot and libpayload but the
original chromium patch added cb_range to libpayload instead. A followup
patch 'arm: libpayload: Add cache coherent DMA memory definition
and management' (b8fad3d) used the incorrect cb_range structure but
this wasn't caught since the current verification build doesn't
build libpayload for arm.
Change-Id: I7cedc66a4794bf4daa214f54be6e917f96418ff6
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6665
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See http://review.coreboot.org/6665 for details.
-gerrit
Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6680
-gerrit
commit cf3149df8455e5e059e3c5ac935ddc4447b91350
Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
Date: Fri Aug 15 12:25:28 2014 -0600
AMD Steppe Eagle: Add northbridge HT link ID to pci_ids.h
Add a #define for the HT northbridge link ID into the "known PCI
device IDs" table.
Change-Id: If0a32b2af5df6c20e0fb5af200c06d80fab3637a
Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
---
src/include/device/pci_ids.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 4f15c37..061a11e 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -287,6 +287,7 @@
#define PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT 0x1600
#define PCI_DEVICE_ID_AMD_15H_MODEL_001F_NB_HT 0x1400
#define PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT 0x1536
+#define PCI_DEVICE_ID_AMD_16H_MODEL_003F_NB_HT 0x1566
#define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200
#define PCI_DEVICE_ID_AMD_15H_NB_IOMMU 0x1419
Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6679
-gerrit
commit 095912aba49a57f7c63fea0e394600a00779e702
Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
Date: Fri Aug 15 12:15:33 2014 -0600
AMD Steppe Eagle: CPU files for new SoC
Add the CPU files required to support the Steppe Eagle and Mullins
models of Family 16h SoC processors from AMD. This CPU is based on
the Jaguar core and is similar to Kabini.
Change-Id: Ib48a3f03128f99a1242fe8c157e0e98feb53b1ea
Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
---
src/cpu/amd/agesa/00730F01/Kconfig | 69 +++++++++++++++
src/cpu/amd/agesa/00730F01/Makefile.inc | 29 +++++++
src/cpu/amd/agesa/00730F01/acpi/cpu.asl | 83 ++++++++++++++++++
src/cpu/amd/agesa/00730F01/chip_name.c | 24 ++++++
src/cpu/amd/agesa/00730F01/model_16_init.c | 133 +++++++++++++++++++++++++++++
src/cpu/amd/agesa/Kconfig | 2 +
src/cpu/amd/agesa/Makefile.inc | 1 +
src/include/cpu/x86/lapic_def.h | 4 +
8 files changed, 345 insertions(+)
diff --git a/src/cpu/amd/agesa/00730F01/Kconfig b/src/cpu/amd/agesa/00730F01/Kconfig
new file mode 100644
index 0000000..ccc44d6
--- /dev/null
+++ b/src/cpu/amd/agesa/00730F01/Kconfig
@@ -0,0 +1,69 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+config CPU_AMD_AGESA_00730F01
+ bool
+ select PCI_IO_CFG_EXT
+ select X86_AMD_FIXED_MTRRS
+
+if CPU_AMD_AGESA_00730F01
+
+config CPU_ADDR_BITS
+ int
+ default 40
+
+config CPU_SOCKET_TYPE
+ hex
+ default 0x10
+
+# DDR2 and REG
+config DIMM_SUPPORT
+ hex
+ default 0x0104
+
+config EXT_RT_TBL_SUPPORT
+ bool
+ default n
+
+config EXT_CONF_SUPPORT
+ bool
+ default n
+
+config CBB
+ hex
+ default 0x0
+
+config CDB
+ hex
+ default 0x18
+
+config XIP_ROM_BASE
+ hex
+ default 0xfff80000
+
+config XIP_ROM_SIZE
+ hex
+ default 0x100000
+
+config HIGH_SCRATCH_MEMORY_SIZE
+ hex
+ # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
+ default 0xA1000
+
+endif
diff --git a/src/cpu/amd/agesa/00730F01/Makefile.inc b/src/cpu/amd/agesa/00730F01/Makefile.inc
new file mode 100644
index 0000000..fba2185
--- /dev/null
+++ b/src/cpu/amd/agesa/00730F01/Makefile.inc
@@ -0,0 +1,29 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+ramstage-y += chip_name.c
+ramstage-y += model_16_init.c
+
+subdirs-y += ../../mtrr
+subdirs-y += ../../../x86/tsc
+subdirs-y += ../../../x86/lapic
+subdirs-y += ../../../x86/cache
+subdirs-y += ../../../x86/mtrr
+subdirs-y += ../../../x86/pae
+subdirs-y += ../../../x86/smm
diff --git a/src/cpu/amd/agesa/00730F01/acpi/cpu.asl b/src/cpu/amd/agesa/00730F01/acpi/cpu.asl
new file mode 100644
index 0000000..dc86df5
--- /dev/null
+++ b/src/cpu/amd/agesa/00730F01/acpi/cpu.asl
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+ /*
+ * Processor Object
+ *
+ */
+ Scope (\_PR) { /* define processor scope */
+ Processor(
+ P000, /* name space name */
+ 0, /* Unique number for this processor */
+ 0x810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+
+ Processor(
+ P001, /* name space name */
+ 1, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P002, /* name space name */
+ 2, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P003, /* name space name */
+ 3, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P004, /* name space name */
+ 4, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P005, /* name space name */
+ 5, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P006, /* name space name */
+ 6, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ Processor(
+ P007, /* name space name */
+ 7, /* Unique number for this processor */
+ 0x0810, /* PBLK system I/O address !hardcoded! */
+ 0x06 /* PBLKLEN for boot processor */
+ ) {
+ }
+ } /* End _PR scope */
+
diff --git a/src/cpu/amd/agesa/00730F01/chip_name.c b/src/cpu/amd/agesa/00730F01/chip_name.c
new file mode 100644
index 0000000..7a1c06c
--- /dev/null
+++ b/src/cpu/amd/agesa/00730F01/chip_name.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+
+struct chip_operations cpu_amd_agesa_00730F01_ops = {
+ CHIP_NAME("AMD CPU Family 16h")
+};
diff --git a/src/cpu/amd/agesa/00730F01/model_16_init.c b/src/cpu/amd/agesa/00730F01/model_16_init.c
new file mode 100644
index 0000000..8053fd1
--- /dev/null
+++ b/src/cpu/amd/agesa/00730F01/model_16_init.c
@@ -0,0 +1,133 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/pae.h>
+#include <pc80/mc146818rtc.h>
+#include <cpu/x86/lapic.h>
+
+#include <cpu/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/amdfam16.h>
+#include <arch/acpi.h>
+#if CONFIG_HAVE_ACPI_RESUME
+#include <cpu/amd/agesa/s3_resume.h>
+#endif
+
+static void model_16_init(device_t dev)
+{
+ printk(BIOS_DEBUG, "Model 16 Init.\n");
+
+ u8 i;
+ msr_t msr;
+ int msrno;
+#if CONFIG_LOGICAL_CPUS
+ u32 siblings;
+#endif
+
+ //x86_enable_cache();
+ //amd_setup_mtrrs();
+ //x86_mtrr_check();
+ disable_cache ();
+ /* Enable access to AMD RdDram and WrDram extension bits */
+ msr = rdmsr(SYSCFG_MSR);
+ msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
+ msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
+ wrmsr(SYSCFG_MSR, msr);
+
+ // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs
+ msr.lo = msr.hi = 0;
+ wrmsr (0x259, msr);
+ msr.lo = msr.hi = 0x1e1e1e1e;
+ wrmsr(0x250, msr);
+ wrmsr(0x258, msr);
+ for (msrno = 0x268; msrno <= 0x26f; msrno++)
+ wrmsr (msrno, msr);
+
+ msr = rdmsr(SYSCFG_MSR);
+ msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
+ msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
+ wrmsr(SYSCFG_MSR, msr);
+
+#if CONFIG_HAVE_ACPI_RESUME
+ if (acpi_slp_type == 3)
+ restore_mtrr();
+#endif
+
+ x86_mtrr_check();
+ x86_enable_cache();
+
+ /* zero the machine check error status registers */
+ msr.lo = 0;
+ msr.hi = 0;
+ for (i = 0; i < 6; i++) {
+ wrmsr(MCI_STATUS + (i * 4), msr);
+ }
+
+
+ /* Enable the local cpu apics */
+ setup_lapic();
+
+#if CONFIG_LOGICAL_CPUS
+ siblings = cpuid_ecx(0x80000008) & 0xff;
+
+ if (siblings > 0) {
+ msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
+ msr.lo |= 1 << 28;
+ wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
+
+ msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
+ msr.hi |= 1 << (33 - 32);
+ wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
+ }
+ printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
+#endif
+
+ /* DisableCf8ExtCfg */
+ msr = rdmsr(NB_CFG_MSR);
+ msr.hi &= ~(1 << (46 - 32));
+ wrmsr(NB_CFG_MSR, msr);
+
+
+ /* Write protect SMM space with SMMLOCK. */
+ msr = rdmsr(HWCR_MSR);
+ msr.lo |= (1 << 0);
+ wrmsr(HWCR_MSR, msr);
+}
+
+static struct device_operations cpu_dev_ops = {
+ .init = model_16_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+ { X86_VENDOR_AMD, 0x730f00 }, /* ML-A0, Guess, TODO: */
+ { 0, 0 },
+};
+
+static const struct cpu_driver model_16 __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index fcba0cf..d288fef 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -25,6 +25,7 @@ config CPU_AMD_AGESA
default y if CPU_AMD_AGESA_FAMILY15
default y if CPU_AMD_AGESA_FAMILY15_TN
default y if CPU_AMD_AGESA_FAMILY16_KB
+ default y if CPU_AMD_AGESA_00730F01
default n
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
@@ -84,4 +85,5 @@ source src/cpu/amd/agesa/family14/Kconfig
source src/cpu/amd/agesa/family15/Kconfig
source src/cpu/amd/agesa/family15tn/Kconfig
source src/cpu/amd/agesa/family16kb/Kconfig
+source src/cpu/amd/agesa/00730F01/Kconfig
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
index beba040..800f8e7 100644
--- a/src/cpu/amd/agesa/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -22,6 +22,7 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
+subdirs-$(CONFIG_CPU_AMD_AGESA_00730F01) += 00730F01
romstage-y += s3_resume.c
ramstage-y += s3_resume.c
diff --git a/src/include/cpu/x86/lapic_def.h b/src/include/cpu/x86/lapic_def.h
index f96b53b..2b1ca5a 100644
--- a/src/include/cpu/x86/lapic_def.h
+++ b/src/include/cpu/x86/lapic_def.h
@@ -6,8 +6,12 @@
#define LAPIC_BASE_MSR_ENABLE (1 << 11)
#define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000
+#ifndef LOCAL_APIC_ADDR
#define LOCAL_APIC_ADDR 0xfee00000
+#endif
+#ifndef LAPIC_DEFAULT_BASE
#define LAPIC_DEFAULT_BASE LOCAL_APIC_ADDR
+#endif
#define LAPIC_ID 0x020
#define LAPIC_LVR 0x030