Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6659
-gerrit
commit 56742e6028398869328462b320b83b2d2145b175
Author: Gabe Black <gabeblack(a)google.com>
Date: Sun Oct 6 06:13:24 2013 -0700
tegra: Change how tegra124 and tegra include files from each other.
A problem with including the tegra124 directory directly in the include path
is that it makes all headers in that directory first level headers available
everywhere including places that have nothing to do with the SOC, even headers
which were only intended for local use by tegra124 code. This change modifies
things a bit to be more like the way the arch headers are chosen. In the
tegra124 directory, there's an include directory which has an soc subdirectory
in it. That include directory is added to the include path, making it possible
to have headers private to the tegra124. When files specific to whatever tegra
is being built for are needed, you can include <soc/foo.h> and get the version
specific to that particular soc.
Also, the soc.h header file was overhauled to use enums instead of defines, to
consistently name things as far as their prefix (the less cryptic TEGRA instead
of NV_PA) and suffixes like "BASE", and to get rid of values which were
specific to U-Boot which we don't need. Since the only thing in the file were
address constants, I also renamed the file addressmap.h. It would be included
as:
<soc/addressmap.h>
which I think is easy to remember, does what you'd think it does from the
name, and won't conflict with other header files just minding their own
business in some other directory.
Change-Id: I6a1be1ba28417b7103ad8584e6ec5024a7ff4e55
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/172080
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-by: Ronald Minnich <rminnich(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit 2c554f58f9ee18e151e824f01c03eb3f0e907858)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/soc/nvidia/tegra124/Makefile.inc | 2 +-
src/soc/nvidia/tegra124/clock.c | 9 ++--
src/soc/nvidia/tegra124/include/soc/addressmap.h | 60 ++++++++++++++++++++++
src/soc/nvidia/tegra124/soc.h | 64 ------------------------
4 files changed, 66 insertions(+), 69 deletions(-)
diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc
index 0037a69..aa35b48 100644
--- a/src/soc/nvidia/tegra124/Makefile.inc
+++ b/src/soc/nvidia/tegra124/Makefile.inc
@@ -13,7 +13,7 @@ ramstage-y += cbfs.c
ramstage-y += monotonic_timer.c
ramstage-y += timer.c
-INCLUDES += -Isrc/soc/nvidia/tegra124 -Isrc/soc/nvidia
+CPPFLAGS_common += -Isrc/soc/nvidia/tegra124/include/
# We want to grab the bootblock right before it goes into the image and wrap
# it inside a BCT, but ideally we would do that without making special, one
diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c
index 691a6ee..af01b56 100644
--- a/src/soc/nvidia/tegra124/clock.c
+++ b/src/soc/nvidia/tegra124/clock.c
@@ -16,11 +16,12 @@
#include <delay.h>
#include <arch/io.h>
-#include <soc.h>
-#include <clk_rst.h>
-#include <clock.h>
+#include <soc/addressmap.h>
-static struct clk_rst_ctlr *clk_rst = (void *)NV_PA_CLK_RST_BASE;
+#include "clk_rst.h"
+#include "clock.h"
+
+static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
/*
* On poweron, AVP clock source (also called system clock) is set to PLLP_out0
* with frequency set at 1MHz. Before initializing PLLP, we need to move the
diff --git a/src/soc/nvidia/tegra124/include/soc/addressmap.h b/src/soc/nvidia/tegra124/include/soc/addressmap.h
new file mode 100644
index 0000000..edacf15
--- /dev/null
+++ b/src/soc/nvidia/tegra124/include/soc/addressmap.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright 2013 Google Inc.
+ *
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__
+#define __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__
+
+enum {
+ TEGRA_SRAM_BASE = 0x40000000,
+ TEGRA_SRAM_SIZE = 0x20000
+};
+
+enum {
+ TEGRA_ARM_PERIPHBASE = 0x50040000,
+ TEGRA_PG_UP_BASE = 0x60000000,
+ TEGRA_TMRUS_BASE = 0x60005010,
+ TEGRA_CLK_RST_BASE = 0x60006000,
+ TEGRA_FLOW_BASE = 0x60007000,
+ TEGRA_GPIO_BASE = 0x6000D000,
+ TEGRA_EVP_BASE = 0x6000F000,
+ TEGRA_APB_MISC_BASE = 0x70000000,
+ TEGRA_APB_MISC_GP_BASE = TEGRA_APB_MISC_BASE + 0x0800,
+ TEGRA_APB_UARTA_BASE = TEGRA_APB_MISC_BASE + 0x6000,
+ TEGRA_APB_UARTB_BASE = TEGRA_APB_MISC_BASE + 0x6040,
+ TEGRA_APB_UARTC_BASE = TEGRA_APB_MISC_BASE + 0x6200,
+ TEGRA_APB_UARTD_BASE = TEGRA_APB_MISC_BASE + 0x6300,
+ TEGRA_APB_UARTE_BASE = TEGRA_APB_MISC_BASE + 0x6400,
+ TEGRA_NAND_BASE = TEGRA_APB_MISC_BASE + 0x8000,
+ TEGRA_SPI_BASE = TEGRA_APB_MISC_BASE + 0xC380,
+ TEGRA_SLINK1_BASE = TEGRA_APB_MISC_BASE + 0xD400,
+ TEGRA_SLINK2_BASE = TEGRA_APB_MISC_BASE + 0xD600,
+ TEGRA_SLINK3_BASE = TEGRA_APB_MISC_BASE + 0xD800,
+ TEGRA_SLINK4_BASE = TEGRA_APB_MISC_BASE + 0xDA00,
+ TEGRA_SLINK5_BASE = TEGRA_APB_MISC_BASE + 0xDC00,
+ TEGRA_SLINK6_BASE = TEGRA_APB_MISC_BASE + 0xDE00,
+ TEGRA_DVC_BASE = TEGRA_APB_MISC_BASE + 0xD000,
+ TEGRA_PMC_BASE = TEGRA_APB_MISC_BASE + 0xE400,
+ TEGRA_EMC_BASE = TEGRA_APB_MISC_BASE + 0xF400,
+ TEGRA_FUSE_BASE = TEGRA_APB_MISC_BASE + 0xF800,
+ TEGRA_CSITE_BASE = 0x70040000,
+ TEGRA_USB_ADDR_MASK = 0xFFFFC000,
+};
+
+#endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ */
diff --git a/src/soc/nvidia/tegra124/soc.h b/src/soc/nvidia/tegra124/soc.h
deleted file mode 100644
index 7a164b0..0000000
--- a/src/soc/nvidia/tegra124/soc.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
- * Copyright 2013 Google Inc.
- *
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef _TEGRA124_SOC_H
-
-/* AP base physical address of internal SRAM */
-#define NV_PA_BASE_SRAM 0x40000000
-#define NV_PA_BASE_SRAM_SIZE 0x20000
-
-/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
-#define NV_WB_RUN_ADDRESS 0x40020000
-
-#define NV_PA_ARM_PERIPHBASE 0x50040000
-#define NV_PA_PG_UP_BASE 0x60000000
-#define NV_PA_TMRUS_BASE 0x60005010
-#define NV_PA_CLK_RST_BASE 0x60006000
-#define NV_PA_FLOW_BASE 0x60007000
-#define NV_PA_GPIO_BASE 0x6000D000
-#define NV_PA_EVP_BASE 0x6000F000
-#define NV_PA_APB_MISC_BASE 0x70000000
-#define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
-#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
-#define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040)
-#define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200)
-#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300)
-#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
-#define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000)
-#define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
-#define NV_PA_SLINK1_BASE (NV_PA_APB_MISC_BASE + 0xD400)
-#define NV_PA_SLINK2_BASE (NV_PA_APB_MISC_BASE + 0xD600)
-#define NV_PA_SLINK3_BASE (NV_PA_APB_MISC_BASE + 0xD800)
-#define NV_PA_SLINK4_BASE (NV_PA_APB_MISC_BASE + 0xDA00)
-#define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00)
-#define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00)
-#define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000)
-#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
-#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400)
-#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
-#define NV_PA_CSITE_BASE 0x70040000
-#define TEGRA_USB_ADDR_MASK 0xFFFFC000
-
-#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE
-
-#define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */
-#define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */
-
-#endif /* _TEGRA124_SOC_H_ */
the following patch was just integrated into master:
commit 9665d389e453d852eef4bc4ae3699ee11d15c999
Author: Julius Werner <jwerner(a)chromium.org>
Date: Fri Sep 13 18:21:46 2013 -0700
libpayload: dma_malloc: Prevent warm reboot problems and add debugging
Since the DMA memory is allocated by Coreboot (outside of the payload's
linker script), it won't get zeroed upon loading like the heap.
Therefore, a warm reboot that doesn't reset memory may leave stale
malloc cookies lying around and misinterpret them as memory that is
still in use on the next boot. After several boots this may fill up the
whole DMA memory and lead to OOM conditions.
Therefore, this patch explicitly wipes the first cookie in
init_dma_memory() to prevent that from happening. It also expands the
existing memory allocator debugging code to cover the DMA parts, which
was very helpful in identifying this particular problem.
Change-Id: I6e2083c286ff8ec865b22dd922c39c456944b451
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/169455
Reviewed-by: Stefan Reinauer <reinauer(a)google.com>
(cherry picked from commit 8e5e1784638563b865553125cd5dab1d36a5d2cb)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6645
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See http://review.coreboot.org/6645 for details.
-gerrit
the following patch was just integrated into master:
commit 1f86434227beaf9806de86269f8b42eed817ae3a
Author: Julius Werner <jwerner(a)chromium.org>
Date: Tue Sep 3 17:15:31 2013 -0700
libpayload: xhci: Make XHCI stack usable on ARM
This patch updates the libpayload XHCI stack to run on ARM CPUs (tested
with the DWC3 controller on an Exynos5420). Firstly, it adds support for
64-byte Slot/Endpoint Context sizes. Since the existing context handling
code represented the whole device context as a C struct (whose size has
to be known at compile time), it was necessary to refactor the input and
device context structures to consist of pointers to the actual contexts
instead.
Secondly, it moves all data structures that the xHC accesses through DMA
to cache-coherent memory. With a similar rationale as in the ARM patches
for EHCI, using explicit cache maintenance functions to correctly handle
the actual transfer buffers in all cases is presumably impossible.
Instead this patch also chooses to create a DMA bounce buffer in the
XHCI stack where transfer buffers which are not already cache-coherent
will be copied to/from.
Change-Id: I14e82fffb43b4d52d687b65415f2e33920e088de
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/169453
Reviewed-by: Stefan Reinauer <reinauer(a)google.com>
(cherry picked from commit 1fa9964063cce6cbd87ba68334806dde8aa2354c)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6643
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/6643 for details.
-gerrit
the following patch was just integrated into master:
commit d96541f3fc934fa27b800a07ccf0597bd5a80dd5
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Tue Sep 10 11:02:58 2013 -0700
armv7: mark EABI compatibility symbols as used
These symbols are not used anywhere in our C code, so
when using GCC's link time optimization feature they
will be dropped even though they're needed by libgcc.
Hence we need to mark them as used so GCC does not stumble
and fall over its own guts.
Change-Id: Ib2e9ea2610b57ab8244d5b699dd56025a4f08a01
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/168773
(cherry picked from commit 416ffc880bcf4122b5430fbd9d9547c83886af2f)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6640
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See http://review.coreboot.org/6640 for details.
-gerrit
the following patch was just integrated into master:
commit 509c37e7507c6d68019abb096df0374858f541f5
Author: Julius Werner <jwerner(a)chromium.org>
Date: Wed Aug 28 12:29:28 2013 -0700
libpayload: Make EHCI driver cache-aware
This patch makes the EHCI driver work on ARM platforms which usually do
not support automatic cache snooping. It uses the new DMA memory
mechanism (which needs to be correctly set up in the Coreboot mainboard
code) to allocate all EHCI-internal communication structures in
cache-coherent memory, and cleans/invalidates the externally supplied
transfer buffers in Bulk and Control functions with explicit calls as
necessary.
Old-Change-Id: Ie8a62545d905b7a4fdd2a56b9405774be69779e5
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167339
(cherry picked from commit 322338934add36a5372ffe7d2a45e61a4fdd4a54)
libpayload: ehci: Cache management is hard, let's go copying...
It turns out that my previous commit to make the EHCI stack cache aware
on ARM devices wasn't quite correct, and the problem is actually much
trickier than I thought. After having some fun with more weird transfer
problems that appear/disappear based on stack alignment, this is my
current worst-case threat model that any cache managing implementation
would need to handle correctly:
Some upper layer calls ehci_bulk() with a transfer buffer on its stack.
Due to stack alignment, it happens to start just at the top of a cache
line, so up to 64 - 4 bytes of ehci_bulk's stack will share that line.
ehci_bulk() calls dcache_clean() and initializes the USB transfer.
Between that point and the call to dcache_invalidate() at the end of
ehci_bulk(), any access to the stack variables in that cache line (even
a speculative prefetch) will refetch the line into the cache. Afterwards
any other access to a random memory location that just happens to get
aliased to the same cache line may evict it again, causing the processor
to write out stale data to the transfer buffer and possibly overwrite
data that has already been received over USB.
In short, any dcache_clean/dcache_invalidate-based implementation that
preserves correctness while allowing any arbitrary (non cache-aligned)
memory location as a transfer buffer is presumed to be impossible.
Instead, this patch causes all transfer data to be copied to/from a
cache-coherent bounce buffer. It will still transfer directly if the
supplied buffer is already cache-coherent, which can be used by callers
to optimize their transfers (and is true by default on x86).
Old-Change-Id: I112908410bdbc8ca028d44f2f5d388c529f8057f
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/169231
Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org>
(cherry picked from commit 702dc50f1d56fe206442079fa443437f4336daed)
Squashed the initial commit and a follow up fix.
Change-Id: Idf7e5aa855b4f0221f82fa380a76049f273e4c88
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6633
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/6633 for details.
-gerrit
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6658
-gerrit
commit 46d3d1cb27ec4af0c076f8dee9733de5fad45929
Author: Isaac Christensen <isaac.christensen(a)se-eng.com>
Date: Wed Aug 13 17:29:44 2014 -0600
tegra124: fix Kconfig ARCH settings
The initial commit for tegra124 (396b072) was not updated for the new ARCH settings.
Change-Id: I147bdf289e91031bd0c0a61e6da43e9c1a438f84
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/soc/nvidia/tegra124/Kconfig | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig
index 8a0dee4..17e02e7 100644
--- a/src/soc/nvidia/tegra124/Kconfig
+++ b/src/soc/nvidia/tegra124/Kconfig
@@ -1,5 +1,7 @@
config SOC_NVIDIA_TEGRA124
- depends on ARCH_ARMV7
+ select ARCH_BOOTBLOCK_ARMV7
+ select ARCH_ROMSTAGE_ARMV7
+ select ARCH_RAMSTAGE_ARMV7
bool
default n
the following patch was just integrated into master:
commit e8eb86f570723cc6becf7712b815c41e305bee5a
Author: Gabe Black <gabeblack(a)google.com>
Date: Wed Sep 18 05:37:20 2013 -0700
libpayload: Add in a missing "static".
The readwrite_chunk was private to the usb mass storage driver, but wasn't
marked as static which was upsetting the compiler.
Change-Id: I0ef5c5f96a29f793dd43ff672a939902bad13c45
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/169816
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit 8140e6145b3d072b7f12a924418570022207c065)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6648
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/6648 for details.
-gerrit
the following patch was just integrated into master:
commit ab11a6a94cc4f7d33fb2f8f3c34414e6dc4da255
Author: Idwer Vollering <vidwer(a)gmail.com>
Date: Mon Aug 11 16:09:07 2014 +0200
payloads/external/SeaBIOS: move build directory
Move SeaBIOS' build directory out of build/
This allows the user to delete build/ in the top dir
and keep the built binary in payloads/external/SeaBIOS/seabios/out/
Change-Id: Ia7d515cd7e349beebcd9b62c9d956137acb73c82
Signed-off-by: Idwer Vollering <vidwer(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6460
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/6460 for details.
-gerrit
the following patch was just integrated into master:
commit df6d09d0fb319f5c834b75babad62a0221582fce
Author: Shawn Nematbakhsh <shawnn(a)chromium.org>
Date: Thu Sep 12 18:23:09 2013 -0700
libpayload: Reduce media init timeout to 5 seconds.
Currently, we wait for up to 30 seconds for a device to become ready to
respond to a TEST_UNIT_READY command. In practice, all media devices become
ready much sooner. But, certain devices do not function with libpayload's
USB driver, and always timeout. To provide a better user experience when
booting with such devices, reduce the timeout to 5 seconds.
Change-Id: Icceab99fa266cdf441847627087eaa5de9b88ecc
Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/169209
(cherry picked from commit 9e55204e92adca0476d273565683f211d6803e7a)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6647
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/6647 for details.
-gerrit
the following patch was just integrated into master:
commit 7ecc912b32f3fa1f94c1aadaba275ddb3d5efac5
Author: Shawn Nematbakhsh <shawnn(a)chromium.org>
Date: Thu Sep 12 18:09:39 2013 -0700
libpayload: Increase accuracy of timeout period for media init.
When bringing up media, we claim to wait for up to 30 seconds for a
device to respond to our TEST_UNIT_READY command. Actually, we can wait
far longer because we do not take into account execution delay.
To improve timeout accuracy, make use of gettimeofday(), which calculates
time based upon a CPU counter. This improves the user experience
slightly when certain non-working USB devices are used.
Change-Id: Id9605ecfc0a522d7a0b039fd8eac541232605082
Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/169208
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
(cherry picked from commit 1d3d535db83ff478c512e37f37015b43927b3efc)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6646
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/6646 for details.
-gerrit