coreboot-gerrit August 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: b4cc3b4 lenovo/t530/romstage.c: Trivial - move include to top
by Edward O'Callaghan 23 Aug '14

23 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6750 -gerrit commit b4cc3b4c1389a94a90ece73133869a9c122f952e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 23 14:25:30 2014 +1000 lenovo/t530/romstage.c: Trivial - move include to top Change-Id: I6b80ad0da39e93072e28b48c40e1c71602133e7b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 8880e30..bb4c0a5 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -41,6 +41,7 @@ #include <cpu/x86/msr.h> #include "gpio.h" #include <cbfs.h> +#include <cpu/intel/romstage.h> static void pch_enable_lpc(void) { @@ -109,7 +110,6 @@ static void rcba_config(void) RCBA32(BUC) = 0; } -#include <cpu/intel/romstage.h> void main(unsigned long bist) { int boot_mode = 0;

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Patch set updated for coreboot: eec98a0 lenovo/t530: Make use of gpio.h for gpio configuration
by Edward O'Callaghan 23 Aug '14

23 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6461 -gerrit commit eec98a0a2e8d7526222a79038e367f3aed3f997f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 2 12:58:29 2014 +1000 lenovo/t530: Make use of gpio.h for gpio configuration Rather than using 'outl()' calls directly, update and use gpio.h struct's with the internal southbridge resource allocator to do the write outs. Change-Id: I289e525f34ce74dba2f4d6ab55a30b155beb0e24 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/gpio.h | 143 +++++++++++++++++++++++------------ src/mainboard/lenovo/t530/romstage.c | 14 +--- 2 files changed, 97 insertions(+), 60 deletions(-) diff --git a/src/mainboard/lenovo/t530/gpio.h b/src/mainboard/lenovo/t530/gpio.h index 70e4c09..f741eb3 100644 --- a/src/mainboard/lenovo/t530/gpio.h +++ b/src/mainboard/lenovo/t530/gpio.h @@ -23,6 +23,7 @@ #include "southbridge/intel/bd82x6x/gpio.h" +/* outl(0x3962a5ff, DEFAULT_GPIOBASE + GPIO_USE_SEL); */ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, @@ -32,32 +33,33 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio5 = GPIO_MODE_GPIO, .gpio6 = GPIO_MODE_GPIO, .gpio7 = GPIO_MODE_GPIO, - .gpio8 = GPIO_MODE_GPIO, - .gpio9 = GPIO_MODE_NATIVE, - .gpio10 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_NATIVE, .gpio11 = GPIO_MODE_NATIVE, - .gpio12 = GPIO_MODE_NATIVE, - .gpio13 = GPIO_MODE_GPIO, - .gpio14 = GPIO_MODE_NATIVE, - .gpio15 = GPIO_MODE_GPIO, - .gpio16 = GPIO_MODE_NATIVE, - .gpio17 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_NATIVE, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_NATIVE, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_NATIVE, .gpio18 = GPIO_MODE_NATIVE, .gpio19 = GPIO_MODE_NATIVE, - .gpio20 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_GPIO, .gpio21 = GPIO_MODE_GPIO, - .gpio22 = GPIO_MODE_GPIO, - .gpio23 = GPIO_MODE_NATIVE, - .gpio24 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_NATIVE, .gpio25 = GPIO_MODE_NATIVE, - .gpio26 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, .gpio27 = GPIO_MODE_GPIO, .gpio28 = GPIO_MODE_GPIO, - .gpio29 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, .gpio30 = GPIO_MODE_NATIVE, .gpio31 = GPIO_MODE_NATIVE, }; +/* outl(0x8ebf6aff, DEFAULT_GPIOBASE + GP_IO_SEL); */ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, @@ -93,47 +95,86 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio31 = GPIO_DIR_INPUT }; +/* outl(0x66917ebb, DEFAULT_GPIOBASE + GP_LVL); */ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, - .gpio1 = GPIO_LEVEL_HIGH, - .gpio2 = GPIO_LEVEL_LOW, + .gpio1 = GPIO_LEVEL_LOW, + .gpio2 = GPIO_LEVEL_HIGH, .gpio3 = GPIO_LEVEL_HIGH, .gpio4 = GPIO_LEVEL_HIGH, - .gpio5 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_LOW, .gpio6 = GPIO_LEVEL_HIGH, - .gpio7 = GPIO_LEVEL_HIGH, - .gpio8 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_HIGH, .gpio9 = GPIO_LEVEL_HIGH, .gpio10 = GPIO_LEVEL_HIGH, .gpio11 = GPIO_LEVEL_HIGH, .gpio12 = GPIO_LEVEL_HIGH, .gpio13 = GPIO_LEVEL_HIGH, - .gpio14 = GPIO_LEVEL_HIGH, - .gpio15 = GPIO_LEVEL_LOW, - .gpio16 = GPIO_LEVEL_HIGH, - .gpio17 = GPIO_LEVEL_HIGH, - .gpio18 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_LOW, .gpio19 = GPIO_LEVEL_HIGH, - .gpio20 = GPIO_LEVEL_HIGH, - .gpio21 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, .gpio22 = GPIO_LEVEL_HIGH, - .gpio23 = GPIO_LEVEL_HIGH, - .gpio24 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_HIGH, .gpio25 = GPIO_LEVEL_HIGH, - .gpio26 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_LOW, .gpio27 = GPIO_LEVEL_LOW, - .gpio28 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, .gpio29 = GPIO_LEVEL_HIGH, - .gpio30 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_LOW, .gpio31 = GPIO_LEVEL_LOW, }; +/* Output Control Registers */ +/* outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK); */ +const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_NO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +/* outl(0x00002002, DEFAULT_GPIOBASE + GPI_INV); */ const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, - .gpio6 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; +/* outl(0x02ff08fe, DEFAULT_GPIOBASE + GPIO_USE_SEL2); */ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, @@ -169,10 +210,11 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio63 = GPIO_MODE_NATIVE, }; +/* outl(0x1f47f7fd, DEFAULT_GPIOBASE + GP_IO_SEL2); */ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, - .gpio33 = GPIO_DIR_INPUT, - .gpio34 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, .gpio35 = GPIO_DIR_INPUT, .gpio36 = GPIO_DIR_INPUT, .gpio37 = GPIO_DIR_INPUT, @@ -204,28 +246,29 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio63 = GPIO_DIR_OUTPUT, }; +/* outl(0xffbeff43, DEFAULT_GPIOBASE + GP_LVL2); */ const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_HIGH, - .gpio33 = GPIO_LEVEL_HIGH, + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, .gpio34 = GPIO_LEVEL_LOW, .gpio35 = GPIO_LEVEL_LOW, - .gpio36 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_HIGH, .gpio37 = GPIO_LEVEL_LOW, .gpio38 = GPIO_LEVEL_HIGH, - .gpio39 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_HIGH, .gpio40 = GPIO_LEVEL_HIGH, .gpio41 = GPIO_LEVEL_HIGH, .gpio42 = GPIO_LEVEL_HIGH, .gpio43 = GPIO_LEVEL_HIGH, .gpio44 = GPIO_LEVEL_HIGH, .gpio45 = GPIO_LEVEL_HIGH, - .gpio46 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_LOW, .gpio47 = GPIO_LEVEL_HIGH, .gpio48 = GPIO_LEVEL_HIGH, .gpio49 = GPIO_LEVEL_HIGH, .gpio50 = GPIO_LEVEL_HIGH, .gpio51 = GPIO_LEVEL_HIGH, - .gpio52 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, .gpio53 = GPIO_LEVEL_HIGH, .gpio54 = GPIO_LEVEL_HIGH, .gpio55 = GPIO_LEVEL_HIGH, @@ -236,11 +279,13 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio60 = GPIO_LEVEL_HIGH, .gpio61 = GPIO_LEVEL_HIGH, .gpio62 = GPIO_LEVEL_LOW, - .gpio63 = GPIO_LEVEL_HIGH, + .gpio63 = GPIO_LEVEL_LOW, }; +/* GPIO_USE_SEL3 */ +/* outl(0x000000ff, DEFAULT_GPIOBASE + GPIO_USE_SEL3); */ const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_GPIO, + .gpio64 = GPIO_MODE_GPIO, // native = 0, gpio = 1 .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, .gpio67 = GPIO_MODE_GPIO, @@ -254,8 +299,10 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio75 = GPIO_MODE_NATIVE, }; +/* GP_IO_SEL3 */ +/* outl(0x00000fff, DEFAULT_GPIOBASE + GP_IO_SEL3); */ const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio64 = GPIO_DIR_INPUT, + .gpio64 = GPIO_DIR_INPUT, // out = 0, in = 1 .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, .gpio67 = GPIO_DIR_INPUT, @@ -269,15 +316,17 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio75 = GPIO_DIR_INPUT, }; +/* GP_LVL3 */ +/* outl(0x00000f4f, DEFAULT_GPIOBASE + GP_LVL3); */ const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_HIGH, .gpio65 = GPIO_LEVEL_HIGH, .gpio66 = GPIO_LEVEL_HIGH, .gpio67 = GPIO_LEVEL_HIGH, .gpio68 = GPIO_LEVEL_LOW, - .gpio69 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, // low = 0 .gpio70 = GPIO_LEVEL_HIGH, - .gpio71 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_LOW, .gpio72 = GPIO_LEVEL_HIGH, .gpio73 = GPIO_LEVEL_HIGH, .gpio74 = GPIO_LEVEL_HIGH, @@ -289,8 +338,8 @@ const struct pch_gpio_map t530_gpio_map = { .mode = &pch_gpio_set1_mode, .direction = &pch_gpio_set1_direction, .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, .invert = &pch_gpio_set1_invert, - }, .set2 = { .mode = &pch_gpio_set2_mode, diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index a7d83cc..fb870ce 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -182,19 +182,7 @@ void main(unsigned long bist) pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); -// setup_pch_gpios(&t530_gpio_map); - /* ICH7 GPIOBASE */ - outl(0x3962a5ff, DEFAULT_GPIOBASE + GPIO_USE_SEL); - outl(0x8ebf6aff, DEFAULT_GPIOBASE + GP_IO_SEL); - outl(0x66917ebb, DEFAULT_GPIOBASE + GP_LVL); - outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK); - outl(0x00002002, DEFAULT_GPIOBASE + GPI_INV); - outl(0x02ff08fe, DEFAULT_GPIOBASE + GPIO_USE_SEL2); - outl(0x1f47f7fd, DEFAULT_GPIOBASE + GP_IO_SEL2); - outl(0xffbeff43, DEFAULT_GPIOBASE + GP_LVL2); - outl(0x000000ff, DEFAULT_GPIOBASE + GPIO_USE_SEL3); - outl(0x00000fff, DEFAULT_GPIOBASE + GP_IO_SEL3); - outl(0x00000f4f, DEFAULT_GPIOBASE + GP_LVL3); + setup_pch_gpios(&t530_gpio_map); /* Initialize console device(s) */ console_init();

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Patch set updated for coreboot: 70456d1 lenovo/t530: Be safe by disabling blink gpio hw with a writeout
by Edward O'Callaghan 23 Aug '14

23 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6436 -gerrit commit 70456d153053514484d338448c80854daa284734 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Aug 1 20:30:21 2014 +1000 lenovo/t530: Be safe by disabling blink gpio hw with a writeout This disables the blink hardware as it seems to be in the dump. This is safer as it does not rely on 0 as the reset value when '0x00040000' is the default according to the util/inteltool. As seen: gpiobase+0x0018: 0x00040000 (GPO_BLINK) DIFF Change-Id: Ia1fde108bf3752484f5e991600c435f776af0ced Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/romstage.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 9aa8c4f..a7d83cc 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -187,6 +187,7 @@ void main(unsigned long bist) outl(0x3962a5ff, DEFAULT_GPIOBASE + GPIO_USE_SEL); outl(0x8ebf6aff, DEFAULT_GPIOBASE + GP_IO_SEL); outl(0x66917ebb, DEFAULT_GPIOBASE + GP_LVL); + outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK); outl(0x00002002, DEFAULT_GPIOBASE + GPI_INV); outl(0x02ff08fe, DEFAULT_GPIOBASE + GPIO_USE_SEL2); outl(0x1f47f7fd, DEFAULT_GPIOBASE + GP_IO_SEL2);

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Patch set updated for coreboot: d571f12 lenovo/t530: Use native raminit over MRC blob
by Edward O'Callaghan 23 Aug '14

23 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6394 -gerrit commit d571f1231f551f48c9df0b96608dcee6b7ab5ae1 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jul 29 14:09:27 2014 +1000 lenovo/t530: Use native raminit over MRC blob We now have Native raminit for both sandy/ivybridge introduced in: 7686a56 sandy/ivybridge: Native raminit. Let us make good use of this support over using the Intel MRC blob to initialise memory. USB RCBA configuration data taken between base of 0x3500 up to 0x3600 from `inteltool -r`. Remark: Note the current port is poorly tested at the moment and I am the sole maintainer, however one less blob invites more interest for better support. More to come hopefully. Change-Id: I41d0ef8303dfd369c5565b823e68a6bee09c44f5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/Kconfig | 12 ++-- src/mainboard/lenovo/t530/romstage.c | 134 +++++++++++++---------------------- 2 files changed, 55 insertions(+), 91 deletions(-) diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 473f8b8..efeca4b 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -3,7 +3,7 @@ if BOARD_LENOVO_T530 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 @@ -18,8 +18,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SERIRQ_CONTINUOUS_MODE config HAVE_MRC_CACHE - bool - default n + bool + default y config HAVE_IFD_BIN bool @@ -41,10 +41,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config CACHE_ROM_SIZE_OVERRIDE - hex - default 0x800000 - config IRQ_SLOT_COUNT int default 18 @@ -57,7 +53,7 @@ config USBDEBUG_HCD_INDEX int default 2 -config DRAM_GATE_GPIO +config DRAM_RESET_GATE_GPIO int default 10 diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index fb870ce..749ea31 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -33,7 +33,7 @@ #include <cbmem.h> #include <console/console.h> #include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" +#include "northbridge/intel/sandybridge/raminit_native.h" #include "southbridge/intel/bd82x6x/pch.h" #include "southbridge/intel/bd82x6x/gpio.h" #include <arch/cpu.h> @@ -110,66 +110,57 @@ static void rcba_config(void) RCBA32(BUC) = 0; } +static void init_usb(void) +{ + const u32 rcba_dump[64] = { + /* 3500 */ 0x20000f57, 0x20000f57, 0x2000055b, 0x20000f57, + /* 3510 */ 0x20000f57, 0x20000153, 0x20000153, 0x2000055b, + /* 3520 */ 0x20000153, 0x20000f57, 0x20000153, 0x20000153, + /* 3530 */ 0x20000f51, 0x20000f57, 0x00000000, 0x00000000, + /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050, + /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, + /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00001448, + /* 35a0 */ 0x04000201, 0x00000200, 0x00000000, 0x00000000, + /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + }; + int i; + /* Activate PMBAR. */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ + + /* Unlock registers. */ + outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c); + + for (i = 0; i < 64; i++) + write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), rcba_dump[i]); + + pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); + + /* Relock registers. */ + outw (0x0000, DEFAULT_PMBASE | 0x003c); +} + + void main(unsigned long bist) { - int boot_mode = 0; - int cbmem_was_initted; + int s3resume = 0; u32 pm1_cnt; u16 pm1_sts; + spd_raw_data spd[4]; if (MCHBAR16(SSKPD) == 0xCAFE) { outb(0x6, 0xcf9); hlt (); } - struct pei_data pei_data = { - .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, - .dmibar = DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00,0xA2,0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .gbe_enable = 1, - .ddr3lv_support = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* enabled usb oc pin length */ - { 1, 0, 0x0080 }, /* P0 (left, fan side), OC 0 */ - { 1, 1, 0x0080 }, /* P1 (left touchpad side), OC 1 */ - { 1, 3, 0x0080 }, /* P2: dock, OC 3 */ - { 1, 0, 0x0040 }, /* P3: wwan, no OC */ - { 1, 0, 0x0080 }, /* P4: Wacom tablet on X230t, otherwise empty */ - { 1, 0, 0x0080 }, /* P5: Expresscard, no OC */ - { 0, 0, 0x0000 }, /* P6: Empty */ - { 1, 0, 0x0080 }, /* P7: dock, no OC */ - { 0, 0, 0x0000 }, /* P8: Empty */ - { 1, 5, 0x0080 }, /* P9: Right (EHCI debug), OC 5 */ - { 1, 0, 0x0040 }, /* P10: fingerprint reader, no OC */ - { 1, 0, 0x0040 }, /* P11: bluetooth, no OC. */ - { 1, 0, 0x0040 }, /* P12: wlan, no OC */ - { 1, 0, 0x0080 }, /* P13: webcam, no OC */ - }, - .ddr_refresh_rate_config = 2, /* Force double refresh rate */ - }; - timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); @@ -184,6 +175,8 @@ void main(unsigned long bist) setup_pch_gpios(&t530_gpio_map); + init_usb(); + /* Initialize console device(s) */ console_init(); @@ -205,7 +198,7 @@ void main(unsigned long bist) if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { if (acpi_s3_resume_allowed()) { printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; + s3resume = 1; /* Clear SLP_TYPE. This will break stage2 but * we care for that when we get there. */ @@ -219,31 +212,16 @@ void main(unsigned long bist) /* Enable SPD ROMs and DDR-III DRAM */ enable_smbus(); - /* Prepare USB controller early in S3 resume */ - if (boot_mode == 2) - enable_usb_bar(); - post_code(0x39); post_code(0x3a); - pei_data.boot_mode = boot_mode; timestamp_add_now(TS_BEFORE_INITRAM); - /* MRC.bin has a bug and sometimes halts (instead of reboot?). - */ - if (boot_mode != 2) - { - RCBA32(GCS) = RCBA32(GCS) & ~(1 << 5); /* reset */ - outw((0 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* let timer go */ - } - - sdram_initialize(&pei_data); + memset (spd, 0, sizeof (spd)); + read_spd (&spd[0], 0x50); + read_spd (&spd[2], 0x51); - if (boot_mode != 2) - { - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ - } + init_dram_ddr3 (spd, 1, TCK_800MHZ, s3resume); timestamp_add_now(TS_AFTER_INITRAM); post_code(0x3c); @@ -251,13 +229,7 @@ void main(unsigned long bist) rcba_config(); post_code(0x3d); - quick_ram_check(); - post_code(0x3e); - MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_recovery(boot_mode==2); - if (boot_mode!=2) - save_mrc_data(&pei_data); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so @@ -267,18 +239,14 @@ void main(unsigned long bist) *(u32 *)CBMEM_BOOT_MODE = 0; *(u32 *)CBMEM_RESUME_BACKUP = 0; - if ((boot_mode == 2) && cbmem_was_initted) { + if (s3resume) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; + *(u32 *)CBMEM_BOOT_MODE = 2; *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; } /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { - /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - hlt(); } else { pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); }

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Patch set updated for coreboot: 6be2891 lenovo/t530: Use GPIO defines specified in bd82x6x/pch.h header
by Edward O'Callaghan 23 Aug '14

23 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6435 -gerrit commit 6be28915e30e58ce6baeb3dc968277626da576e5 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Aug 1 20:29:40 2014 +1000 lenovo/t530: Use GPIO defines specified in bd82x6x/pch.h header Use defines of offsets rather than hard coded values. Change-Id: Id2471cd22aa402d74163473e48f86af9789cdaa7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/romstage.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index bb4c0a5..9aa8c4f 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -183,16 +183,17 @@ void main(unsigned long bist) pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); // setup_pch_gpios(&t530_gpio_map); - outl(0x3962a5ff, DEFAULT_GPIOBASE); - outl(0x8ebf6aff, DEFAULT_GPIOBASE + 4); - outl(0x66917ebb, DEFAULT_GPIOBASE + 0xc); - outl(0x00002002, DEFAULT_GPIOBASE + 0x2c); - outl(0x02ff08fe, DEFAULT_GPIOBASE + 0x30); - outl(0x1f47f7fd, DEFAULT_GPIOBASE + 0x34); - outl(0xffbeff43, DEFAULT_GPIOBASE + 0x38); - outl(0x000000ff, DEFAULT_GPIOBASE + 0x40); - outl(0x00000fff, DEFAULT_GPIOBASE + 0x44); - outl(0x00000f4f, DEFAULT_GPIOBASE + 0x48); + /* ICH7 GPIOBASE */ + outl(0x3962a5ff, DEFAULT_GPIOBASE + GPIO_USE_SEL); + outl(0x8ebf6aff, DEFAULT_GPIOBASE + GP_IO_SEL); + outl(0x66917ebb, DEFAULT_GPIOBASE + GP_LVL); + outl(0x00002002, DEFAULT_GPIOBASE + GPI_INV); + outl(0x02ff08fe, DEFAULT_GPIOBASE + GPIO_USE_SEL2); + outl(0x1f47f7fd, DEFAULT_GPIOBASE + GP_IO_SEL2); + outl(0xffbeff43, DEFAULT_GPIOBASE + GP_LVL2); + outl(0x000000ff, DEFAULT_GPIOBASE + GPIO_USE_SEL3); + outl(0x00000fff, DEFAULT_GPIOBASE + GP_IO_SEL3); + outl(0x00000f4f, DEFAULT_GPIOBASE + GP_LVL3); /* Initialize console device(s) */ console_init();

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Patch set updated for coreboot: 559201e lenovo/t530: Use GPIO defines specified in bd82x6x/pch.h header
by Edward O'Callaghan 23 Aug '14

23 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6435 -gerrit commit 559201e47425559122a186a776076d887b00c274 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Aug 1 20:29:40 2014 +1000 lenovo/t530: Use GPIO defines specified in bd82x6x/pch.h header Use defines of offsets rather than hard coded values. Change-Id: Id2471cd22aa402d74163473e48f86af9789cdaa7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/romstage.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 8880e30..29eee3e 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -183,16 +183,17 @@ void main(unsigned long bist) pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); // setup_pch_gpios(&t530_gpio_map); - outl(0x3962a5ff, DEFAULT_GPIOBASE); - outl(0x8ebf6aff, DEFAULT_GPIOBASE + 4); - outl(0x66917ebb, DEFAULT_GPIOBASE + 0xc); - outl(0x00002002, DEFAULT_GPIOBASE + 0x2c); - outl(0x02ff08fe, DEFAULT_GPIOBASE + 0x30); - outl(0x1f47f7fd, DEFAULT_GPIOBASE + 0x34); - outl(0xffbeff43, DEFAULT_GPIOBASE + 0x38); - outl(0x000000ff, DEFAULT_GPIOBASE + 0x40); - outl(0x00000fff, DEFAULT_GPIOBASE + 0x44); - outl(0x00000f4f, DEFAULT_GPIOBASE + 0x48); + /* ICH7 GPIOBASE */ + outl(0x3962a5ff, DEFAULT_GPIOBASE + GPIO_USE_SEL); + outl(0x8ebf6aff, DEFAULT_GPIOBASE + GP_IO_SEL); + outl(0x66917ebb, DEFAULT_GPIOBASE + GP_LVL); + outl(0x00002002, DEFAULT_GPIOBASE + GPI_INV); + outl(0x02ff08fe, DEFAULT_GPIOBASE + GPIO_USE_SEL2); + outl(0x1f47f7fd, DEFAULT_GPIOBASE + GP_IO_SEL2); + outl(0xffbeff43, DEFAULT_GPIOBASE + GP_LVL2); + outl(0x000000ff, DEFAULT_GPIOBASE + GPIO_USE_SEL3); + outl(0x00000fff, DEFAULT_GPIOBASE + GP_IO_SEL3); + outl(0x00000f4f, DEFAULT_GPIOBASE + GP_LVL3); /* Initialize console device(s) */ console_init();

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Patch set updated for coreboot: 9c31d0b lenovo/t530: Use native LVDS gfx init
by Edward O'Callaghan 23 Aug '14

23 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6395 -gerrit commit 9c31d0b6c86b3ebd88357a030125e75a4d750ea6 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jul 29 14:42:26 2014 +1000 lenovo/t530: Use native LVDS gfx init As introduced in: 1783a3c ivybridge: LVDS gfx init. Change-Id: I2e3b56a2a3d1ede08a704b839cc11fe6d685cf5b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/Kconfig | 6 ++++++ src/mainboard/lenovo/t530/devicetree.cb | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index efeca4b..76c36c1 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -13,6 +13,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER + select EARLY_CBMEM_INIT + select VGA + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + select IVYBRIDGE_LVDS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 6a09004..d9b751a 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -10,6 +10,12 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms + register "gpu_use_spread_spectrum_clock" = "1" + register "gpu_lvds_dual_channel" = "0" + register "gpu_link_frequency_270_mhz" = "1" + register "gpu_lvds_num_lanes" = "1" + register "gpu_cpu_backlight" = "0x1155" + register "gpu_pch_backlight" = "0x11551155" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989

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Patch merged into coreboot/master: becf739 lenovo/t520: Remove empty smi.h
by gerrit＠coreboot.org 23 Aug '14

23 Aug '14

the following patch was just integrated into master: commit becf739b2ea49529d4c161804fe4d469b4e4ff6c Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Fri Aug 22 15:22:20 2014 +0200 lenovo/t520: Remove empty smi.h Change-Id: I60fa19b72f91f16db5f354aeec631f661e3494d3 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Reviewed-on: http://review.coreboot.org/6736 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6736 for details. -gerrit

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Patch merged into coreboot/master: 6d790f7 lenovo/t520: Fix ExpressCard hotplug
by gerrit＠coreboot.org 23 Aug '14

23 Aug '14

the following patch was just integrated into master: commit 6d790f730500ce6a79aeb9e4d57b0ea4c9e9ee69 Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Fri Aug 22 15:10:49 2014 +0200 lenovo/t520: Fix ExpressCard hotplug Thinkpad T520 ExpressCard Slot PCIe lanes are connected to port 4. Tested with Serial Port Card. Information read from schematic / lspci Change-Id: I459943d427578d135f9aed1aa66da269ddfeee87 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Reviewed-on: http://review.coreboot.org/6735 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6735 for details. -gerrit

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Patch merged into coreboot/master: d2da65e superio/smsc/sch4037: Cleanup and fix .c inclusion
by gerrit＠coreboot.org 23 Aug '14

23 Aug '14

the following patch was just integrated into master: commit d2da65e3abd93840c81fbc30c6488b625baf359b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Aug 6 21:32:50 2014 +1000 superio/smsc/sch4037: Cleanup and fix .c inclusion Clean up both ram and rom stage support and fix board to match. Change-Id: I55e3e7338c0551f0fb663eb9707f16ecdc1aca35 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6509 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/6509 for details. -gerrit

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coreboot-gerrit August 2014