coreboot-gerrit August 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 3fb27d3 lenovo/t520: update Kconfig
by Nicolas Reinecke 25 Aug '14

25 Aug '14

Nicolas Reinecke (nr(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6759 -gerrit commit 3fb27d3177684780c9583b45676e138550312846 Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sun Aug 24 22:12:37 2014 +0200 lenovo/t520: update Kconfig override default ivy BIOS_PCI_ID add model & part number Remove ARCH_X86 as is in, fd33781 Move ARCH_* from board/Kconfig to cpu or soc Kconfig. Change-Id: I61dc6434de7af2d8672f784df87a8b9d3f0fb068 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/mainboard/lenovo/t520/Kconfig | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 5d43ea1..0f0fd88 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -2,7 +2,6 @@ if BOARD_LENOVO_T520 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_RPGA988B select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_BD82X6X @@ -36,7 +35,11 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER string - default "XXXXXXX" + default "4242W1A" + +config MAINBOARD_VERSION + string + default "ThinkPad T520" config MMCONF_BASE_ADDRESS hex @@ -62,6 +65,10 @@ config DRAM_GATE_GPIO int default 10 +config VGA_BIOS_ID + string + default "8086,0126" + config VGA_BIOS_FILE string default "pci8086,0126.rom"

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Patch merged into coreboot/master: 1065cc9 lenovo/t5x0: replace invalid config DRAM_GATE_GPIO
by gerrit＠coreboot.org 25 Aug '14

25 Aug '14

the following patch was just integrated into master: commit 1065cc9a2568831d6c4ca415a45296f98024045a Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sun Aug 24 22:14:29 2014 +0200 lenovo/t5x0: replace invalid config DRAM_GATE_GPIO Change-Id: I3b13bddfc127353e0c13d8d2ae7918d5c3deb72c Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Reviewed-on: http://review.coreboot.org/6760 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/6760 for details. -gerrit

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Patch merged into coreboot/master: 96555bf lenovo/x230: Add subsystem ids.
by gerrit＠coreboot.org 25 Aug '14

25 Aug '14

the following patch was just integrated into master: commit 96555bf4deee042c89bb28dac79303bc28b41686 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Aug 24 22:38:56 2014 +0200 lenovo/x230: Add subsystem ids. Change-Id: I917a89da50d8efe998c368ba46206f2a1c580fd0 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/6756 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6756 for details. -gerrit

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Patch set updated for coreboot: cc324c0 lenovo/t530: Make use of gpio.h for gpio configuration
by Edward O'Callaghan 25 Aug '14

25 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6461 -gerrit commit cc324c042f8d47158cfee4a38da406ab646a410a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 2 12:58:29 2014 +1000 lenovo/t530: Make use of gpio.h for gpio configuration Rather than using 'outl()' calls directly, update and use gpio.h struct's with the internal southbridge resource allocator to do the write outs. Change-Id: I289e525f34ce74dba2f4d6ab55a30b155beb0e24 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/gpio.h | 113 +++++++++++++++++++++++++---------- src/mainboard/lenovo/t530/romstage.c | 13 +--- 2 files changed, 82 insertions(+), 44 deletions(-) diff --git a/src/mainboard/lenovo/t530/gpio.h b/src/mainboard/lenovo/t530/gpio.h index 70e4c09..2ccdce7 100644 --- a/src/mainboard/lenovo/t530/gpio.h +++ b/src/mainboard/lenovo/t530/gpio.h @@ -23,6 +23,7 @@ #include "southbridge/intel/bd82x6x/gpio.h" +/* outl(0x3962a5ff, DEFAULT_GPIOBASE + GPIO_USE_SEL); */ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, @@ -58,6 +59,7 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio31 = GPIO_MODE_NATIVE, }; +/* outl(0x8ebf6aff, DEFAULT_GPIOBASE + GP_IO_SEL); */ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, @@ -93,47 +95,86 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio31 = GPIO_DIR_INPUT }; +/* outl(0x66917ebb, DEFAULT_GPIOBASE + GP_LVL); */ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, - .gpio1 = GPIO_LEVEL_HIGH, - .gpio2 = GPIO_LEVEL_LOW, + .gpio1 = GPIO_LEVEL_LOW, + .gpio2 = GPIO_LEVEL_HIGH, .gpio3 = GPIO_LEVEL_HIGH, .gpio4 = GPIO_LEVEL_HIGH, - .gpio5 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_LOW, .gpio6 = GPIO_LEVEL_HIGH, - .gpio7 = GPIO_LEVEL_HIGH, - .gpio8 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_HIGH, .gpio9 = GPIO_LEVEL_HIGH, .gpio10 = GPIO_LEVEL_HIGH, .gpio11 = GPIO_LEVEL_HIGH, .gpio12 = GPIO_LEVEL_HIGH, .gpio13 = GPIO_LEVEL_HIGH, - .gpio14 = GPIO_LEVEL_HIGH, - .gpio15 = GPIO_LEVEL_LOW, - .gpio16 = GPIO_LEVEL_HIGH, - .gpio17 = GPIO_LEVEL_HIGH, - .gpio18 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_LOW, .gpio19 = GPIO_LEVEL_HIGH, - .gpio20 = GPIO_LEVEL_HIGH, - .gpio21 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, .gpio22 = GPIO_LEVEL_HIGH, - .gpio23 = GPIO_LEVEL_HIGH, - .gpio24 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_HIGH, .gpio25 = GPIO_LEVEL_HIGH, - .gpio26 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_LOW, .gpio27 = GPIO_LEVEL_LOW, - .gpio28 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, .gpio29 = GPIO_LEVEL_HIGH, - .gpio30 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_LOW, .gpio31 = GPIO_LEVEL_LOW, }; +/* Output Control Registers */ +/* outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK); */ +const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_NO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +/* outl(0x00002002, DEFAULT_GPIOBASE + GPI_INV); */ const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, - .gpio6 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; +/* outl(0x02ff08fe, DEFAULT_GPIOBASE + GPIO_USE_SEL2); */ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, @@ -169,10 +210,11 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio63 = GPIO_MODE_NATIVE, }; +/* outl(0x1f47f7fd, DEFAULT_GPIOBASE + GP_IO_SEL2); */ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, - .gpio33 = GPIO_DIR_INPUT, - .gpio34 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, .gpio35 = GPIO_DIR_INPUT, .gpio36 = GPIO_DIR_INPUT, .gpio37 = GPIO_DIR_INPUT, @@ -204,28 +246,29 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio63 = GPIO_DIR_OUTPUT, }; +/* outl(0xffbeff43, DEFAULT_GPIOBASE + GP_LVL2); */ const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_HIGH, - .gpio33 = GPIO_LEVEL_HIGH, + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, .gpio34 = GPIO_LEVEL_LOW, .gpio35 = GPIO_LEVEL_LOW, - .gpio36 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_HIGH, .gpio37 = GPIO_LEVEL_LOW, .gpio38 = GPIO_LEVEL_HIGH, - .gpio39 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_HIGH, .gpio40 = GPIO_LEVEL_HIGH, .gpio41 = GPIO_LEVEL_HIGH, .gpio42 = GPIO_LEVEL_HIGH, .gpio43 = GPIO_LEVEL_HIGH, .gpio44 = GPIO_LEVEL_HIGH, .gpio45 = GPIO_LEVEL_HIGH, - .gpio46 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_LOW, .gpio47 = GPIO_LEVEL_HIGH, .gpio48 = GPIO_LEVEL_HIGH, .gpio49 = GPIO_LEVEL_HIGH, .gpio50 = GPIO_LEVEL_HIGH, .gpio51 = GPIO_LEVEL_HIGH, - .gpio52 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, .gpio53 = GPIO_LEVEL_HIGH, .gpio54 = GPIO_LEVEL_HIGH, .gpio55 = GPIO_LEVEL_HIGH, @@ -236,11 +279,13 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio60 = GPIO_LEVEL_HIGH, .gpio61 = GPIO_LEVEL_HIGH, .gpio62 = GPIO_LEVEL_LOW, - .gpio63 = GPIO_LEVEL_HIGH, + .gpio63 = GPIO_LEVEL_LOW, }; +/* GPIO_USE_SEL3 */ +/* outl(0x000000ff, DEFAULT_GPIOBASE + GPIO_USE_SEL3); */ const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_GPIO, + .gpio64 = GPIO_MODE_GPIO, // native = 0, gpio = 1 .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, .gpio67 = GPIO_MODE_GPIO, @@ -254,8 +299,10 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio75 = GPIO_MODE_NATIVE, }; +/* GP_IO_SEL3 */ +/* outl(0x00000fff, DEFAULT_GPIOBASE + GP_IO_SEL3); */ const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio64 = GPIO_DIR_INPUT, + .gpio64 = GPIO_DIR_INPUT, // out = 0, in = 1 .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, .gpio67 = GPIO_DIR_INPUT, @@ -269,15 +316,17 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio75 = GPIO_DIR_INPUT, }; +/* GP_LVL3 */ +/* outl(0x00000f4f, DEFAULT_GPIOBASE + GP_LVL3); */ const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_HIGH, .gpio65 = GPIO_LEVEL_HIGH, .gpio66 = GPIO_LEVEL_HIGH, .gpio67 = GPIO_LEVEL_HIGH, .gpio68 = GPIO_LEVEL_LOW, - .gpio69 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, // low = 0 .gpio70 = GPIO_LEVEL_HIGH, - .gpio71 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_LOW, .gpio72 = GPIO_LEVEL_HIGH, .gpio73 = GPIO_LEVEL_HIGH, .gpio74 = GPIO_LEVEL_HIGH, @@ -289,8 +338,8 @@ const struct pch_gpio_map t530_gpio_map = { .mode = &pch_gpio_set1_mode, .direction = &pch_gpio_set1_direction, .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, .invert = &pch_gpio_set1_invert, - }, .set2 = { .mode = &pch_gpio_set2_mode, diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index abad272..fb870ce 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -182,18 +182,7 @@ void main(unsigned long bist) pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); -// setup_pch_gpios(&t530_gpio_map); - outl(0x3962a5ff, DEFAULT_GPIOBASE + GPIO_USE_SEL); - outl(0x8ebf6aff, DEFAULT_GPIOBASE + GP_IO_SEL); - outl(0x66917ebb, DEFAULT_GPIOBASE + GP_LVL); - outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK); - outl(0x00002002, DEFAULT_GPIOBASE + GPI_INV); - outl(0x02ff08fe, DEFAULT_GPIOBASE + GPIO_USE_SEL2); - outl(0x1f47f7fd, DEFAULT_GPIOBASE + GP_IO_SEL2); - outl(0xffbeff43, DEFAULT_GPIOBASE + GP_LVL2); - outl(0x000000ff, DEFAULT_GPIOBASE + GPIO_USE_SEL3); - outl(0x00000fff, DEFAULT_GPIOBASE + GP_IO_SEL3); - outl(0x00000f4f, DEFAULT_GPIOBASE + GP_LVL3); + setup_pch_gpios(&t530_gpio_map); /* Initialize console device(s) */ console_init();

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Patch merged into coreboot/master: 7cf3d22 lenovo/t530: Be safe by disabling blink gpio hw with a writeout
by gerrit＠coreboot.org 25 Aug '14

25 Aug '14

the following patch was just integrated into master: commit 7cf3d226e225bdea9d9cf8f2c85ede64710e06b5 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Aug 1 20:30:21 2014 +1000 lenovo/t530: Be safe by disabling blink gpio hw with a writeout This disables the blink hardware as it seems to be in the dump. This is safer as it does not rely on 0 as the reset value when '0x00040000' is the default according to the util/inteltool. As seen: gpiobase+0x0018: 0x00040000 (GPO_BLINK) DIFF Change-Id: Ia1fde108bf3752484f5e991600c435f776af0ced Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6436 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/6436 for details. -gerrit

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Patch merged into coreboot/master: 9ba922f sandybridge: Native gfx init.
by gerrit＠coreboot.org 25 Aug '14

25 Aug '14

the following patch was just integrated into master: commit 9ba922f8bda1e4a7e201fadca2b0f1c38f89f4e0 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Aug 24 22:38:07 2014 +0200 sandybridge: Native gfx init. Change-Id: I07590086ffe3b1d068fa6ae6b156039cc2e55893 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/6755 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6755 for details. -gerrit

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New patch to review for coreboot: bbbc19a lenovo/t520/mainboard.c: Add EC info to SMBIOS
by Nicolas Reinecke 24 Aug '14

24 Aug '14

Nicolas Reinecke (nr(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6761 -gerrit commit bbbc19a66a0636865ac3d177429158a18c0511ec Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sun Aug 24 22:20:13 2014 +0200 lenovo/t520/mainboard.c: Add EC info to SMBIOS As is in: 91175bb lenovo/x201 & x230: Add EC info to SMBIOS This is needed for the Linux driver for the Lenovo's to properly attach. Change-Id: I92bed33c639e36c41dffe556bc58ee4e5b6d42ab Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/mainboard/lenovo/t520/mainboard.c | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c index 8b1aa0d..c04bc68 100644 --- a/src/mainboard/lenovo/t520/mainboard.c +++ b/src/mainboard/lenovo/t520/mainboard.c @@ -40,6 +40,7 @@ #include <cbfs.h> #include <pc80/keyboard.h> #include <ec/lenovo/h8/h8.h> +#include <build.h> #include <device/azalia_device.h> void mainboard_suspend_resume(void) @@ -133,6 +134,15 @@ static int int15_handler(void) } #endif +const char *smbios_mainboard_bios_version(void) +{ + /* Satisfy thinkpad_acpi. */ + if (strlen(CONFIG_LOCALVERSION)) + return "CBET4000 " CONFIG_LOCALVERSION; + else + return "CBET4000 " COREBOOT_VERSION; +} + const char *smbios_mainboard_version(void) { return "ThinkPad T520"; @@ -166,11 +176,28 @@ static void mainboard_init(device_t dev) 0x42, 0x142); } -/* mainboard_enable is executed as first thing after -enumerate_buses(). */ +static int mainboard_smbios_data(device_t dev, int *handle, unsigned long *current) +{ + int len; + char tpec[] = "IBM ThinkPad Embedded Controller -[ ]-"; + const char *oem_strings[] = { + tpec, + }; + + h8_build_id_and_function_spec_version(tpec + 35, 17); + len = smbios_write_type11(current, (*handle)++, oem_strings, ARRAY_SIZE(oem_strings)); + + return len; +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->get_smbios_data = mainboard_smbios_data; + #if CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler);

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New patch to review for coreboot: 40b2492 lenovo/t5x0: replace invalid config DRAM_GATE_GPIO
by Nicolas Reinecke 24 Aug '14

24 Aug '14

Nicolas Reinecke (nr(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6760 -gerrit commit 40b2492c04d1d34693451ed281b15e22bcdc53b0 Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sun Aug 24 22:14:29 2014 +0200 lenovo/t5x0: replace invalid config DRAM_GATE_GPIO Change-Id: I3b13bddfc127353e0c13d8d2ae7918d5c3deb72c Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/mainboard/lenovo/t520/Kconfig | 2 +- src/mainboard/lenovo/t530/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 0f0fd88..b6c9e05 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -61,7 +61,7 @@ config USBDEBUG_HCD_INDEX int default 2 -config DRAM_GATE_GPIO +config DRAM_RESET_GATE_GPIO int default 10 diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 473f8b8..a850e11 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -57,7 +57,7 @@ config USBDEBUG_HCD_INDEX int default 2 -config DRAM_GATE_GPIO +config DRAM_RESET_GATE_GPIO int default 10

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New patch to review for coreboot: 504fcc9 lenovo/t520: update Kconfig
by Nicolas Reinecke 24 Aug '14

24 Aug '14

Nicolas Reinecke (nr(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6759 -gerrit commit 504fcc96c8696b192cd9551f50178ba7e295642b Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sun Aug 24 22:12:37 2014 +0200 lenovo/t520: update Kconfig override default ivy BIOS_PCI_ID add model & part number remove ARCH_X86 -> http://review.coreboot.org/5570 Change-Id: I61dc6434de7af2d8672f784df87a8b9d3f0fb068 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/mainboard/lenovo/t520/Kconfig | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 5d43ea1..0f0fd88 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -2,7 +2,6 @@ if BOARD_LENOVO_T520 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select ARCH_X86 select CPU_INTEL_SOCKET_RPGA988B select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_BD82X6X @@ -36,7 +35,11 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER string - default "XXXXXXX" + default "4242W1A" + +config MAINBOARD_VERSION + string + default "ThinkPad T520" config MMCONF_BASE_ADDRESS hex @@ -62,6 +65,10 @@ config DRAM_GATE_GPIO int default 10 +config VGA_BIOS_ID + string + default "8086,0126" + config VGA_BIOS_FILE string default "pci8086,0126.rom"

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New patch to review for coreboot: 12aaaf2 lenovo/t520: fix PCIe interrupt and function disable config
by Nicolas Reinecke 24 Aug '14

24 Aug '14

Nicolas Reinecke (nr(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6758 -gerrit commit 12aaaf258c74a930fba78abb619a7d6ae25f326e Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sun Aug 24 19:49:35 2014 +0200 lenovo/t520: fix PCIe interrupt and function disable config Change-Id: I33e71c0a246583885368dc3d3af761c190b2fb5c Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl | 6 +++--- src/mainboard/lenovo/t520/romstage.c | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl index 6c1c695..b4b81a2 100644 --- a/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl +++ b/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl @@ -29,9 +29,9 @@ Method(_PRT) // High Definition Audio 0:1b.0 Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB - Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF - Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD + Package() { 0x001cffff, 0, 0, 17 },// D28IP_P2IP WLAN INTA -> PIRQB + Package() { 0x001cffff, 1, 0, 21 },// D28IP_P4IP EXC INTB -> PIRQF + Package() { 0x001cffff, 2, 0, 19 },// D28IP_P5IP SDCARD INTC -> PIRQD // EHCI #1 0:1d.0 Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD // EHCI #2 0:1a.0 diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index c3cd602..8aef922 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -64,9 +64,9 @@ static void rcba_config(void) { /* * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P2IP ETH0 INTB -> PIRQF - * D28IP_P3IP SDCARD INTC -> PIRQD + * D28IP_P2IP WLAN INTA -> PIRQB + * D28IP_P4IP EXC INTB -> PIRQF + * D28IP_P5IP SDCARD INTC -> PIRQD * D29IP_E1P EHCI1 INTA -> PIRQD * D26IP_E2P EHCI2 INTA -> PIRQF * D31IP_SIP SATA INTA -> PIRQB (MSI) @@ -83,8 +83,8 @@ static void rcba_config(void) RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); RCBA32(D29IP) = (INTA << D29IP_E1P); - RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | - (INTC << D28IP_P3IP); + RCBA32(D28IP) = (INTA << D28IP_P2IP) | (INTB << D28IP_P4IP) | + (INTC << D28IP_P5IP); RCBA32(D27IP) = (INTA << D27IP_ZIP); RCBA32(D26IP) = (INTA << D26IP_E2P); RCBA32(D25IP) = (NOINT << D25IP_LIP); @@ -105,7 +105,7 @@ static void rcba_config(void) (void) RCBA16(OIC); /* Disable unused devices (board specific) */ - RCBA32(FD) = 0x17f81fe3; + RCBA32(FD) = 0x1ee51fe3; RCBA32(BUC) = 0; }

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coreboot-gerrit August 2014