coreboot-gerrit August 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 7b6a0a3 lenovo/t530/romstage.c: Trivial - move include to top
by Edward O'Callaghan 24 Aug '14

24 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6750 -gerrit commit 7b6a0a37315c8c59030685e4c02ac4dbc7688344 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 23 14:25:30 2014 +1000 lenovo/t530/romstage.c: Trivial - move include to top Change-Id: I6b80ad0da39e93072e28b48c40e1c71602133e7b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 8880e30..bb4c0a5 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -41,6 +41,7 @@ #include <cpu/x86/msr.h> #include "gpio.h" #include <cbfs.h> +#include <cpu/intel/romstage.h> static void pch_enable_lpc(void) { @@ -109,7 +110,6 @@ static void rcba_config(void) RCBA32(BUC) = 0; } -#include <cpu/intel/romstage.h> void main(unsigned long bist) { int boot_mode = 0;

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Patch set updated for coreboot: 42cc717 lenovo/t530: Make use of gpio.h for gpio configuration
by Edward O'Callaghan 24 Aug '14

24 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6461 -gerrit commit 42cc717e66c7c9f8db73e21c05468e700c8cd93a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 2 12:58:29 2014 +1000 lenovo/t530: Make use of gpio.h for gpio configuration Rather than using 'outl()' calls directly, update and use gpio.h struct's with the internal southbridge resource allocator to do the write outs. Change-Id: I289e525f34ce74dba2f4d6ab55a30b155beb0e24 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/gpio.h | 137 ++++++++++++++++++++++++----------- src/mainboard/lenovo/t530/romstage.c | 13 +--- 2 files changed, 94 insertions(+), 56 deletions(-) diff --git a/src/mainboard/lenovo/t530/gpio.h b/src/mainboard/lenovo/t530/gpio.h index 70e4c09..88b93d6 100644 --- a/src/mainboard/lenovo/t530/gpio.h +++ b/src/mainboard/lenovo/t530/gpio.h @@ -23,6 +23,7 @@ #include "southbridge/intel/bd82x6x/gpio.h" +/* outl(0x3962a5ff, DEFAULT_GPIOBASE + GPIO_USE_SEL); */ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, .gpio1 = GPIO_MODE_GPIO, @@ -36,28 +37,29 @@ const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio9 = GPIO_MODE_NATIVE, .gpio10 = GPIO_MODE_GPIO, .gpio11 = GPIO_MODE_NATIVE, - .gpio12 = GPIO_MODE_NATIVE, - .gpio13 = GPIO_MODE_GPIO, - .gpio14 = GPIO_MODE_NATIVE, - .gpio15 = GPIO_MODE_GPIO, - .gpio16 = GPIO_MODE_NATIVE, - .gpio17 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_NATIVE, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_NATIVE, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_NATIVE, .gpio18 = GPIO_MODE_NATIVE, .gpio19 = GPIO_MODE_NATIVE, - .gpio20 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_GPIO, .gpio21 = GPIO_MODE_GPIO, - .gpio22 = GPIO_MODE_GPIO, - .gpio23 = GPIO_MODE_NATIVE, - .gpio24 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_NATIVE, .gpio25 = GPIO_MODE_NATIVE, - .gpio26 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, .gpio27 = GPIO_MODE_GPIO, .gpio28 = GPIO_MODE_GPIO, - .gpio29 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, .gpio30 = GPIO_MODE_NATIVE, .gpio31 = GPIO_MODE_NATIVE, }; +/* outl(0x8ebf6aff, DEFAULT_GPIOBASE + GP_IO_SEL); */ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio0 = GPIO_DIR_INPUT, .gpio1 = GPIO_DIR_INPUT, @@ -93,47 +95,86 @@ const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio31 = GPIO_DIR_INPUT }; +/* outl(0x66917ebb, DEFAULT_GPIOBASE + GP_LVL); */ const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio0 = GPIO_LEVEL_HIGH, - .gpio1 = GPIO_LEVEL_HIGH, - .gpio2 = GPIO_LEVEL_LOW, + .gpio1 = GPIO_LEVEL_LOW, + .gpio2 = GPIO_LEVEL_HIGH, .gpio3 = GPIO_LEVEL_HIGH, .gpio4 = GPIO_LEVEL_HIGH, - .gpio5 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_LOW, .gpio6 = GPIO_LEVEL_HIGH, - .gpio7 = GPIO_LEVEL_HIGH, - .gpio8 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_LOW, + .gpio8 = GPIO_LEVEL_HIGH, .gpio9 = GPIO_LEVEL_HIGH, .gpio10 = GPIO_LEVEL_HIGH, .gpio11 = GPIO_LEVEL_HIGH, .gpio12 = GPIO_LEVEL_HIGH, .gpio13 = GPIO_LEVEL_HIGH, - .gpio14 = GPIO_LEVEL_HIGH, - .gpio15 = GPIO_LEVEL_LOW, - .gpio16 = GPIO_LEVEL_HIGH, - .gpio17 = GPIO_LEVEL_HIGH, - .gpio18 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_LOW, .gpio19 = GPIO_LEVEL_HIGH, - .gpio20 = GPIO_LEVEL_HIGH, - .gpio21 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, .gpio22 = GPIO_LEVEL_HIGH, - .gpio23 = GPIO_LEVEL_HIGH, - .gpio24 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_HIGH, .gpio25 = GPIO_LEVEL_HIGH, - .gpio26 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_LOW, .gpio27 = GPIO_LEVEL_LOW, - .gpio28 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, .gpio29 = GPIO_LEVEL_HIGH, - .gpio30 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_LOW, .gpio31 = GPIO_LEVEL_LOW, }; +/* Output Control Registers */ +/* outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK); */ +const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_NO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +/* outl(0x00002002, DEFAULT_GPIOBASE + GPI_INV); */ const struct pch_gpio_set1 pch_gpio_set1_invert = { .gpio1 = GPIO_INVERT, - .gpio6 = GPIO_INVERT, .gpio13 = GPIO_INVERT, }; +/* outl(0x02ff08fe, DEFAULT_GPIOBASE + GPIO_USE_SEL2); */ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio32 = GPIO_MODE_NATIVE, .gpio33 = GPIO_MODE_GPIO, @@ -169,10 +210,11 @@ const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio63 = GPIO_MODE_NATIVE, }; +/* outl(0x1f47f7fd, DEFAULT_GPIOBASE + GP_IO_SEL2); */ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio32 = GPIO_DIR_INPUT, - .gpio33 = GPIO_DIR_INPUT, - .gpio34 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, .gpio35 = GPIO_DIR_INPUT, .gpio36 = GPIO_DIR_INPUT, .gpio37 = GPIO_DIR_INPUT, @@ -204,28 +246,29 @@ const struct pch_gpio_set2 pch_gpio_set2_direction = { .gpio63 = GPIO_DIR_OUTPUT, }; +/* outl(0xffbeff43, DEFAULT_GPIOBASE + GP_LVL2); */ const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio32 = GPIO_LEVEL_HIGH, - .gpio33 = GPIO_LEVEL_HIGH, + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, .gpio34 = GPIO_LEVEL_LOW, .gpio35 = GPIO_LEVEL_LOW, - .gpio36 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_HIGH, .gpio37 = GPIO_LEVEL_LOW, .gpio38 = GPIO_LEVEL_HIGH, - .gpio39 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_HIGH, .gpio40 = GPIO_LEVEL_HIGH, .gpio41 = GPIO_LEVEL_HIGH, .gpio42 = GPIO_LEVEL_HIGH, .gpio43 = GPIO_LEVEL_HIGH, .gpio44 = GPIO_LEVEL_HIGH, .gpio45 = GPIO_LEVEL_HIGH, - .gpio46 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_LOW, .gpio47 = GPIO_LEVEL_HIGH, .gpio48 = GPIO_LEVEL_HIGH, .gpio49 = GPIO_LEVEL_HIGH, .gpio50 = GPIO_LEVEL_HIGH, .gpio51 = GPIO_LEVEL_HIGH, - .gpio52 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, .gpio53 = GPIO_LEVEL_HIGH, .gpio54 = GPIO_LEVEL_HIGH, .gpio55 = GPIO_LEVEL_HIGH, @@ -236,11 +279,13 @@ const struct pch_gpio_set2 pch_gpio_set2_level = { .gpio60 = GPIO_LEVEL_HIGH, .gpio61 = GPIO_LEVEL_HIGH, .gpio62 = GPIO_LEVEL_LOW, - .gpio63 = GPIO_LEVEL_HIGH, + .gpio63 = GPIO_LEVEL_LOW, }; +/* GPIO_USE_SEL3 */ +/* outl(0x000000ff, DEFAULT_GPIOBASE + GPIO_USE_SEL3); */ const struct pch_gpio_set3 pch_gpio_set3_mode = { - .gpio64 = GPIO_MODE_GPIO, + .gpio64 = GPIO_MODE_GPIO, // native = 0, gpio = 1 .gpio65 = GPIO_MODE_GPIO, .gpio66 = GPIO_MODE_GPIO, .gpio67 = GPIO_MODE_GPIO, @@ -254,8 +299,10 @@ const struct pch_gpio_set3 pch_gpio_set3_mode = { .gpio75 = GPIO_MODE_NATIVE, }; +/* GP_IO_SEL3 */ +/* outl(0x00000fff, DEFAULT_GPIOBASE + GP_IO_SEL3); */ const struct pch_gpio_set3 pch_gpio_set3_direction = { - .gpio64 = GPIO_DIR_INPUT, + .gpio64 = GPIO_DIR_INPUT, // out = 0, in = 1 .gpio65 = GPIO_DIR_INPUT, .gpio66 = GPIO_DIR_INPUT, .gpio67 = GPIO_DIR_INPUT, @@ -269,15 +316,17 @@ const struct pch_gpio_set3 pch_gpio_set3_direction = { .gpio75 = GPIO_DIR_INPUT, }; +/* GP_LVL3 */ +/* outl(0x00000f4f, DEFAULT_GPIOBASE + GP_LVL3); */ const struct pch_gpio_set3 pch_gpio_set3_level = { .gpio64 = GPIO_LEVEL_HIGH, .gpio65 = GPIO_LEVEL_HIGH, .gpio66 = GPIO_LEVEL_HIGH, .gpio67 = GPIO_LEVEL_HIGH, .gpio68 = GPIO_LEVEL_LOW, - .gpio69 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, // low = 0 .gpio70 = GPIO_LEVEL_HIGH, - .gpio71 = GPIO_LEVEL_HIGH, + .gpio71 = GPIO_LEVEL_LOW, .gpio72 = GPIO_LEVEL_HIGH, .gpio73 = GPIO_LEVEL_HIGH, .gpio74 = GPIO_LEVEL_HIGH, @@ -289,8 +338,8 @@ const struct pch_gpio_map t530_gpio_map = { .mode = &pch_gpio_set1_mode, .direction = &pch_gpio_set1_direction, .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, .invert = &pch_gpio_set1_invert, - }, .set2 = { .mode = &pch_gpio_set2_mode, diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index abad272..fb870ce 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -182,18 +182,7 @@ void main(unsigned long bist) pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); -// setup_pch_gpios(&t530_gpio_map); - outl(0x3962a5ff, DEFAULT_GPIOBASE + GPIO_USE_SEL); - outl(0x8ebf6aff, DEFAULT_GPIOBASE + GP_IO_SEL); - outl(0x66917ebb, DEFAULT_GPIOBASE + GP_LVL); - outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK); - outl(0x00002002, DEFAULT_GPIOBASE + GPI_INV); - outl(0x02ff08fe, DEFAULT_GPIOBASE + GPIO_USE_SEL2); - outl(0x1f47f7fd, DEFAULT_GPIOBASE + GP_IO_SEL2); - outl(0xffbeff43, DEFAULT_GPIOBASE + GP_LVL2); - outl(0x000000ff, DEFAULT_GPIOBASE + GPIO_USE_SEL3); - outl(0x00000fff, DEFAULT_GPIOBASE + GP_IO_SEL3); - outl(0x00000f4f, DEFAULT_GPIOBASE + GP_LVL3); + setup_pch_gpios(&t530_gpio_map); /* Initialize console device(s) */ console_init();

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Patch set updated for coreboot: d71f496 lenovo/t530: Be safe by disabling blink gpio hw with a writeout
by Edward O'Callaghan 24 Aug '14

24 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6436 -gerrit commit d71f496949bd4c4d16367819b958f19f17e67b35 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Aug 1 20:30:21 2014 +1000 lenovo/t530: Be safe by disabling blink gpio hw with a writeout This disables the blink hardware as it seems to be in the dump. This is safer as it does not rely on 0 as the reset value when '0x00040000' is the default according to the util/inteltool. As seen: gpiobase+0x0018: 0x00040000 (GPO_BLINK) DIFF Change-Id: Ia1fde108bf3752484f5e991600c435f776af0ced Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/romstage.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 3be1869..abad272 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -186,6 +186,7 @@ void main(unsigned long bist) outl(0x3962a5ff, DEFAULT_GPIOBASE + GPIO_USE_SEL); outl(0x8ebf6aff, DEFAULT_GPIOBASE + GP_IO_SEL); outl(0x66917ebb, DEFAULT_GPIOBASE + GP_LVL); + outl(0x00000000, DEFAULT_GPIOBASE + GPO_BLINK); outl(0x00002002, DEFAULT_GPIOBASE + GPI_INV); outl(0x02ff08fe, DEFAULT_GPIOBASE + GPIO_USE_SEL2); outl(0x1f47f7fd, DEFAULT_GPIOBASE + GP_IO_SEL2);

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Patch set updated for coreboot: 6d0327c lenovo/t530: Use native raminit over MRC blob
by Edward O'Callaghan 24 Aug '14

24 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6394 -gerrit commit 6d0327c1a203ce7d35f99406eb2b1e6b13cf115b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jul 29 14:09:27 2014 +1000 lenovo/t530: Use native raminit over MRC blob We now have Native raminit for both sandy/ivybridge introduced in: 7686a56 sandy/ivybridge: Native raminit. Let us make good use of this support over using the Intel MRC blob to initialise memory. USB RCBA configuration data taken between base of 0x3500 up to 0x3600 from `inteltool -r`. Remark: Note the current port is poorly tested at the moment and I am the sole maintainer, however one less blob invites more interest for better support. More to come hopefully. Change-Id: I41d0ef8303dfd369c5565b823e68a6bee09c44f5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/Kconfig | 12 ++-- src/mainboard/lenovo/t530/romstage.c | 134 +++++++++++++---------------------- 2 files changed, 55 insertions(+), 91 deletions(-) diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 473f8b8..efeca4b 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -3,7 +3,7 @@ if BOARD_LENOVO_T530 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 @@ -18,8 +18,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SERIRQ_CONTINUOUS_MODE config HAVE_MRC_CACHE - bool - default n + bool + default y config HAVE_IFD_BIN bool @@ -41,10 +41,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config CACHE_ROM_SIZE_OVERRIDE - hex - default 0x800000 - config IRQ_SLOT_COUNT int default 18 @@ -57,7 +53,7 @@ config USBDEBUG_HCD_INDEX int default 2 -config DRAM_GATE_GPIO +config DRAM_RESET_GATE_GPIO int default 10 diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index fb870ce..749ea31 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -33,7 +33,7 @@ #include <cbmem.h> #include <console/console.h> #include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" +#include "northbridge/intel/sandybridge/raminit_native.h" #include "southbridge/intel/bd82x6x/pch.h" #include "southbridge/intel/bd82x6x/gpio.h" #include <arch/cpu.h> @@ -110,66 +110,57 @@ static void rcba_config(void) RCBA32(BUC) = 0; } +static void init_usb(void) +{ + const u32 rcba_dump[64] = { + /* 3500 */ 0x20000f57, 0x20000f57, 0x2000055b, 0x20000f57, + /* 3510 */ 0x20000f57, 0x20000153, 0x20000153, 0x2000055b, + /* 3520 */ 0x20000153, 0x20000f57, 0x20000153, 0x20000153, + /* 3530 */ 0x20000f51, 0x20000f57, 0x00000000, 0x00000000, + /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050, + /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, + /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00001448, + /* 35a0 */ 0x04000201, 0x00000200, 0x00000000, 0x00000000, + /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + }; + int i; + /* Activate PMBAR. */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ + + /* Unlock registers. */ + outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c); + + for (i = 0; i < 64; i++) + write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), rcba_dump[i]); + + pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); + + /* Relock registers. */ + outw (0x0000, DEFAULT_PMBASE | 0x003c); +} + + void main(unsigned long bist) { - int boot_mode = 0; - int cbmem_was_initted; + int s3resume = 0; u32 pm1_cnt; u16 pm1_sts; + spd_raw_data spd[4]; if (MCHBAR16(SSKPD) == 0xCAFE) { outb(0x6, 0xcf9); hlt (); } - struct pei_data pei_data = { - .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, - .dmibar = DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00,0xA2,0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .gbe_enable = 1, - .ddr3lv_support = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* enabled usb oc pin length */ - { 1, 0, 0x0080 }, /* P0 (left, fan side), OC 0 */ - { 1, 1, 0x0080 }, /* P1 (left touchpad side), OC 1 */ - { 1, 3, 0x0080 }, /* P2: dock, OC 3 */ - { 1, 0, 0x0040 }, /* P3: wwan, no OC */ - { 1, 0, 0x0080 }, /* P4: Wacom tablet on X230t, otherwise empty */ - { 1, 0, 0x0080 }, /* P5: Expresscard, no OC */ - { 0, 0, 0x0000 }, /* P6: Empty */ - { 1, 0, 0x0080 }, /* P7: dock, no OC */ - { 0, 0, 0x0000 }, /* P8: Empty */ - { 1, 5, 0x0080 }, /* P9: Right (EHCI debug), OC 5 */ - { 1, 0, 0x0040 }, /* P10: fingerprint reader, no OC */ - { 1, 0, 0x0040 }, /* P11: bluetooth, no OC. */ - { 1, 0, 0x0040 }, /* P12: wlan, no OC */ - { 1, 0, 0x0080 }, /* P13: webcam, no OC */ - }, - .ddr_refresh_rate_config = 2, /* Force double refresh rate */ - }; - timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); @@ -184,6 +175,8 @@ void main(unsigned long bist) setup_pch_gpios(&t530_gpio_map); + init_usb(); + /* Initialize console device(s) */ console_init(); @@ -205,7 +198,7 @@ void main(unsigned long bist) if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { if (acpi_s3_resume_allowed()) { printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; + s3resume = 1; /* Clear SLP_TYPE. This will break stage2 but * we care for that when we get there. */ @@ -219,31 +212,16 @@ void main(unsigned long bist) /* Enable SPD ROMs and DDR-III DRAM */ enable_smbus(); - /* Prepare USB controller early in S3 resume */ - if (boot_mode == 2) - enable_usb_bar(); - post_code(0x39); post_code(0x3a); - pei_data.boot_mode = boot_mode; timestamp_add_now(TS_BEFORE_INITRAM); - /* MRC.bin has a bug and sometimes halts (instead of reboot?). - */ - if (boot_mode != 2) - { - RCBA32(GCS) = RCBA32(GCS) & ~(1 << 5); /* reset */ - outw((0 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* let timer go */ - } - - sdram_initialize(&pei_data); + memset (spd, 0, sizeof (spd)); + read_spd (&spd[0], 0x50); + read_spd (&spd[2], 0x51); - if (boot_mode != 2) - { - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ - } + init_dram_ddr3 (spd, 1, TCK_800MHZ, s3resume); timestamp_add_now(TS_AFTER_INITRAM); post_code(0x3c); @@ -251,13 +229,7 @@ void main(unsigned long bist) rcba_config(); post_code(0x3d); - quick_ram_check(); - post_code(0x3e); - MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_recovery(boot_mode==2); - if (boot_mode!=2) - save_mrc_data(&pei_data); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so @@ -267,18 +239,14 @@ void main(unsigned long bist) *(u32 *)CBMEM_BOOT_MODE = 0; *(u32 *)CBMEM_RESUME_BACKUP = 0; - if ((boot_mode == 2) && cbmem_was_initted) { + if (s3resume) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; + *(u32 *)CBMEM_BOOT_MODE = 2; *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; } /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { - /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - hlt(); } else { pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); }

1 0

Patch set updated for coreboot: 12ee802 lenovo/t530: Use GPIO defines specified in bd82x6x/pch.h header
by Edward O'Callaghan 24 Aug '14

24 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6435 -gerrit commit 12ee802670db719f4fb1ad56a17cadd12df58eac Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Aug 1 20:29:40 2014 +1000 lenovo/t530: Use GPIO defines specified in bd82x6x/pch.h header Use defines of offsets rather than hard coded values. Change-Id: Id2471cd22aa402d74163473e48f86af9789cdaa7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/romstage.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index bb4c0a5..3be1869 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -183,16 +183,16 @@ void main(unsigned long bist) pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); // setup_pch_gpios(&t530_gpio_map); - outl(0x3962a5ff, DEFAULT_GPIOBASE); - outl(0x8ebf6aff, DEFAULT_GPIOBASE + 4); - outl(0x66917ebb, DEFAULT_GPIOBASE + 0xc); - outl(0x00002002, DEFAULT_GPIOBASE + 0x2c); - outl(0x02ff08fe, DEFAULT_GPIOBASE + 0x30); - outl(0x1f47f7fd, DEFAULT_GPIOBASE + 0x34); - outl(0xffbeff43, DEFAULT_GPIOBASE + 0x38); - outl(0x000000ff, DEFAULT_GPIOBASE + 0x40); - outl(0x00000fff, DEFAULT_GPIOBASE + 0x44); - outl(0x00000f4f, DEFAULT_GPIOBASE + 0x48); + outl(0x3962a5ff, DEFAULT_GPIOBASE + GPIO_USE_SEL); + outl(0x8ebf6aff, DEFAULT_GPIOBASE + GP_IO_SEL); + outl(0x66917ebb, DEFAULT_GPIOBASE + GP_LVL); + outl(0x00002002, DEFAULT_GPIOBASE + GPI_INV); + outl(0x02ff08fe, DEFAULT_GPIOBASE + GPIO_USE_SEL2); + outl(0x1f47f7fd, DEFAULT_GPIOBASE + GP_IO_SEL2); + outl(0xffbeff43, DEFAULT_GPIOBASE + GP_LVL2); + outl(0x000000ff, DEFAULT_GPIOBASE + GPIO_USE_SEL3); + outl(0x00000fff, DEFAULT_GPIOBASE + GP_IO_SEL3); + outl(0x00000f4f, DEFAULT_GPIOBASE + GP_LVL3); /* Initialize console device(s) */ console_init();

1 0

Patch merged into coreboot/master: 6ccc346 lenovo/t520: fix devicetree
by gerrit＠coreboot.org 23 Aug '14

23 Aug '14

the following patch was just integrated into master: commit 6ccc3465c3488411e6e743bb9a2822ac5902b6df Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sat Aug 23 01:06:33 2014 +0200 lenovo/t520: fix devicetree SATA Port documentation PCIe unused ports and documentation T520 have no keyboard backlight Change-Id: I517ff8519ea22a9a7a9b6e3136efd15d4a0f8fc4 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Reviewed-on: http://review.coreboot.org/6743 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6743 for details. -gerrit

1 0

Patch set updated for coreboot: c30f0cb lenovo/t520: fix devicetree
by Nicolas Reinecke 23 Aug '14

23 Aug '14

Nicolas Reinecke (nr(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6743 -gerrit commit c30f0cbb0a3e89e19902d721d7262d1312e06b4f Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sat Aug 23 01:06:33 2014 +0200 lenovo/t520: fix devicetree SATA Port documentation PCIe unused ports and documentation T520 have no keyboard backlight Change-Id: I517ff8519ea22a9a7a9b6e3136efd15d4a0f8fc4 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/mainboard/lenovo/t520/devicetree.cb | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 475e49c..c911d99 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -34,6 +34,7 @@ chip northbridge/intel/sandybridge device domain 0 on device pci 00.0 on end # host bridge + device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH @@ -54,7 +55,7 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "2" register "gpi8_routing" = "2" - # Enable SATA ports 0 + # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock) register "sata_port_map" = "0x1f" # Set max SATA speed to 6.0 Gb/s register "sata_interface_speed_support" = "0x3" @@ -73,11 +74,14 @@ chip northbridge/intel/sandybridge device pci 19.0 on end # Intel Gigabit Ethernet device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 + device pci 1c.0 off end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN - device pci 1c.2 off end - device pci 1c.3 on end # PCIe Port #3 Express Card - device pci 1c.4 on end # PCIe Port #4 MMC/SDXC + IEEE1394 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 Express Card + device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394 + device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY + device pci 1c.6 off end # PCIe Port #7 USB 3.0 only W520 + device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1f.0 on #LPC bridge chip ec/lenovo/pmh7 @@ -100,8 +104,6 @@ chip northbridge/intel/sandybridge register "config2" = "0xa0" register "config3" = "0xc2" - register "has_keyboard_backlight" = "1" - register "beepmask0" = "0x00" register "beepmask1" = "0x86" register "has_power_management_beeps" = "0"

1 0

Patch merged into coreboot/master: 23aad4a lenovo/t520: fix usb config & documentation
by gerrit＠coreboot.org 23 Aug '14

23 Aug '14

the following patch was just integrated into master: commit 23aad4a83c3390dc39f7d1c1f5422f7ac54a80f3 Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sat Aug 23 00:51:49 2014 +0200 lenovo/t520: fix usb config & documentation Change-Id: I71398ab2d7ef5b9256795861dd2bebbb0cf32d5f Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Reviewed-on: http://review.coreboot.org/6742 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/6742 for details. -gerrit

1 0

Patch merged into coreboot/master: e4340b5 ec/lenovo/h8/acpi/systemstatus.asl: Fix typo in o*n* in comment
by gerrit＠coreboot.org 23 Aug '14

23 Aug '14

the following patch was just integrated into master: commit e4340b52ced8bddc796d15cce4c1a154c98dcabd Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Aug 15 15:58:36 2014 +0200 ec/lenovo/h8/acpi/systemstatus.asl: Fix typo in o*n* in comment Change-Id: I655536f64faaa7e1600d4fec62ba80730e2cc45a Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6674 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6674 for details. -gerrit

1 0

New patch to review for coreboot: 01e1ec3 Revert "intel/cpu: rename car.h to romstage.h"
by Edward O'Callaghan 23 Aug '14

23 Aug '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6751 -gerrit commit 01e1ec3a4c56de3626ebca9632736a5a158b8f6e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 23 14:34:32 2014 +1000 Revert "intel/cpu: rename car.h to romstage.h" This header has more to do with CAR than mainboard's romstage in actual fact as it contains the type-signature for the entry-point from CAR which /happens to be in romstage/. Further this change just went and made Intel inconsistent with AMD and friends just as soon as it became consistent. This reverts commit a0a3727dbbd7f3ae9f9021e0797ce2fc61d1b79e. Change-Id: Iedc750c1c1ff1ac10cbf9856b7e7d47ef18287e1 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/include/cpu/intel/car.h | 7 +++++++ src/include/cpu/intel/romstage.h | 7 ------- src/mainboard/a-trend/atc-6220/romstage.c | 2 +- src/mainboard/a-trend/atc-6240/romstage.c | 2 +- src/mainboard/aaeon/pfm-540i_revb/romstage.c | 2 +- src/mainboard/abit/be6-ii_v2_0/romstage.c | 2 +- src/mainboard/advantech/pcm-5820/romstage.c | 2 +- src/mainboard/amd/db800/romstage.c | 2 +- src/mainboard/amd/norwich/romstage.c | 2 +- src/mainboard/amd/rumba/romstage.c | 2 +- src/mainboard/aopen/dxplplusu/romstage.c | 2 +- src/mainboard/artecgroup/dbe61/romstage.c | 2 +- src/mainboard/asi/mb_5blgp/romstage.c | 2 +- src/mainboard/asi/mb_5blmp/romstage.c | 2 +- src/mainboard/asus/dsbf/romstage.c | 2 +- src/mainboard/asus/mew-am/romstage.c | 2 +- src/mainboard/asus/mew-vm/romstage.c | 2 +- src/mainboard/asus/p2b-d/romstage.c | 2 +- src/mainboard/asus/p2b-ds/romstage.c | 2 +- src/mainboard/asus/p2b-f/romstage.c | 2 +- src/mainboard/asus/p2b-ls/romstage.c | 2 +- src/mainboard/asus/p2b/romstage.c | 2 +- src/mainboard/asus/p3b-f/romstage.c | 2 +- src/mainboard/axus/tc320/romstage.c | 2 +- src/mainboard/azza/pt-6ibd/romstage.c | 2 +- src/mainboard/bachmann/ot200/romstage.c | 2 +- src/mainboard/bcom/winnet100/romstage.c | 2 +- src/mainboard/bcom/winnetp680/romstage.c | 2 +- src/mainboard/biostar/m6tba/romstage.c | 2 +- src/mainboard/compaq/deskpro_en_sff_p600/romstage.c | 2 +- src/mainboard/digitallogic/adl855pc/romstage.c | 2 +- src/mainboard/digitallogic/msm586seg/romstage.c | 2 +- src/mainboard/digitallogic/msm800sev/romstage.c | 2 +- src/mainboard/dmp/vortex86ex/romstage.c | 2 +- src/mainboard/eaglelion/5bcm/romstage.c | 2 +- src/mainboard/ecs/p6iwp-fe/romstage.c | 2 +- src/mainboard/emulation/qemu-i440fx/romstage.c | 2 +- src/mainboard/emulation/qemu-q35/romstage.c | 2 +- src/mainboard/getac/p470/romstage.c | 2 +- src/mainboard/gigabyte/ga-6bxc/romstage.c | 2 +- src/mainboard/gigabyte/ga-6bxe/romstage.c | 2 +- src/mainboard/google/butterfly/romstage.c | 2 +- src/mainboard/google/link/romstage.c | 2 +- src/mainboard/google/parrot/romstage.c | 2 +- src/mainboard/google/stout/romstage.c | 2 +- src/mainboard/hp/e_vectra_p2706t/romstage.c | 2 +- src/mainboard/ibase/mb899/romstage.c | 2 +- src/mainboard/iei/juki-511p/romstage.c | 2 +- src/mainboard/iei/nova4899r/romstage.c | 2 +- src/mainboard/iei/pcisa-lx-800-r10/romstage.c | 2 +- src/mainboard/iei/pm-lx-800-r11/romstage.c | 2 +- src/mainboard/iei/pm-lx2-800-r10/romstage.c | 2 +- src/mainboard/intel/d810e2cb/romstage.c | 2 +- src/mainboard/intel/d945gclf/romstage.c | 2 +- src/mainboard/intel/eagleheights/romstage.c | 2 +- src/mainboard/intel/emeraldlake2/romstage.c | 2 +- src/mainboard/intel/jarrell/romstage.c | 2 +- src/mainboard/intel/mtarvon/romstage.c | 2 +- src/mainboard/intel/truxton/romstage.c | 2 +- src/mainboard/intel/xe7501devkit/romstage.c | 2 +- src/mainboard/iwave/iWRainbowG6/romstage.c | 2 +- src/mainboard/jetway/j7f2/romstage.c | 2 +- src/mainboard/kontron/986lcd-m/romstage.c | 2 +- src/mainboard/kontron/ktqm77/romstage.c | 2 +- src/mainboard/lanner/em8510/romstage.c | 2 +- src/mainboard/lenovo/t520/romstage.c | 2 +- src/mainboard/lenovo/t530/romstage.c | 2 +- src/mainboard/lenovo/t60/romstage.c | 2 +- src/mainboard/lenovo/x201/romstage.c | 2 +- src/mainboard/lenovo/x230/romstage.c | 2 +- src/mainboard/lenovo/x60/romstage.c | 2 +- src/mainboard/lippert/frontrunner/romstage.c | 2 +- src/mainboard/lippert/hurricane-lx/romstage.c | 2 +- src/mainboard/lippert/literunner-lx/romstage.c | 2 +- src/mainboard/lippert/roadrunner-lx/romstage.c | 2 +- src/mainboard/lippert/spacerunner-lx/romstage.c | 2 +- src/mainboard/mitac/6513wu/romstage.c | 2 +- src/mainboard/msi/ms6119/romstage.c | 2 +- src/mainboard/msi/ms6147/romstage.c | 2 +- src/mainboard/msi/ms6156/romstage.c | 2 +- src/mainboard/msi/ms6178/romstage.c | 2 +- src/mainboard/nec/powermate2000/romstage.c | 2 +- src/mainboard/nokia/ip530/romstage.c | 2 +- src/mainboard/packardbell/ms2290/romstage.c | 2 +- src/mainboard/pcengines/alix1c/romstage.c | 2 +- src/mainboard/pcengines/alix2d/romstage.c | 2 +- src/mainboard/rca/rm4100/romstage.c | 2 +- src/mainboard/roda/rk886ex/romstage.c | 2 +- src/mainboard/roda/rk9/romstage.c | 2 +- src/mainboard/samsung/lumpy/romstage.c | 2 +- src/mainboard/samsung/stumpy/romstage.c | 2 +- src/mainboard/soyo/sy-6ba-plus-iii/romstage.c | 2 +- src/mainboard/supermicro/x6dai_g/romstage.c | 2 +- src/mainboard/supermicro/x6dhe_g/romstage.c | 2 +- src/mainboard/supermicro/x6dhe_g2/romstage.c | 2 +- src/mainboard/supermicro/x6dhr_ig/romstage.c | 2 +- src/mainboard/supermicro/x6dhr_ig2/romstage.c | 2 +- src/mainboard/supermicro/x7db8/romstage.c | 2 +- src/mainboard/technologic/ts5300/romstage.c | 2 +- src/mainboard/televideo/tc7020/romstage.c | 2 +- src/mainboard/thomson/ip1000/romstage.c | 2 +- src/mainboard/traverse/geos/romstage.c | 2 +- src/mainboard/tyan/s1846/romstage.c | 2 +- src/mainboard/tyan/s2735/romstage.c | 2 +- src/mainboard/via/epia-cn/romstage.c | 2 +- src/mainboard/via/epia-m/romstage.c | 2 +- src/mainboard/via/epia-m700/romstage.c | 2 +- src/mainboard/via/epia-m850/romstage.c | 2 +- src/mainboard/via/epia-n/romstage.c | 2 +- src/mainboard/via/epia/romstage.c | 2 +- src/mainboard/via/pc2500e/romstage.c | 2 +- src/mainboard/via/vt8454c/romstage.c | 2 +- src/mainboard/winent/pl6064/romstage.c | 2 +- src/mainboard/wyse/s50/romstage.c | 2 +- 114 files changed, 119 insertions(+), 119 deletions(-) diff --git a/src/include/cpu/intel/car.h b/src/include/cpu/intel/car.h new file mode 100644 index 0000000..dc89ffc --- /dev/null +++ b/src/include/cpu/intel/car.h @@ -0,0 +1,7 @@ +#ifndef _CPU_INTEL_CAR_H +#define _CPU_INTEL_CAR_H + +/* std signature of entry-point to romstage.c */ +void main(unsigned long bist); + +#endif /* _CPU_INTEL_CAR_H */ diff --git a/src/include/cpu/intel/romstage.h b/src/include/cpu/intel/romstage.h deleted file mode 100644 index 0ebb912..0000000 --- a/src/include/cpu/intel/romstage.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef _CPU_INTEL_ROMSTAGE_H -#define _CPU_INTEL_ROMSTAGE_H - -/* std signature of entry-point to romstage.c */ -void main(unsigned long bist); - -#endif /* _CPU_INTEL_ROMSTAGE_H */ diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c index 70bc5d8..3c3f9eb 100644 --- a/src/mainboard/a-trend/atc-6220/romstage.c +++ b/src/mainboard/a-trend/atc-6220/romstage.c @@ -42,7 +42,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c index 392f40f..a153730 100644 --- a/src/mainboard/a-trend/atc-6240/romstage.c +++ b/src/mainboard/a-trend/atc-6240/romstage.c @@ -41,7 +41,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c index c4bf462..7f78dce 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c +++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c @@ -54,7 +54,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c index 41a09da..a17e68f 100644 --- a/src/mainboard/abit/be6-ii_v2_0/romstage.c +++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c @@ -43,7 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/advantech/pcm-5820/romstage.c b/src/mainboard/advantech/pcm-5820/romstage.c index a6b856e..51a713c 100644 --- a/src/mainboard/advantech/pcm-5820/romstage.c +++ b/src/mainboard/advantech/pcm-5820/romstage.c @@ -30,7 +30,7 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1) -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 3df26c6..f645812 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -49,7 +49,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index 1b8a303..2daef93 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -45,7 +45,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index 2d43fff..9158aad 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -31,7 +31,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/geode_gx2/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl [] = { diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 86470b3..7ef8a47 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -39,7 +39,7 @@ int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index 343351f..23e537f 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -57,7 +57,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { diff --git a/src/mainboard/asi/mb_5blgp/romstage.c b/src/mainboard/asi/mb_5blgp/romstage.c index 43c5cf7..c7f3090 100644 --- a/src/mainboard/asi/mb_5blgp/romstage.c +++ b/src/mainboard/asi/mb_5blgp/romstage.c @@ -30,7 +30,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1) -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asi/mb_5blmp/romstage.c b/src/mainboard/asi/mb_5blmp/romstage.c index 1fb3378..6c18d8f 100644 --- a/src/mainboard/asi/mb_5blmp/romstage.c +++ b/src/mainboard/asi/mb_5blmp/romstage.c @@ -31,7 +31,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1) -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c index fbd0848..6db0866 100644 --- a/src/mainboard/asus/dsbf/romstage.c +++ b/src/mainboard/asus/dsbf/romstage.c @@ -110,7 +110,7 @@ int mainboard_set_fbd_clock(int speed) } } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { if (bist == 0) diff --git a/src/mainboard/asus/mew-am/romstage.c b/src/mainboard/asus/mew-am/romstage.c index 7a79e85..9ea6c04 100644 --- a/src/mainboard/asus/mew-am/romstage.c +++ b/src/mainboard/asus/mew-am/romstage.c @@ -34,7 +34,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/mew-vm/romstage.c b/src/mainboard/asus/mew-vm/romstage.c index 04bbd86..87f8d65 100644 --- a/src/mainboard/asus/mew-vm/romstage.c +++ b/src/mainboard/asus/mew-vm/romstage.c @@ -34,7 +34,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1) -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c index d41afc8..4faae20 100644 --- a/src/mainboard/asus/p2b-d/romstage.c +++ b/src/mainboard/asus/p2b-d/romstage.c @@ -41,7 +41,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index 494a3f0..070b002 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -41,7 +41,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c index 1b905e4..64b4dae 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/romstage.c @@ -43,7 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index 09b9a4e..8cf2b42 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -42,7 +42,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 70bc5d8..3c3f9eb 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -42,7 +42,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 78c7629..825457e 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -74,7 +74,7 @@ static void disable_spd(void) outb(0x67, PM_IO_BASE + 0x37); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/axus/tc320/romstage.c b/src/mainboard/axus/tc320/romstage.c index 15362e3..e733003 100644 --- a/src/mainboard/axus/tc320/romstage.c +++ b/src/mainboard/axus/tc320/romstage.c @@ -31,7 +31,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c index b31be70..7325618 100644 --- a/src/mainboard/azza/pt-6ibd/romstage.c +++ b/src/mainboard/azza/pt-6ibd/romstage.c @@ -43,7 +43,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c index 849479c..41a65dd 100644 --- a/src/mainboard/bachmann/ot200/romstage.c +++ b/src/mainboard/bachmann/ot200/romstage.c @@ -46,7 +46,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/bcom/winnet100/romstage.c b/src/mainboard/bcom/winnet100/romstage.c index 15362e3..e733003 100644 --- a/src/mainboard/bcom/winnet100/romstage.c +++ b/src/mainboard/bcom/winnet100/romstage.c @@ -31,7 +31,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 898ad1a..3676a6d 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -81,7 +81,7 @@ static const struct mem_controller ctrl = { .channel0 = { DIMM0 }, }; -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { /* Enable multifunction for northbridge. */ diff --git a/src/mainboard/biostar/m6tba/romstage.c b/src/mainboard/biostar/m6tba/romstage.c index 921aa52..43158bd 100644 --- a/src/mainboard/biostar/m6tba/romstage.c +++ b/src/mainboard/biostar/m6tba/romstage.c @@ -40,7 +40,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c index 70f820a..8de8a83 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c @@ -42,7 +42,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { /* FIXME: Should be PC97307! */ diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index 093c60b..0ae7610 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -26,7 +26,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/i855/raminit.c" #include "northbridge/intel/i855/reset_test.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { if (bist == 0) { diff --git a/src/mainboard/digitallogic/msm586seg/romstage.c b/src/mainboard/digitallogic/msm586seg/romstage.c index ab944a4..b6412e8 100644 --- a/src/mainboard/digitallogic/msm586seg/romstage.c +++ b/src/mainboard/digitallogic/msm586seg/romstage.c @@ -154,7 +154,7 @@ static inline void irqinit(void){ #endif } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { volatile int i; diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index 8bfe8e5..6075565 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -30,7 +30,7 @@ int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c index a7b31ca..040b937 100644 --- a/src/mainboard/dmp/vortex86ex/romstage.c +++ b/src/mainboard/dmp/vortex86ex/romstage.c @@ -300,7 +300,7 @@ static void enable_l2_cache(void) pci_write_config8(NB1, 0xe8, reg_nb_f1_e8); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { device_t dev; diff --git a/src/mainboard/eaglelion/5bcm/romstage.c b/src/mainboard/eaglelion/5bcm/romstage.c index 28ddcc5..cbfe04d 100644 --- a/src/mainboard/eaglelion/5bcm/romstage.c +++ b/src/mainboard/eaglelion/5bcm/romstage.c @@ -12,7 +12,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c index 9d5f2cd..7deb730 100644 --- a/src/mainboard/ecs/p6iwp-fe/romstage.c +++ b/src/mainboard/ecs/p6iwp-fe/romstage.c @@ -37,7 +37,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO) -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index 6c17645..8dc61b2 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -33,7 +33,7 @@ #include "memory.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { int cbmem_was_initted; diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index dd86701..635a44f 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -34,7 +34,7 @@ #include "../qemu-i440fx/memory.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { int cbmem_was_initted; diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 3dab527..5ebc451 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -265,7 +265,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { u32 reg32; diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c index e0a248b..d28ac34 100644 --- a/src/mainboard/gigabyte/ga-6bxc/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c @@ -40,7 +40,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c index 5d69510..cad3694 100644 --- a/src/mainboard/gigabyte/ga-6bxe/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c @@ -40,7 +40,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { it8671f_48mhz_clkin(); diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 083abe1..1c7b8ba 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -112,7 +112,7 @@ static void rcba_config(void) RCBA32(FD) = reg32; } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 6d819b4..25c6529 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -150,7 +150,7 @@ static void copy_spd(struct pei_data *peid) sizeof(peid->spd_data[0])); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 6c3ec79..a4daae5 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -113,7 +113,7 @@ static void rcba_config(void) RCBA32(FD) = reg32; } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 05caa3e..008f1f8 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -154,7 +154,7 @@ static void early_ec_init(void) } } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c index c34801e..85660c0 100644 --- a/src/mainboard/hp/e_vectra_p2706t/romstage.c +++ b/src/mainboard/hp/e_vectra_p2706t/romstage.c @@ -37,7 +37,7 @@ /* TODO: It's a PC87364 actually! */ #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { /* TODO: It's a PC87364 actually! */ diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 322907b..eec574d 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -223,7 +223,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { u32 reg32; diff --git a/src/mainboard/iei/juki-511p/romstage.c b/src/mainboard/iei/juki-511p/romstage.c index 1b8e952..b8daac4 100644 --- a/src/mainboard/iei/juki-511p/romstage.c +++ b/src/mainboard/iei/juki-511p/romstage.c @@ -32,7 +32,7 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1) -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/iei/nova4899r/romstage.c b/src/mainboard/iei/nova4899r/romstage.c index 2b6caf3..9a89107 100644 --- a/src/mainboard/iei/nova4899r/romstage.c +++ b/src/mainboard/iei/nova4899r/romstage.c @@ -32,7 +32,7 @@ #include "northbridge/amd/gx1/raminit.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index 9f42232..2af0b2f 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -49,7 +49,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { diff --git a/src/mainboard/iei/pm-lx-800-r11/romstage.c b/src/mainboard/iei/pm-lx-800-r11/romstage.c index ac68b1d..d2e331e 100644 --- a/src/mainboard/iei/pm-lx-800-r11/romstage.c +++ b/src/mainboard/iei/pm-lx-800-r11/romstage.c @@ -53,7 +53,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include <cpu/amd/geode_lx/syspreinit.c> #include <cpu/amd/geode_lx/msrinit.c> -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c index a83bf7e..947b52d 100644 --- a/src/mainboard/iei/pm-lx2-800-r10/romstage.c +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -53,7 +53,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include <cpu/amd/geode_lx/syspreinit.c> #include <cpu/amd/geode_lx/msrinit.c> -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c index 8b74b17..982060c 100644 --- a/src/mainboard/intel/d810e2cb/romstage.c +++ b/src/mainboard/intel/d810e2cb/romstage.c @@ -35,7 +35,7 @@ #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { /* Set southbridge and Super I/O GPIOs. */ diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 0c48247..94b6610 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -156,7 +156,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { u32 reg32; diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index e35140b..99445b8 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -120,7 +120,7 @@ static void early_config(void) pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0)); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { /* int boot_mode = 0; */ diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index e10e7b6..12abb54 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -162,7 +162,7 @@ static void setup_sio_gpios(void) outb(0xaa, port); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index f1cf4c3..a672afa 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -38,7 +38,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "debug.c" #include "arch/x86/lib/stages.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { static const struct mem_controller mch[] = { diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index c1ee9bb..2e99be5 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -51,7 +51,7 @@ static inline int spd_read_byte(u16 device, u8 address) #include "arch/x86/lib/stages.c" #endif -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { msr_t msr; diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index cd49967..c56b1df 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -51,7 +51,7 @@ static inline int spd_read_byte(u16 device, u8 address) #define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1) -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { msr_t msr; diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c index e1a5807..f35f93b 100644 --- a/src/mainboard/intel/xe7501devkit/romstage.c +++ b/src/mainboard/intel/xe7501devkit/romstage.c @@ -33,7 +33,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" // This function MUST appear last (ROMCC limitation) -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c index 00d4a38..5ede2f9 100644 --- a/src/mainboard/iwave/iWRainbowG6/romstage.c +++ b/src/mainboard/iwave/iWRainbowG6/romstage.c @@ -332,7 +332,7 @@ static void poulsbo_setup_Stage2Regs(void) printk(BIOS_DEBUG, " done.\n"); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index a9c71c3..cc207b1 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -86,7 +86,7 @@ static const struct mem_controller ctrl = { .channel0 = { DIMM0 }, }; -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { /* Enable multifunction for northbridge. */ diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 2c12c5d..842f7bc 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -329,7 +329,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { u32 reg32; diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 211bfb5..98f5f10 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -159,7 +159,7 @@ static void superio_gpio_config(void) pnp_exit_ext_func_mode(dev); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c index c51ee35..186e9fd 100644 --- a/src/mainboard/lanner/em8510/romstage.c +++ b/src/mainboard/lanner/em8510/romstage.c @@ -48,7 +48,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/i855/raminit.c" #include "northbridge/intel/i855/reset_test.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { if (bist == 0) { diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 62bf1d9..df46092 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -108,7 +108,7 @@ static void rcba_config(void) RCBA32(BUC) = 0; } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 8880e30..b2cd616 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -109,7 +109,7 @@ static void rcba_config(void) RCBA32(BUC) = 0; } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index f11b33e..01e48e7 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -206,7 +206,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { u32 reg32; diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 2c3dfd1..5f8e291 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -215,7 +215,7 @@ static void set_fsb_frequency(void) smbus_block_write(0x69, 0, 5, block); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { u32 reg32; diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 94fa5cf..1705003 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -148,7 +148,7 @@ init_usb (void) outw (0x0000, DEFAULT_PMBASE | 0x003c); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { int s3resume = 0; diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 943143a..68a9b48 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -213,7 +213,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { u32 reg32; diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index 81642a1..3192e5c 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -71,7 +71,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_gx2/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl [] = { diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index d8e9cd9..b3b4498 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -110,7 +110,7 @@ static void mb_gpio_init(void) } } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 6839332..2f7bd85 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -152,7 +152,7 @@ static void mb_gpio_init(void) } } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { int err; diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index ef3f7d2..18f48f6 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -85,7 +85,7 @@ static void mb_gpio_init(void) } } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index f397e37..c3f1c8a 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -149,7 +149,7 @@ static void mb_gpio_init(void) } } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { int err; diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c index e29423e..59e1c6d 100644 --- a/src/mainboard/mitac/6513wu/romstage.c +++ b/src/mainboard/mitac/6513wu/romstage.c @@ -35,7 +35,7 @@ #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c index be273f3..578de61 100644 --- a/src/mainboard/msi/ms6119/romstage.c +++ b/src/mainboard/msi/ms6119/romstage.c @@ -41,7 +41,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c index c3a7557..a6767bc 100644 --- a/src/mainboard/msi/ms6147/romstage.c +++ b/src/mainboard/msi/ms6147/romstage.c @@ -41,7 +41,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c index ff888bc..3811cc5 100644 --- a/src/mainboard/msi/ms6156/romstage.c +++ b/src/mainboard/msi/ms6156/romstage.c @@ -41,7 +41,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c index ae78990..4005ac8 100644 --- a/src/mainboard/msi/ms6178/romstage.c +++ b/src/mainboard/msi/ms6178/romstage.c @@ -36,7 +36,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { w83627hf_set_clksel_48(DUMMY_DEV); diff --git a/src/mainboard/nec/powermate2000/romstage.c b/src/mainboard/nec/powermate2000/romstage.c index d4a2d8f..97d0580 100644 --- a/src/mainboard/nec/powermate2000/romstage.c +++ b/src/mainboard/nec/powermate2000/romstage.c @@ -34,7 +34,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/nokia/ip530/romstage.c b/src/mainboard/nokia/ip530/romstage.c index 5c87867..39c75ca 100644 --- a/src/mainboard/nokia/ip530/romstage.c +++ b/src/mainboard/nokia/ip530/romstage.c @@ -40,7 +40,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index c4a278e..93dd7c2 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -198,7 +198,7 @@ static inline u16 read_acpi16(u32 addr) return inw(DEFAULT_PMBASE | addr); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { u32 reg32; diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 4f80550..436edc0 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -107,7 +107,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 52c5310..9b272a4 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -130,7 +130,7 @@ static void mb_gpio_init(void) outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 3 disabled */ } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c index af91bde..7dd4b48 100644 --- a/src/mainboard/rca/rm4100/romstage.c +++ b/src/mainboard/rca/rm4100/romstage.c @@ -94,7 +94,7 @@ static void mb_early_setup(void) pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { if (bist == 0) { diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 7cc1a1d..a4f55a8 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -251,7 +251,7 @@ static void init_artec_dongle(void) outb(0xf4, 0x88); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { u32 reg32; diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index c8b75e0..81b141e 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -120,7 +120,7 @@ static void default_superio_gpio_setup(void) outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */ } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { sysinfo_t sysinfo; diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 32f1ec5..f984af2 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -132,7 +132,7 @@ static void early_pch_init(void) pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index a3905ab..3abea10 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -172,7 +172,7 @@ static void setup_sio_gpios(void) it8772f_gpio_setup(DUMMY_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { int boot_mode = 0; diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index 82ac56f..fccd29a 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -40,7 +40,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index 0385cad..6b10a68 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -42,7 +42,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "arch/x86/lib/stages.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { static const struct mem_controller mch[] = { diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 405a2bc..9a637be 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -46,7 +46,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "arch/x86/lib/stages.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { static const struct mem_controller mch[] = { diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index 48945eb..09f4c57 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -43,7 +43,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "arch/x86/lib/stages.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { static const struct mem_controller mch[] = { diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 08b0ccd..3e51b73 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -45,7 +45,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "arch/x86/lib/stages.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { static const struct mem_controller mch[] = { diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index dfe0da2..868fbdc 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -45,7 +45,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "arch/x86/lib/stages.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { static const struct mem_controller mch[] = { diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c index 83e34b5..a52193f 100644 --- a/src/mainboard/supermicro/x7db8/romstage.c +++ b/src/mainboard/supermicro/x7db8/romstage.c @@ -111,7 +111,7 @@ int mainboard_set_fbd_clock(int speed) } } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { if (bist == 0) diff --git a/src/mainboard/technologic/ts5300/romstage.c b/src/mainboard/technologic/ts5300/romstage.c index 5d33bae..64de0c0 100644 --- a/src/mainboard/technologic/ts5300/romstage.c +++ b/src/mainboard/technologic/ts5300/romstage.c @@ -136,7 +136,7 @@ static void hard_reset(void) while (1) ; } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { volatile int i; diff --git a/src/mainboard/televideo/tc7020/romstage.c b/src/mainboard/televideo/tc7020/romstage.c index 15362e3..e733003 100644 --- a/src/mainboard/televideo/tc7020/romstage.c +++ b/src/mainboard/televideo/tc7020/romstage.c @@ -31,7 +31,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1) -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c index bb8d15c..ed87462 100644 --- a/src/mainboard/thomson/ip1000/romstage.c +++ b/src/mainboard/thomson/ip1000/romstage.c @@ -92,7 +92,7 @@ static void mb_early_setup(void) pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { if (bist == 0) { diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c index b3358b5..115b402 100644 --- a/src/mainboard/traverse/geos/romstage.c +++ b/src/mainboard/traverse/geos/romstage.c @@ -46,7 +46,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/tyan/s1846/romstage.c b/src/mainboard/tyan/s1846/romstage.c index 0c81e8e..78313fc 100644 --- a/src/mainboard/tyan/s1846/romstage.c +++ b/src/mainboard/tyan/s1846/romstage.c @@ -40,7 +40,7 @@ int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { pc87309_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c index 5d4fd0e..1b03982 100644 --- a/src/mainboard/tyan/s2735/romstage.c +++ b/src/mainboard/tyan/s2735/romstage.c @@ -34,7 +34,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/intel/e7501/reset_test.c" #include "lib/generic_sdram.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl[] = { diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 20f99cb..e7e65f2 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -79,7 +79,7 @@ static const struct mem_controller ctrl = { .channel0 = { DIMM0 }, }; -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { /* Enable multifunction for northbridge. */ diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c index 3f2a0c4..b3b515d 100644 --- a/src/mainboard/via/epia-m/romstage.c +++ b/src/mainboard/via/epia-m/romstage.c @@ -66,7 +66,7 @@ static void enable_shadow_ram(void) pci_write_config8(dev, 0x63, shadowreg); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { device_t dev; diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index b00ece1..c33acbe 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -373,7 +373,7 @@ static void EmbedComInit(void) #endif /* cache_as_ram.inc jumps to here. */ -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { u16 boot_mode; diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 7b62d86..969e2b6 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -42,7 +42,7 @@ #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) /* cache_as_ram.inc jumps to here. */ -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { u32 tolm; diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c index 2ede8d8..5c1477d 100644 --- a/src/mainboard/via/epia-n/romstage.c +++ b/src/mainboard/via/epia-n/romstage.c @@ -101,7 +101,7 @@ static void enable_shadow_ram(void) pci_write_config8(ctrl.d0f3, 0x82, shadowreg); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { unsigned long x; diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c index 1d312d7..e839541 100644 --- a/src/mainboard/via/epia/romstage.c +++ b/src/mainboard/via/epia/romstage.c @@ -69,7 +69,7 @@ static void enable_shadow_ram(void) pci_write_config8(dev, 0x63, shadowreg); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> static void main(unsigned long bist) { if (bist == 0) diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 0b1aeb4..aa7e2de 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -55,7 +55,7 @@ static const struct mem_controller ctrl = { .channel0 = { DIMM0 }, /* TODO: CN700 currently only supports 1 DIMM. */ }; -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { /* Enable multifunction for northbridge. */ diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index f6d58c8..d3ad0e2 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -83,7 +83,7 @@ static void enable_shadow_ram(const struct mem_controller *ctrl) pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg); } -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { /* Set statically so it should work with cx700 as well */ diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index 47ea722..f9b4eec 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -51,7 +51,7 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c index b9de16c..07216d5 100644 --- a/src/mainboard/wyse/s50/romstage.c +++ b/src/mainboard/wyse/s50/romstage.c @@ -49,7 +49,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_gx2/syspreinit.c" #include "cpu/amd/geode_lx/msrinit.c" -#include <cpu/intel/romstage.h> +#include <cpu/intel/car.h> void main(unsigned long bist) { static const struct mem_controller memctrl [] = {

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coreboot-gerrit August 2014