coreboot-gerrit August 2014

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New patch to review for coreboot: 5ecc8fd lenovo/x220: New port
by Vladimir Serbinenko 24 Aug '14

24 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6757 -gerrit commit 5ecc8fd541e388fb81d5039f425b3704625220a6 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Aug 24 22:40:33 2014 +0200 lenovo/x220: New port Change-Id: Ic213948e4d31457dda9b9f2d5a4f92cd34d1e57d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/Kconfig | 6 + src/mainboard/lenovo/x220/Kconfig | 86 +++++++ src/mainboard/lenovo/x220/Makefile.inc | 20 ++ src/mainboard/lenovo/x220/acpi/ec.asl | 26 ++ src/mainboard/lenovo/x220/acpi/gpe.asl | 13 + src/mainboard/lenovo/x220/acpi/platform.asl | 77 ++++++ .../lenovo/x220/acpi/sandybridge_pci_irqs.asl | 64 +++++ src/mainboard/lenovo/x220/acpi/superio.asl | 1 + src/mainboard/lenovo/x220/acpi_tables.c | 253 +++++++++++++++++++ src/mainboard/lenovo/x220/board_info.txt | 6 + src/mainboard/lenovo/x220/cmos.default | 17 ++ src/mainboard/lenovo/x220/cmos.layout | 167 +++++++++++++ src/mainboard/lenovo/x220/devicetree.cb | 188 +++++++++++++++ src/mainboard/lenovo/x220/dsdt.asl | 60 +++++ src/mainboard/lenovo/x220/fadt.c | 160 ++++++++++++ src/mainboard/lenovo/x220/hda_verb.h | 267 +++++++++++++++++++++ src/mainboard/lenovo/x220/mainboard.c | 217 +++++++++++++++++ src/mainboard/lenovo/x220/romstage.c | 265 ++++++++++++++++++++ src/mainboard/lenovo/x220/smihandler.c | 194 +++++++++++++++ src/mainboard/lenovo/x220/thermal.h | 30 +++ 20 files changed, 2117 insertions(+) diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index 812a586..c3ba61b 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -22,6 +22,11 @@ config BOARD_LENOVO_X201 help Lenovo X201 laptop. Consult wiki for details. +config BOARD_LENOVO_X220 + bool "ThinkPad X220" + help + Lenovo X220 laptop. Consult wiki for details. + config BOARD_LENOVO_X230 bool "ThinkPad X230" help @@ -50,6 +55,7 @@ endchoice source "src/mainboard/lenovo/x60/Kconfig" source "src/mainboard/lenovo/x200/Kconfig" source "src/mainboard/lenovo/x201/Kconfig" +source "src/mainboard/lenovo/x220/Kconfig" source "src/mainboard/lenovo/x230/Kconfig" source "src/mainboard/lenovo/t520/Kconfig" source "src/mainboard/lenovo/t530/Kconfig" diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig new file mode 100644 index 0000000..3ce4a47 --- /dev/null +++ b/src/mainboard/lenovo/x220/Kconfig @@ -0,0 +1,86 @@ +if BOARD_LENOVO_X220 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_INTEL_SOCKET_RPGA989 + select NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE + select SOUTHBRIDGE_INTEL_C216 + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select HAVE_SMI_HANDLER + select EARLY_CBMEM_INIT + select VGA + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + select SANDYBRIDGE_LVDS + + # Workaround for EC/KBC IRQ1. + select SERIRQ_CONTINUOUS_MODE + +config HAVE_MRC_CACHE + bool + default y + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default lenovo/x220 + +config MAINBOARD_PART_NUMBER + string + default "4299Y48" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config DRAM_RESET_GATE_GPIO + int + default 10 + +config VGA_BIOS_FILE + string + default "pci8086,0126.rom" + +config VGA_BIOS_ID + string + default "8086,0126" + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x17aa + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x21db + +config MAINBOARD_VENDOR + string + default "LENOVO" + +endif # BOARD_LENOVO_X220 diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc new file mode 100644 index 0000000..d514d4b --- /dev/null +++ b/src/mainboard/lenovo/x220/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/lenovo/x220/acpi/ec.asl b/src/mainboard/lenovo/x220/acpi/ec.asl new file mode 100644 index 0000000..4b3e72c --- /dev/null +++ b/src/mainboard/lenovo/x220/acpi/ec.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <ec/lenovo/h8/acpi/ec.asl> + +Scope(\_SB.PCI0.LPCB.EC) +{ +} diff --git a/src/mainboard/lenovo/x220/acpi/gpe.asl b/src/mainboard/lenovo/x220/acpi/gpe.asl new file mode 100644 index 0000000..80bee71 --- /dev/null +++ b/src/mainboard/lenovo/x220/acpi/gpe.asl @@ -0,0 +1,13 @@ + Method (_L01, 0, NotSerialized) + { + If (\_SB.PCI0.RP04.HPCS) + { + Sleep (100) + Store (0x01, \_SB.PCI0.RP04.HPCS) + If (\_SB.PCI0.RP04.PDC) + { + Store (0x01, \_SB.PCI0.RP04.PDC) + Notify (\_SB.PCI0.RP04, 0x00) + } + } + } diff --git a/src/mainboard/lenovo/x220/acpi/platform.asl b/src/mainboard/lenovo/x220/acpi/platform.asl new file mode 100644 index 0000000..72b9dbf --- /dev/null +++ b/src/mainboard/lenovo/x220/acpi/platform.asl @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + /* ME may not be up yet. */ + Store (0, \_TZ.MEB1) + Store (0, \_TZ.MEB2) + + /* Not implemented. */ + Return(Package(){0,0}) +} diff --git a/src/mainboard/lenovo/x220/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/x220/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..6c1c695 --- /dev/null +++ b/src/mainboard/lenovo/x220/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB + Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF + Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) + Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH + Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} diff --git a/src/mainboard/lenovo/x220/acpi/superio.asl b/src/mainboard/lenovo/x220/acpi/superio.asl new file mode 100644 index 0000000..a2657f1 --- /dev/null +++ b/src/mainboard/lenovo/x220/acpi/superio.asl @@ -0,0 +1 @@ +#include "../../../../drivers/pc80/ps2_controller.asl" diff --git a/src/mainboard/lenovo/x220/acpi_tables.c b/src/mainboard/lenovo/x220/acpi_tables.c new file mode 100644 index 0000000..5dfae0a --- /dev/null +++ b/src/mainboard/lenovo/x220/acpi_tables.c @@ -0,0 +1,253 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> + +extern const unsigned char AmlCode[]; +#if CONFIG_HAVE_ACPI_SLIC +unsigned long acpi_create_slic(unsigned long current); +#endif + +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} + +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); + + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; + + // the lid is open by default. + gnvs->lids = 1; + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, + const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + /* Pack GNVS into the ACPI table area */ + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " + "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); + *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes + acpi_save_gnvs(current); + break; + } + } + + /* And fill it */ + acpi_create_gnvs((global_nvs_t *)current); + + /* And tell SMI about it */ + smm_setup_structures((void *)current, NULL, NULL); + + current += sizeof(global_nvs_t); + ALIGN_CURRENT; + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + +#if CONFIG_HAVE_ACPI_SLIC + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/lenovo/x220/board_info.txt b/src/mainboard/lenovo/x220/board_info.txt new file mode 100644 index 0000000..7e7a41c --- /dev/null +++ b/src/mainboard/lenovo/x220/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +Board name: X220 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default new file mode 100644 index 0000000..ef3e920 --- /dev/null +++ b/src/mainboard/lenovo/x220/cmos.default @@ -0,0 +1,17 @@ +boot_option=Fallback +last_boot=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Enable +nmi=Enable +volume=0x3 +first_battery=Primary +bluetooth=Enable +wwan=Enable +wlan=Enable +touchpad=Enable +sata_mode=AHCI +fn_ctrl_swap=Disable +sticky_fn=Disable +trackpoint=Enable +hyper_threading=Enable diff --git a/src/mainboard/lenovo/x220/cmos.layout b/src/mainboard/lenovo/x220/cmos.layout new file mode 100644 index 0000000..cf64f92 --- /dev/null +++ b/src/mainboard/lenovo/x220/cmos.layout @@ -0,0 +1,167 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +400 8 h 0 volume + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 1 e 1 power_management_beeps +421 1 e 9 sata_mode +#422 2 r 1 unused + +# coreboot config options: cpu +424 1 e 2 hyper_threading +#425 7 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 549 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb new file mode 100644 index 0000000..96bed1e --- /dev/null +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -0,0 +1,188 @@ +chip northbridge/intel/sandybridge + + # Enable DisplayPort Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable Panel as LVDS and configure power delays + register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_power_cycle_delay" = "5" + register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms + register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms + register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms + register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms + register "gpu_use_spread_spectrum_clock" = "1" + register "gpu_lvds_dual_channel" = "0" + register "gpu_link_frequency_270_mhz" = "1" + register "gpu_lvds_num_lanes" = "4" + register "gpu_cpu_backlight" = "0x1155" + register "gpu_pch_backlight" = "0x06100610" + + device cpu_cluster 0 on + chip cpu/intel/socket_rPGA989 + device lapic 0 on end + end + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + # Coordinate with HW_ALL + register "pstate_coord_type" = "0xfe" + + register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + + register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + end + end + + device domain 0 on + device pci 00.0 on + subsystemid 0x17aa 0x21db + end # host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on + subsystemid 0x17aa 0x21db + end # vga controller + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "alt_gp_smi_en" = "0x0000" + register "gpi1_routing" = "2" + register "gpi8_routing" = "2" + + # Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata) + register "sata_port_map" = "0x7" + # Set max SATA speed to 6.0 Gb/s + register "sata_interface_speed_support" = "0x3" + + register "gen1_dec" = "0x7c1601" + register "gen2_dec" = "0x0c15e1" + register "gen4_dec" = "0x0c06a1" + + # Enable zero-based linear PCIe root port functions + register "pcie_port_coalesce" = "1" + + device pci 16.0 on + subsystemid 0x17aa 0x21db + end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on + subsystemid 0x17aa 0x21ce + end # Intel Gigabit Ethernet + device pci 1a.0 on + subsystemid 0x17aa 0x21db + end # USB2 EHCI #2 + device pci 1b.0 on + subsystemid 0x17aa 0x21db + end # High Definition Audio + device pci 1c.0 on + subsystemid 0x17aa 0x21db + end # PCIe Port #1 + device pci 1c.1 on + subsystemid 0x17aa 0x21db + end # PCIe Port #2 (wlan) + device pci 1c.2 on + subsystemid 0x17aa 0x21db + end # PCIe Port #3 + device pci 1c.3 on + subsystemid 0x17aa 0x21db + end # PCIe Port #4 + device pci 1c.4 on + subsystemid 0x17aa 0x21db + device pci 00.0 on + subsystemid 0x17aa 0x21db + end + device pci 00.1 on + subsystemid 0x17aa 0x21db + end + end # PCIe Port #5 (SD) + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on + subsystemid 0x17aa 0x21db + end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on #LPC bridge + subsystemid 0x17aa 0x21db + chip ec/lenovo/pmh7 + device pnp ff.1 on # dummy + end + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + end + + chip ec/lenovo/h8 + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + + register "config0" = "0xa6" + register "config1" = "0x01" + register "config2" = "0xa0" + register "config3" = "0x60" + + register "has_keyboard_backlight" = "0" + + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "has_power_management_beeps" = "1" + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xd0" + register "event5_enable" = "0xfc" + register "event6_enable" = "0x00" + register "event7_enable" = "0x81" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventa_enable" = "0x01" + register "eventb_enable" = "0xf0" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x0d" + end + end # LPC bridge + device pci 1f.2 on + subsystemid 0x17aa 0x21db + end # SATA Controller 1 + device pci 1f.3 on + subsystemid 0x17aa 0x21db + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 on + subsystemid 0x17aa 0x21db + end # Thermal + end + end +end diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl new file mode 100644 index 0000000..b6b4b33 --- /dev/null +++ b/src/mainboard/lenovo/x220/dsdt.asl @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define THINKPAD_EC_GPE 17 +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define RP04_IS_EXPRESSCARD 1 +#define EC_LENOVO_H8_ME_WORKAROUND 1 +#define HAVE_LCD_SCREEN 1 + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + #include <cpu/intel/model_206ax/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> +} diff --git a/src/mainboard/lenovo/x220/fadt.c b/src/mainboard/lenovo/x220/fadt.c new file mode 100644 index 0000000..27e6303 --- /dev/null +++ b/src/mainboard/lenovo/x220/fadt.c @@ -0,0 +1,160 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), + 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, "CORE", 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 101; /* c2 not supported */ + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/lenovo/x220/hda_verb.h b/src/mainboard/lenovo/x220/hda_verb.h new file mode 100644 index 0000000..6cf79c5 --- /dev/null +++ b/src/mainboard/lenovo/x220/hda_verb.h @@ -0,0 +1,267 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Vendor Name : Conexant + * Vendor ID : 0x14f1506e + * Subsystem ID : 0x17aa21db + * Revision ID : 0x100002 + */ + + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x14f1506e, // Codec Vendor / Device ID: Conexant CX20590 + 0x17aa21db, // Subsystem ID + 0x00000077, // Number of 4 dword sets + +/* Bits 31:28 - Codec Address */ +/* Bits 27:20 - NID */ +/* Bits 19:8 - Verb ID */ +/* Bits 7:0 - Payload */ + +/* NID 0x01 - NodeInfo */ + 0x001720DB, + 0x00172121, + 0x001722AA, + 0x00172317, + + 0x01971C40, + 0x01971D10, + 0x01971E21, + 0x01971F04, + + 0x01A71C50, + 0x01A71D90, + 0x01A71EA1, + 0x01A71F61, + + 0x01B71C60, + 0x01B71D10, + 0x01B71EA1, + 0x01B71F04, + + 0x01C71C1F, + 0x01C71D40, + 0x01C71E21, + 0x01C71F61, + + 0x01D71CF0, + 0x01D71D01, + 0x01D71EF0, + 0x01D71F40, + + 0x01E71CF0, + 0x01E71D01, + 0x01E71EF0, + 0x01E71F40, + + 0x01F71C10, + 0x01F71D01, + 0x01F71E17, + 0x01F71F90, + + 0x02071CF0, + 0x02071D01, + 0x02071EF0, + 0x02071F40, + + 0x02271CF0, + 0x02271D01, + 0x02271EF0, + 0x02271F40, + + 0x02371C70, + 0x02371D01, + 0x02371EA6, + 0x02371F90, + + /* + * Hardware EQ Parameters + * Sample Rate 88200 + */ + 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, + 0x0227AA3E, 0x0227ABEB, 0x0227AC00, 0x0227AD80, + 0x0227A681, 0x0227A782, 0x0227A829, 0x0227A981, + 0x0227AA82, 0x0227AB29, 0x0227AC01, 0x0227AD80, + 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, + 0x0227AA3E, 0x0227ABEB, 0x0227AC02, 0x0227AD80, + 0x0227A67E, 0x0227A77B, 0x0227A846, 0x0227A97E, + 0x0227AA7B, 0x0227AB46, 0x0227AC03, 0x0227AD80, + 0x0227A6C1, 0x0227A77F, 0x0227A898, 0x0227A9C1, + 0x0227AA7F, 0x0227AB98, 0x0227AC04, 0x0227AD80, + 0x0227A63E, 0x0227A7D1, 0x0227A84F, 0x0227A93E, + 0x0227AAD1, 0x0227AB4F, 0x0227AC05, 0x0227AD80, + 0x0227A683, 0x0227A7BE, 0x0227A855, 0x0227A983, + 0x0227AABE, 0x0227AB55, 0x0227AC06, 0x0227AD80, + 0x0227A63D, 0x0227A7B9, 0x0227A856, 0x0227A93D, + 0x0227AAB9, 0x0227AB56, 0x0227AC07, 0x0227AD80, + 0x0227A67C, 0x0227A741, 0x0227A8AB, 0x0227A97C, + 0x0227AA41, 0x0227ABAB, 0x0227AC08, 0x0227AD80, + 0x0227A6C3, 0x0227A775, 0x0227A85A, 0x0227A9C3, + 0x0227AA75, 0x0227AB5A, 0x0227AC09, 0x0227AD80, + 0x0227A63F, 0x0227A79E, 0x0227A829, 0x0227A93F, + 0x0227AA9E, 0x0227AB29, 0x0227AC0A, 0x0227AD80, + 0x0227A682, 0x0227A7E3, 0x0227A867, 0x0227A982, + 0x0227AAE3, 0x0227AB67, 0x0227AC0B, 0x0227AD80, + 0x0227A63E, 0x0227A74F, 0x0227A89D, 0x0227A93E, + 0x0227AA4F, 0x0227AB9D, 0x0227AC0C, 0x0227AD80, + 0x0227A67D, 0x0227A71C, 0x0227A899, 0x0227A97D, + 0x0227AA1C, 0x0227AB99, 0x0227AC0D, 0x0227AD80, + 0x0227A6C2, 0x0227A712, 0x0227A839, 0x0227A9C2, + 0x0227AA12, 0x0227AB39, 0x0227AC0E, 0x0227AD80, + 0x0227A63F, 0x0227A708, 0x0227A856, 0x0227A93F, + 0x0227AA08, 0x0227AB56, 0x0227AC0F, 0x0227AD80, + 0x0227A68E, 0x0227A7ED, 0x0227A89D, 0x0227A98E, + 0x0227AAED, 0x0227AB9D, 0x0227AC10, 0x0227AD80, + 0x0227A637, 0x0227A78F, 0x0227A853, 0x0227A937, + 0x0227AA8F, 0x0227AB53, 0x0227AC11, 0x0227AD80, + 0x0227A671, 0x0227A712, 0x0227A863, 0x0227A971, + 0x0227AA12, 0x0227AB63, 0x0227AC12, 0x0227AD80, + 0x0227A6C9, 0x0227A768, 0x0227A856, 0x0227A9C9, + 0x0227AA68, 0x0227AB56, 0x0227AC13, 0x0227AD80, + 0x0227A642, 0x0227A709, 0x0227A838, 0x0227A942, + 0x0227AA09, 0x0227AB38, 0x0227AC14, 0x0227AD80, + 0x0227A69C, 0x0227A78A, 0x0227A867, 0x0227A99C, + 0x0227AA8A, 0x0227AB67, 0x0227AC15, 0x0227AD80, + 0x0227A634, 0x0227A717, 0x0227A8E3, 0x0227A934, + 0x0227AA17, 0x0227ABE3, 0x0227AC16, 0x0227AD80, + 0x0227A663, 0x0227A775, 0x0227A899, 0x0227A963, + 0x0227AA75, 0x0227AB99, 0x0227AC17, 0x0227AD80, + 0x0227A6C9, 0x0227A7DE, 0x0227A8E5, 0x0227A9C9, + 0x0227AADE, 0x0227ABE5, 0x0227AC18, 0x0227AD80, + 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, + 0x0227AA00, 0x0227AB00, 0x0227AC19, 0x0227AD80, + + /* + * Hardware EQ Parameters + * Sample Rate 96000 + */ + 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, + 0x0227AA4E, 0x0227AB88, 0x0227AC1A, 0x0227AD80, + 0x0227A681, 0x0227A762, 0x0227A8EE, 0x0227A981, + 0x0227AA62, 0x0227ABEE, 0x0227AC1B, 0x0227AD80, + 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, + 0x0227AA4E, 0x0227AB88, 0x0227AC1C, 0x0227AD80, + 0x0227A67E, 0x0227A79A, 0x0227A8E7, 0x0227A97E, + 0x0227AA9A, 0x0227ABE7, 0x0227AC1D, 0x0227AD80, + 0x0227A6C1, 0x0227A760, 0x0227A8C3, 0x0227A9C1, + 0x0227AA60, 0x0227ABC3, 0x0227AC1E, 0x0227AD80, + 0x0227A63E, 0x0227A7E9, 0x0227A84B, 0x0227A93E, + 0x0227AAE9, 0x0227AB4B, 0x0227AC1F, 0x0227AD80, + 0x0227A683, 0x0227A76C, 0x0227A8F2, 0x0227A983, + 0x0227AA6C, 0x0227ABF2, 0x0227AC20, 0x0227AD80, + 0x0227A63D, 0x0227A7E7, 0x0227A880, 0x0227A93D, + 0x0227AAE7, 0x0227AB80, 0x0227AC21, 0x0227AD80, + 0x0227A67C, 0x0227A793, 0x0227A80E, 0x0227A97C, + 0x0227AA93, 0x0227AB0E, 0x0227AC22, 0x0227AD80, + 0x0227A6C3, 0x0227A72F, 0x0227A835, 0x0227A9C3, + 0x0227AA2F, 0x0227AB35, 0x0227AC23, 0x0227AD80, + 0x0227A63F, 0x0227A7A5, 0x0227A8FE, 0x0227A93F, + 0x0227AAA5, 0x0227ABFE, 0x0227AC24, 0x0227AD80, + 0x0227A682, 0x0227A798, 0x0227A89D, 0x0227A982, + 0x0227AA98, 0x0227AB9D, 0x0227AC25, 0x0227AD80, + 0x0227A63E, 0x0227A772, 0x0227A839, 0x0227A93E, + 0x0227AA72, 0x0227AB39, 0x0227AC26, 0x0227AD80, + 0x0227A67D, 0x0227A767, 0x0227A863, 0x0227A97D, + 0x0227AA67, 0x0227AB63, 0x0227AC27, 0x0227AD80, + 0x0227A6C1, 0x0227A7E7, 0x0227A8C8, 0x0227A9C1, + 0x0227AAE7, 0x0227ABC8, 0x0227AC28, 0x0227AD80, + 0x0227A63F, 0x0227A71B, 0x0227A81A, 0x0227A93F, + 0x0227AA1B, 0x0227AB1A, 0x0227AC29, 0x0227AD80, + 0x0227A68D, 0x0227A763, 0x0227A872, 0x0227A98D, + 0x0227AA63, 0x0227AB72, 0x0227AC2A, 0x0227AD80, + 0x0227A638, 0x0227A733, 0x0227A809, 0x0227A938, + 0x0227AA33, 0x0227AB09, 0x0227AC2B, 0x0227AD80, + 0x0227A672, 0x0227A79C, 0x0227A88E, 0x0227A972, + 0x0227AA9C, 0x0227AB8E, 0x0227AC2C, 0x0227AD80, + 0x0227A6C8, 0x0227A7B1, 0x0227A8DD, 0x0227A9C8, + 0x0227AAB1, 0x0227ABDD, 0x0227AC2D, 0x0227AD80, + 0x0227A641, 0x0227A7E1, 0x0227A8D8, 0x0227A941, + 0x0227AAE1, 0x0227ABD8, 0x0227AC2E, 0x0227AD80, + 0x0227A699, 0x0227A70D, 0x0227A820, 0x0227A999, + 0x0227AA0D, 0x0227AB20, 0x0227AC2F, 0x0227AD80, + 0x0227A634, 0x0227A7FE, 0x0227A823, 0x0227A934, + 0x0227AAFE, 0x0227AB23, 0x0227AC30, 0x0227AD80, + 0x0227A666, 0x0227A7F2, 0x0227A8E0, 0x0227A966, + 0x0227AAF2, 0x0227ABE0, 0x0227AC31, 0x0227AD80, + 0x0227A6C9, 0x0227A720, 0x0227A804, 0x0227A9C9, + 0x0227AA20, 0x0227AB04, 0x0227AC32, 0x0227AD80, + 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, + 0x0227AA00, 0x0227AB00, 0x0227AC33, 0x0227AD80, + + /* SAFEDSP Parameters */ + 0x022782C1, 0x02277127, 0x02277227, 0x02278801, + 0x02278C58, 0x02278E90, 0x0227890A, 0x02278A14, + 0x02278B0F, 0x0017B008, + + /* Misc entries */ + 0x00B707C0, /* Enable PortB as Output with HP amp */ + 0x00D70740, /* Enable PortD as Output */ + 0x0017A200, /* Disable ClkEn of PortSenseTst */ + 0x0017C621, /* Slave Port - Port A used as microphone input for + combo Jack + Master Port - Port B used for Jack Presence Detect + Enable Combo Jack Detection */ + 0x0017A208, /* Enable ClkEn of PortSenseTst */ + 0x00170500, /* Set power state to D0 */ + + /* --- Next Codec --- */ + +/* Vendor Name : Intel + * Vendor ID : 0x80862806 + * Subsystem ID : 0x80860101 + * Revision ID : 0x100000 + */ + /* coreboot specific header */ + 0x80862805, // Codec Vendor / Device ID: Intel PantherPoint HDMI + 0x80860101, // Subsystem ID + 0x00000004, // Number of IDs + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + 0x30172001, + 0x30172101, + 0x30172286, + 0x30172380, + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + 0x30571c10, + 0x30571d00, + 0x30571e56, + 0x30571f18, + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + 0x30671c20, + 0x30671d00, + 0x30671e56, + 0x30671f18, + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + 0x30771c30, + 0x30771d00, + 0x30771e56, + 0x30771f18 +}; + +static const u32 mainboard_pc_beep_verbs[] = { + 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ +}; + +static const u32 mainboard_pc_beep_verbs_size = + ARRAY_SIZE(mainboard_pc_beep_verbs); diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c new file mode 100644 index 0000000..8d90c22 --- /dev/null +++ b/src/mainboard/lenovo/x220/mainboard.c @@ -0,0 +1,217 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011-2012 Google Inc. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#if CONFIG_VGA_ROM_RUN +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include "hda_verb.h" +#include <southbridge/intel/bd82x6x/pch.h> +#include <smbios.h> +#include <device/pci.h> +#include <cbfs.h> +#include <pc80/keyboard.h> +#include <ec/lenovo/h8/h8.h> +#include <build.h> +#include <device/azalia_device.h> + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); +} + +#if CONFIG_VGA_ROM_RUN +static int int15_handler(void) +{ + int res = 0; + + printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", + __func__, X86_AX); + + switch (X86_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video bios default + */ + X86_AX = 0x005f; + X86_CL = 0x00; /* Use video bios default */ + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV (eDP) + * bit 2 = EFP + * bit 3 = LFP + * bit 4 = CRT2 + * bit 5 = TV2 (eDP) + * bit 6 = EFP2 + * bit 7 = LFP2 + */ + X86_AX = 0x005f; + X86_CX = 0x0000; /* Use video bios default */ + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + X86_AX = 0x005f; + X86_CX = 0x0001; /* Int-LVDS */ + res = 1; + break; + case 0x5f70: + switch (X86_CH) { + case 0: + /* Get Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", + X86_CH); + break; + } + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + break; + } + return res; +} +#endif + +const char *smbios_mainboard_bios_version(void) +{ + /* Satisfy thinkpad_acpi. */ + if (strlen(CONFIG_LOCALVERSION)) + return "CBET4000 " CONFIG_LOCALVERSION; + else + return "CBET4000 " COREBOOT_VERSION; +} + +const char *smbios_mainboard_version(void) +{ + return "ThinkPad X220"; +} + +/* Audio Setup */ + +static void verb_setup(void) +{ + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); + pc_beep_verbs = mainboard_pc_beep_verbs; + pc_beep_verbs_size = mainboard_pc_beep_verbs_size; + +} + +static void mainboard_init(device_t dev) +{ + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00802005; + RCBA32(0x38c0) = 0x00000007; + + /* This sneaked in here, because X201 SuperIO chip isn't really + connected to anything and hence we don't init it. + */ + pc_keyboard_init(); + + /* Enable expresscard hotplug events. */ + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)), + 0xd8, + pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)), 0xd8) + | (1 << 30)); + pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x1c, 3)), + 0x42, 0x142); +} + +static int mainboard_smbios_data(device_t dev, int *handle, unsigned long *current) +{ + int len; + char tpec[] = "IBM ThinkPad Embedded Controller -[ ]-"; + const char *oem_strings[] = { + tpec, + }; + + h8_build_id_and_function_spec_version(tpec + 35, 17); + len = smbios_write_type11(current, (*handle)++, oem_strings, ARRAY_SIZE(oem_strings)); + + return len; +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + dev->ops->get_smbios_data = mainboard_smbios_data; + +#if CONFIG_VGA_ROM_RUN + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif + verb_setup(); +} + +void h8_mainboard_init_dock (void) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c new file mode 100644 index 0000000..04d577b --- /dev/null +++ b/src/mainboard/lenovo/x220/romstage.c @@ -0,0 +1,265 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include "southbridge/intel/bd82x6x/gpio.h" +#include <arch/cpu.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> +#include <cbfs.h> + +static void pch_enable_lpc(void) +{ + /* X230 EC Decode Range Port60/64, Port62/66 */ + /* Enable EC, PS/2 Keyboard/Mouse */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | + COMA_LPC_EN); + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); + + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + + pci_write_config32(PCH_LPC_DEV, 0xac, + 0x80010000); +} + +static void rcba_config(void) +{ + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP WLAN INTA -> PIRQB + * D28IP_P2IP ETH0 INTB -> PIRQF + * D28IP_P3IP SDCARD INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + * Trackpad interrupt is edge triggered and cannot be shared. + * TRACKPAD -> PIRQG + + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | + (INTC << D28IP_P3IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); + + /* Disable unused devices (board specific) */ + RCBA32(FD) = 0x1fe41fe3; + RCBA32(BUC) = 0; +} + +static void +init_usb (void) +{ + const u32 rcba_dump[64] = { + /* 3500 */ 0x20000153, 0x20000f57, 0x20000f57, 0x20000f57, + /* 3510 */ 0x20000f57, 0x20000f57, 0x20000153, 0x20000153, + /* 3520 */ 0x20000f57, 0x20000f57, 0x20000f57, 0x20000f57, + /* 3530 */ 0x20000f57, 0x20000f57, 0x00000000, 0x00000000, + /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3560 */ 0x020c0001, 0x000024a3, 0x00040002, 0x01000050, + /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, + /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3590 */ 0x00000003, 0x000000c0, 0x00000000, 0x00000000, + /* 35a0 */ 0x0fc00201, 0x102d0200, 0x00000000, 0x00000000, + /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + }; + int i; + /* Activate PMBAR. */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ + + /* Unlock registers. */ + outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c); + + for (i = 0; i < 64; i++) + write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), rcba_dump[i]); + + pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); + + /* Relock registers. */ + outw (0x0000, DEFAULT_PMBASE | 0x003c); +} + +#include <cpu/intel/romstage.h> +void main(unsigned long bist) +{ + int s3resume = 0; + u32 pm1_cnt; + u16 pm1_sts; + spd_raw_data spd[4]; + + if (MCHBAR16(SSKPD) == 0xCAFE) { + outb(0x6, 0xcf9); + hlt (); + } + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + + if (bist == 0) + enable_lapic(); + + pch_enable_lpc(); + + /* Enable GPIOs */ + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); + + outl(0x3963a5ff, DEFAULT_GPIOBASE); + outl(0x9ebf6aff, DEFAULT_GPIOBASE + 4); + outl(0x66ff7ffb, DEFAULT_GPIOBASE + 0xc); + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); + outl(0x00002043, DEFAULT_GPIOBASE + 0x2c); + outl(0x02ff04fe, DEFAULT_GPIOBASE + 0x30); + outl(0x1f47fbf5, DEFAULT_GPIOBASE + 0x34); + outl(0xbdecff87, DEFAULT_GPIOBASE + 0x38); + outl(0x000000f0, DEFAULT_GPIOBASE + 0x40); + outl(0x00000ff0, DEFAULT_GPIOBASE + 0x44); + outl(0x00000fcf, DEFAULT_GPIOBASE + 0x48); + + init_usb(); + + /* Initialize console device(s) */ + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + sandybridge_early_initialization(SANDYBRIDGE_MOBILE); + printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); + + /* Check PM1_STS[15] to see if we are waking from Sx */ + pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); + + /* Read PM1_CNT[12:10] to determine which Sx state */ + pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); + + if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + s3resume = 1; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } + } + + post_code(0x38); + /* Enable SPD ROMs and DDR-III DRAM */ + enable_smbus(); + + post_code(0x39); + + post_code(0x3a); + timestamp_add_now(TS_BEFORE_INITRAM); + + memset (spd, 0, sizeof (spd)); + read_spd (&spd[0], 0x50); + read_spd (&spd[2], 0x51); + + init_dram_ddr3 (spd, 1, TCK_800MHZ, s3resume); + + timestamp_add_now(TS_AFTER_INITRAM); + post_code(0x3c); + + rcba_config(); + post_code(0x3d); + + MCHBAR16(SSKPD) = 0xCAFE; + +#if CONFIG_HAVE_ACPI_RESUME + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + + *(u32 *)CBMEM_BOOT_MODE = 0; + *(u32 *)CBMEM_RESUME_BACKUP = 0; + + if (s3resume) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + if (resume_backup_memory) { + *(u32 *)CBMEM_BOOT_MODE = 2; + *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; + } + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + } else { + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + } +#endif + post_code(0x3f); + timestamp_add_now(TS_END_ROMSTAGE); +} diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c new file mode 100644 index 0000000..5bcde1c --- /dev/null +++ b/src/mainboard/lenovo/x220/smihandler.c @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <pc80/mc146818rtc.h> +#include <ec/lenovo/h8/h8.h> +#include <delay.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/me.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <cpu/intel/model_206ax/model_206ax.h> + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); + /* Enable 0x1600/0x1600 register pair */ + ec_set_bit(0x00, 0x05); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + switch (smif) { + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +static void mainboard_smi_brightness_up(void) +{ + u8 value; + + if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) + pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); +} + +static void mainboard_smi_brightness_down(void) +{ + u8 value; + + if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) + pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, + (value - 0x10) & 0xf0); +} + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); + + switch (event) { + case 0x14: + /* brightness up */ + mainboard_smi_brightness_up(); + break; + case 0x15: + /* brightness down */ + mainboard_smi_brightness_down(); + break; + default: + break; + } +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << 12)) + mainboard_smi_handle_ec_sci(); +} + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + u8 tmp; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, + data); + + if (!pmbase) + return 0; + + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route H8SCI to SCI */ + outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x02; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route H8SCI# to SMI */ + outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, + pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_FINALIZE: + printk(BIOS_DEBUG, "APMC: FINALIZE\n"); + if (mainboard_finalized) { + printk(BIOS_DEBUG, "APMC#: Already finalized\n"); + return 0; + } + + intel_me_finalize_smm(); + intel_pch_finalize_smm(); + intel_sandybridge_finalize_smm(); + intel_model_206ax_finalize_smm(); + + mainboard_finalized = 1; + break; + + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + u32 gpe_rout; + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + + /* Enable EC WAKE GPE. */ + outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); + gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + /* Redirect EC WAKE GPE to SCI. */ + gpe_rout &= ~(3 << 26); + gpe_rout |= (2 << 26); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + } + } +} diff --git a/src/mainboard/lenovo/x220/thermal.h b/src/mainboard/lenovo/x220/thermal.h new file mode 100644 index 0000000..ab24bb1 --- /dev/null +++ b/src/mainboard/lenovo/x220/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef X230_THERMAL_H +#define X230_THERMAL_H + + /* Temperature which OS will shutdown at */ + #define CRITICAL_TEMPERATURE 100 + + /* Temperature which OS will throttle CPU */ + #define PASSIVE_TEMPERATURE 90 + +#endif

1 0

New patch to review for coreboot: d8111b0 lenovo/x230: Add subsystem ids.
by Vladimir Serbinenko 24 Aug '14

24 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6756 -gerrit commit d8111b0eb035dd6d7c9c0538f492f66da6da40fc Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Aug 24 22:38:56 2014 +0200 lenovo/x230: Add subsystem ids. Change-Id: I917a89da50d8efe998c368ba46206f2a1c580fd0 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x230/devicetree.cb | 60 ++++++++++++++++++++++++++------- 1 file changed, 47 insertions(+), 13 deletions(-) diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 1a93ad8..9dc559c 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -39,9 +39,13 @@ chip northbridge/intel/sandybridge end device domain 0 on - device pci 00.0 on end # host bridge + device pci 00.0 on + subsystemid 0x17aa 0x21fa + end # host bridge device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # vga controller + device pci 02.0 on + subsystemid 0x17aa 0x21fa + end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "pirqa_routing" = "0x8b" @@ -73,25 +77,50 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 + device pci 14.0 on + subsystemid 0x17aa 0x21fa + end # USB 3.0 Controller + device pci 16.0 on + subsystemid 0x17aa 0x21fa + end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 (expresscard) + device pci 19.0 on + subsystemid 0x17aa 0x21f3 + end # Intel Gigabit Ethernet + device pci 1a.0 on + subsystemid 0x17aa 0x21fa + end # USB2 EHCI #2 + device pci 1b.0 on + subsystemid 0x17aa 0x21fa + end # High Definition Audio + device pci 1c.0 on + subsystemid 0x17aa 0x21fa + device pci 00.0 on + subsystemid 0x17aa 0x21fa + end + device pci 00.1 on + subsystemid 0x17aa 0x21fa + end + end # PCIe Port #1 + device pci 1c.1 on + subsystemid 0x17aa 0x21fa + end # PCIe Port #2 + device pci 1c.2 on + subsystemid 0x17aa 0x21fa + end # PCIe Port #3 (expresscard) device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 + device pci 1d.0 on + subsystemid 0x17aa 0x21fa + end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge device pci 1f.0 on #LPC bridge + subsystemid 0x17aa 0x21fa chip ec/lenovo/pmh7 device pnp ff.1 on # dummy end @@ -132,8 +161,11 @@ chip northbridge/intel/sandybridge register "evente_enable" = "0x0d" end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 + device pci 1f.2 on + subsystemid 0x17aa 0x21fa + end # SATA Controller 1 device pci 1f.3 on + subsystemid 0x17aa 0x21fa # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -147,7 +179,9 @@ chip northbridge/intel/sandybridge end end # SMBus device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device pci 1f.6 on + subsystemid 0x17aa 0x21fa + end # Thermal end end end

1 0

New patch to review for coreboot: feaff0c sandybridge: Native gfx init.
by Vladimir Serbinenko 24 Aug '14

24 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6755 -gerrit commit feaff0c15cd3e65a5f7714bcb03c383f880988ca Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Aug 24 22:38:07 2014 +0200 sandybridge: Native gfx init. Change-Id: I07590086ffe3b1d068fa6ae6b156039cc2e55893 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/sandybridge/Kconfig | 4 + src/northbridge/intel/sandybridge/Makefile.inc | 1 + .../intel/sandybridge/gma_sandybridge_lvds.c | 558 +++++++++++++++++++++ 3 files changed, 563 insertions(+) diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 1080724..18fd175 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -63,6 +63,10 @@ config IVYBRIDGE_LVDS bool default n +config SANDYBRIDGE_LVDS + bool + default n + config MRC_CACHE_SIZE hex depends on !CHROMEOS diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 83e9b9c..5dfd877 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -21,6 +21,7 @@ ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c ramstage-$(CONFIG_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c +ramstage-$(CONFIG_SANDYBRIDGE_LVDS) += gma_sandybridge_lvds.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-y += mrccache.c diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c new file mode 100644 index 0000000..77c5b6f --- /dev/null +++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c @@ -0,0 +1,558 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013, 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 or (at your option) + * any later version of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <string.h> + +#include <drivers/intel/gma/edid.h> +#include <drivers/intel/gma/i915.h> +#include <drivers/intel/gma/intel_bios.h> +#include "gma.h" +#include "chip.h" +#include <pc80/vga.h> +#include <pc80/vga_io.h> +#include <device/pci_def.h> +#include <device/pci_rom.h> + +#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) + +static size_t generate_vbt(const struct northbridge_intel_sandybridge_config *conf, + void *vbt) +{ + struct vbt_header *head = vbt; + struct bdb_header *bdb_head; + struct bdb_general_features *genfeat; + u8 *ptr; + + memset(head, 0, sizeof (*head)); + + memcpy(head->signature, "$VBT SNB/IVB-MOBILE ", 20); + head->version = 100; + head->header_size = sizeof (*head); + head->bdb_offset = sizeof (*head); + + bdb_head = (struct bdb_header *) (head + 1); + memset(bdb_head, 0, sizeof (*bdb_head)); + memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); + bdb_head->version = 0xa8; + bdb_head->header_size = sizeof (*bdb_head); + + ptr = (u8 *) (bdb_head + 1); + + ptr[0] = BDB_GENERAL_FEATURES; + ptr[1] = sizeof (*genfeat); + ptr[2] = sizeof (*genfeat) >> 8; + ptr += 3; + + genfeat = (struct bdb_general_features *) ptr; + memset(genfeat, 0, sizeof (*genfeat)); + genfeat->panel_fitting = 3; + genfeat->flexaim = 1; + genfeat->download_ext_vbt = 1; + genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; + genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; + genfeat->rsvd10 = 0x4; + genfeat->legacy_monitor_detect = 1; + genfeat->int_crt_support = 1; + genfeat->dp_ssc_enb = 1; + + ptr += sizeof (*genfeat); + + bdb_head->bdb_size = ptr - (u8 *)bdb_head; + head->vbt_size = ptr - (u8 *)head; + head->vbt_checksum = 0; + return ptr - (u8 *)head; +} + +static void train_link(u32 mmio) +{ + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + + write32(mmio + 0xf000c, 0x2040); + write32(mmio + 0xf000c, 0x2050); + write32(mmio + 0x60100, 0x44000); + write32(mmio + 0xf000c, 0x22050); + + mdelay(1); + + write32(mmio + 0x000f0018, 0x0000008ff); + write32(mmio + 0x000f1018, 0x0000008ff); + + write32(mmio + 0x000f000c, 0x001a2050); + write32(mmio + 0x00060100, 0x001c4000); + + write32(mmio + 0x00060100, 0x801c4000); + write32(mmio + 0x000f000c, 0x801a2050); + + write32(mmio + 0x00060100, 0x801c4000); + write32(mmio + 0x000f000c, 0x801a2050); + mdelay(1); + + read32(mmio + 0x000f0014); // = 0x00000100 + write32(mmio + 0x000f0014, 0x00000100); + write32(mmio + 0x00060100, 0x901c4000); + write32(mmio + 0x000f000c, 0x801a2150); + mdelay(1); + read32(mmio + 0x000f0014); // = 0x00000600 +} + +static void power_port(u32 mmio) +{ + read32(mmio + 0x000e1100); // = 0x00000000 + write32(mmio + 0x000e1100, 0x00000000); + write32(mmio + 0x000e1100, 0x00010000); + read32(mmio + 0x000e1100); // = 0x00010000 + read32(mmio + 0x000e1100); // = 0x00010000 + read32(mmio + 0x000e1100); // = 0x00000000 + write32(mmio + 0x000e1100, 0x00000000); + read32(mmio + 0x000e1100); // = 0x00000000 + read32(mmio + 0x000e4200); // = 0x0000001c + write32(mmio + 0x000e4210, 0x8004003e); + write32(mmio + 0x000e4214, 0x80060002); + write32(mmio + 0x000e4218, 0x01000000); + read32(mmio + 0x000e4210); // = 0x5144003e + write32(mmio + 0x000e4210, 0x5344003e); + read32(mmio + 0x000e4210); // = 0x0144003e + write32(mmio + 0x000e4210, 0x8074003e); + read32(mmio + 0x000e4210); // = 0x5144003e + read32(mmio + 0x000e4210); // = 0x5144003e + write32(mmio + 0x000e4210, 0x5344003e); + read32(mmio + 0x000e4210); // = 0x0144003e + write32(mmio + 0x000e4210, 0x8074003e); + read32(mmio + 0x000e4210); // = 0x5144003e + read32(mmio + 0x000e4210); // = 0x5144003e + write32(mmio + 0x000e4210, 0x5344003e); + read32(mmio + 0x000e4210); // = 0x0144003e + write32(mmio + 0x000e4210, 0x8074003e); + read32(mmio + 0x000e4210); // = 0x5144003e + read32(mmio + 0x000e4210); // = 0x5144003e + write32(mmio + 0x000e4210, 0x5344003e); + write32(mmio + 0x000e4f00, 0x0100030c); + write32(mmio + 0x000e4f04, 0x00b8230c); + write32(mmio + 0x000e4f08, 0x06f8930c); + write32(mmio + 0x000e4f0c, 0x09f8e38e); + write32(mmio + 0x000e4f10, 0x00b8030c); + write32(mmio + 0x000e4f14, 0x0b78830c); + write32(mmio + 0x000e4f18, 0x0ff8d3cf); + write32(mmio + 0x000e4f1c, 0x01e8030c); + write32(mmio + 0x000e4f20, 0x0ff863cf); + write32(mmio + 0x000e4f24, 0x0ff803cf); + write32(mmio + 0x000c4030, 0x00001000); + read32(mmio + 0x000c4000); // = 0x00000000 + write32(mmio + 0x000c4030, 0x00001000); + read32(mmio + 0x000e1150); // = 0x0000001c + write32(mmio + 0x000e1150, 0x0000089c); + write32(mmio + 0x000fcc00, 0x01986f00); + write32(mmio + 0x000fcc0c, 0x01986f00); + write32(mmio + 0x000fcc18, 0x01986f00); + write32(mmio + 0x000fcc24, 0x01986f00); + read32(mmio + 0x000c4000); // = 0x00000000 + read32(mmio + 0x000e1180); // = 0x40000002 +} + +int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, + u32 physbase, u16 piobase, u32 mmio, u32 lfb) +{ + int i; + u8 edid_data[128]; + struct edid edid; + u32 hactive, vactive, right_border, bottom_border; + int hpolarity, vpolarity; + u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; + u32 candp1, candn; + u32 best_delta = 0xffffffff; + u32 target_frequency; + u32 pixel_p1 = 1; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; + u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 data_m1; + u32 data_n1 = 0x00800000; + u32 link_m1; + u32 link_n1 = 0x00080000; + + write32(mmio + 0x00070080, 0x00000000); + write32(mmio + DSPCNTR(0), 0x00000000); + write32(mmio + 0x00071180, 0x00000000); + write32(mmio + CPU_VGACNTRL, 0x0000298e | VGA_DISP_DISABLE); + write32(mmio + 0x0007019c, 0x00000000); + write32(mmio + 0x0007119c, 0x00000000); + write32(mmio + 0x000ec008, 0x2c010000); + write32(mmio + 0x000ec020, 0x2c010000); + write32(mmio + 0x000ec038, 0x2c010000); + write32(mmio + 0x000ec050, 0x2c010000); + write32(mmio + 0x000ec408, 0x2c010000); + write32(mmio + 0x000ec420, 0x2c010000); + write32(mmio + 0x000ec438, 0x2c010000); + write32(mmio + 0x000ec450, 0x2c010000); + vga_gr_write(0x18, 0); + write32(mmio + 0x00042004, 0x02000000); + write32(mmio + 0x000fd034, 0x8421ffe0); + + /* Setup GTT. */ + for (i = 0; i < 0x2000; i++) + { + outl((i << 2) | 1, piobase); + outl(physbase + (i << 12) + 1, piobase + 4); + } + + vga_misc_write(0x67); + + const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, + 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, + 0xff + }; + vga_cr_write(0x11, 0); + + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + + power_port(mmio); + + intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data, 128); + decode_edid(edid_data, + sizeof(edid_data), &edid); + + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = edid.x_resolution; + vactive = edid.y_resolution; + right_border = edid.hborder; + bottom_border = edid.vborder; + hpolarity = (edid.phsync == '-'); + vpolarity = (edid.pvsync == '-'); + vsync = edid.vspw; + hsync = edid.hspw; + vblank = edid.vbl; + hblank = edid.hbl; + hfront_porch = edid.hso; + vfront_porch = edid.vso; + + target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + : (2 * edid.pixel_clock); +#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + vga_textmode_init(); +#else + vga_sr_write(1, 1); + vga_sr_write(0x2, 0xf); + vga_sr_write(0x3, 0x0); + vga_sr_write(0x4, 0xe); + vga_gr_write(0, 0x0); + vga_gr_write(1, 0x0); + vga_gr_write(2, 0x0); + vga_gr_write(3, 0x0); + vga_gr_write(4, 0x0); + vga_gr_write(5, 0x0); + vga_gr_write(6, 0x5); + vga_gr_write(7, 0xf); + vga_gr_write(0x10, 0x1); + vga_gr_write(0x11, 0); + + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + + write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888); + write32(mmio + DSPADDR(0), 0); + write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(mmio + DSPSURF(0), 0); + for (i = 0; i < 0x100; i++) + write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); +#endif + + /* Find suitable divisors. */ + for (candp1 = 1; candp1 <= 8; candp1++) { + for (candn = 5; candn <= 10; candn++) { + u32 cur_frequency; + u32 m; /* 77 - 131. */ + u32 denom; /* 35 - 560. */ + u32 current_delta; + + denom = candn * candp1 * 7; + /* Doesnt overflow for up to + 5000000 kHz = 5 GHz. */ + m = (target_frequency * denom + 60000) / 120000; + + if (m < 77 || m > 131) + continue; + + cur_frequency = (120000 * m) / denom; + if (target_frequency > cur_frequency) + current_delta = target_frequency - cur_frequency; + else + current_delta = cur_frequency - target_frequency; + + + if (best_delta > current_delta) { + best_delta = current_delta; + pixel_n = candn; + pixel_p1 = candp1; + pixel_m2 = ((m + 3) % 5) + 7; + pixel_m1 = (m - pixel_m2) / 5; + } + } + } + + if (best_delta == 0xffffffff) { + printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return 0; + } + + link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; + data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) + / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4)); + + printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", + hactive, vactive); + printk(BIOS_DEBUG, "Borders %d x %d\n", + right_border, bottom_border); + printk(BIOS_DEBUG, "Blank %d x %d\n", + hblank, vblank); + printk(BIOS_DEBUG, "Sync %d x %d\n", + hsync, vsync); + printk(BIOS_DEBUG, "Front porch %d x %d\n", + hfront_porch, vfront_porch); + printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + ? "Spread spectrum clock\n" : "DREF clock\n")); + printk(BIOS_DEBUG, + info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + printk(BIOS_DEBUG, "Polarities %d, %d\n", + hpolarity, vpolarity); + printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", + data_m1, data_n1); + printk(BIOS_DEBUG, "Link frequency %d kHz\n", + link_frequency); + printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", + link_m1, link_n1); + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", + 120000 * (5 * pixel_m1 + pixel_m2) / pixel_n + / (pixel_p1 * 7)); + + write32(mmio + PCH_LVDS, + (hpolarity << 20) | (vpolarity << 21) + | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_DETECTED); + write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); + write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock + ? 0x1002 : 0x400)); + mdelay(1); + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(mmio + _PCH_FP0(0), + ((pixel_n - 2) << 16) + | ((pixel_m1 - 2) << 8) | pixel_m2); + write32(mmio + PCH_DPLL_SEL, 8); + write32(mmio + _PCH_DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + mdelay(1); + write32(mmio + _PCH_DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + /* Re-lock the registers. */ + write32(mmio + PCH_PP_CONTROL, + (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + + write32(mmio + PCH_LVDS, + (hpolarity << 20) | (vpolarity << 21) + | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_DETECTED); + + write32(mmio + HTOTAL(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); + write32(mmio + HSYNC(0), + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); + + write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), + (vactive + bottom_border + vfront_porch + vsync - 1) + | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1)); + write32(mmio + PF_CTL(0),0); + write32(mmio + PF_WIN_SZ(0), 0); +#else + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +#endif + + mdelay(1); + + write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); + write32(mmio + PIPE_DATA_N1(0), data_n1); + write32(mmio + PIPE_LINK_M1(0), link_m1); + write32(mmio + PIPE_LINK_N1(0), link_n1); + + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); + write32(mmio + PIPECONF(0), PIPECONF_BPP_6); + write32(mmio + 0x000f000c, 0x00022050); + write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE); +#else + write32(mmio + CPU_VGACNTRL, 0x20298e); +#endif + train_link(mmio); + +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); + mdelay(1); +#endif + + write32(mmio + TRANS_HTOTAL(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + TRANS_HBLANK(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); + write32(mmio + TRANS_HSYNC(0), + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); + + write32(mmio + TRANS_VTOTAL(0), + ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); + write32(mmio + TRANS_VBLANK(0), + ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); + write32(mmio + TRANS_VSYNC(0), + (vactive + bottom_border + vfront_porch + vsync - 1) + | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + 0x00060100, 0xb01c4000); + write32(mmio + 0x000f000c, 0x801a2350); + mdelay(1); + write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + | TRANS_STATE_MASK +#endif + ); + + write32(mmio + PCH_LVDS, + LVDS_PORT_ENABLE + | (hpolarity << 20) | (vpolarity << 21) + | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_DETECTED); + + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); + mdelay(1); + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS + | PANEL_POWER_ON | PANEL_POWER_RESET); + + printk (BIOS_DEBUG, "waiting for panel powerup\n"); + while (1) { + u32 reg32; + reg32 = read32(mmio + PCH_PP_STATUS); + if (((reg32 >> 28) & 3) == 0) + break; + } + printk (BIOS_DEBUG, "panel powered up\n"); + + write32(mmio + PCH_PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + + /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); + +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4); + set_vbe_mode_info_valid(&edid, lfb); +#endif + + /* Linux relies on VBT for panel info. */ + optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; + optionrom_pcir_t *pcir; + size_t vbt_size; + size_t fake_oprom_size; + struct device *dev; + + dev = dev_find_slot(0, PCI_DEVFN(2, 0)); + + memset(oh, 0, 8192); + + oh->signature = OPROM_SIGNATURE; + oh->pcir_offset = 0x40; + oh->vbt_offset = 0x80; + + pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); + pcir->signature = 0x52494350; // PCIR + pcir->vendor = dev->vendor; + pcir->device = dev->device; + pcir->length = sizeof(*pcir); + pcir->revision = dev->class; + pcir->classcode[0] = dev->class >> 8; + pcir->classcode[1] = dev->class >> 16; + pcir->classcode[2] = dev->class >> 24; + pcir->indicator = 0x80; + + vbt_size = generate_vbt (info, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); + fake_oprom_size = (0x80 + vbt_size + 511) / 512; + oh->size = fake_oprom_size; + pcir->imagelength = fake_oprom_size; + + return 1; +} + +#endif

1 0

New patch to review for coreboot: fac2054 sandybridge: Show spew raminit messages only with raminit debug
by Vladimir Serbinenko 24 Aug '14

24 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6754 -gerrit commit fac2054aa6b8d3803c7fd82c723240883ece3823 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Aug 24 22:36:35 2014 +0200 sandybridge: Show spew raminit messages only with raminit debug Change-Id: Ifbc59c28c8d8bd844801da9cb869c5dfbda09168 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/sandybridge/raminit_native.c | 120 ++++++++++----------- 1 file changed, 59 insertions(+), 61 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 9b49f11..5c1af44 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -1219,7 +1219,7 @@ static void write_mrreg(ramctr_timing * ctrl, int channel, int slotrank, { wait_428c(channel); - printk(BIOS_SPEW, "MRd: %x <= %x\n", reg, val); + printram("MRd: %x <= %x\n", reg, val); if (ctrl->rank_mirror[channel][slotrank]) { reg = ((reg >> 1) & 1) | ((reg << 1) & 2); @@ -1227,7 +1227,7 @@ static void write_mrreg(ramctr_timing * ctrl, int channel, int slotrank, | ((val & 0xa8) << 1); } - printk(BIOS_SPEW, "MRd: %x <= %x\n", reg, val); + printram("MRd: %x <= %x\n", reg, val); write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f000); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001); @@ -1365,24 +1365,24 @@ static void dram_mrscommands(ramctr_timing * ctrl) for (rank = 0; rank < 4; rank++) { // MR2 - printk(BIOS_SPEW, "MR2 rank %d...", rank); + printram("MR2 rank %d...", rank); dram_mr2(ctrl, rank); - printk(BIOS_SPEW, "done\n"); + printram("done\n"); // MR3 - printk(BIOS_SPEW, "MR3 rank %d...", rank); + printram("MR3 rank %d...", rank); dram_mr3(ctrl, rank); - printk(BIOS_SPEW, "done\n"); + printram("done\n"); // MR1 - printk(BIOS_SPEW, "MR1 rank %d...", rank); + printram("MR1 rank %d...", rank); dram_mr1(ctrl, rank); - printk(BIOS_SPEW, "done\n"); + printram("done\n"); // MR0 - printk(BIOS_SPEW, "MR0 rank %d...", rank); + printram("MR0 rank %d...", rank); dram_mr0(ctrl, rank); - printk(BIOS_SPEW, "done\n"); + printram("done\n"); } write32(DEFAULT_MCHBAR + 0x4e20, 0x7); @@ -1692,7 +1692,7 @@ static void discover_timA_coarse(ramctr_timing * ctrl, int channel, FOR_ALL_LANES { statistics[lane][timA] = !does_lane_work(ctrl, channel, slotrank, lane); - printk(BIOS_SPEW, "Astat: %d, %d, %d, %x, %x\n", + printram("Astat: %d, %d, %d, %x, %x\n", channel, slotrank, lane, timA, statistics[lane][timA]); } @@ -1703,9 +1703,9 @@ static void discover_timA_coarse(ramctr_timing * ctrl, int channel, upperA[lane] = rn.end; if (upperA[lane] < rn.middle) upperA[lane] += 128; - printk(BIOS_SPEW, "Aval: %d, %d, %d, %x\n", channel, slotrank, + printram("Aval: %d, %d, %d, %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timA); - printk(BIOS_SPEW, "Aend: %d, %d, %d, %x\n", channel, slotrank, + printram("Aend: %d, %d, %d, %x\n", channel, slotrank, lane, upperA[lane]); } } @@ -1744,12 +1744,12 @@ static void discover_timA_fine(ramctr_timing * ctrl, int channel, int slotrank, if (statistics[lane][first_all + 25] == 100) break; - printk(BIOS_SPEW, "lane %d: %d, %d\n", lane, last_zero, + printram("lane %d: %d, %d\n", lane, last_zero, first_all); ctrl->timings[channel][slotrank].lanes[lane].timA = (last_zero + first_all) / 2 + upperA[lane]; - printk(BIOS_SPEW, "Aval: %d, %d, %d, %x\n", channel, slotrank, + printram("Aval: %d, %d, %d, %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timA); } } @@ -1777,18 +1777,18 @@ static void discover_402x(ramctr_timing * ctrl, int channel, int slotrank, if (ctrl->timings[channel][slotrank].val_4024 < 2) die("402x discovery failed"); ctrl->timings[channel][slotrank].val_4024 -= 2; - printk(BIOS_SPEW, "4024 -= 2;\n"); + printram("4024 -= 2;\n"); continue; } ctrl->timings[channel][slotrank].val_4028 += 2; - printk(BIOS_SPEW, "4028 += 2;\n"); + printram("4028 += 2;\n"); if (ctrl->timings[channel][slotrank].val_4028 >= 0x10) die("402x discovery failed"); FOR_ALL_LANES if (works[lane]) { ctrl->timings[channel][slotrank].lanes[lane].timA += 128; upperA[lane] += 128; - printk(BIOS_SPEW, "increment %d, %d, %d\n", channel, + printram("increment %d, %d, %d\n", channel, slotrank, lane); } } @@ -1839,8 +1839,8 @@ static void post_timA_change(ramctr_timing * ctrl, int channel, int slotrank, ctrl->timings[channel][slotrank].val_4028 += shift_402x; ctrl->timings[channel][slotrank].val_4024 += shift_402x; - printk(BIOS_SPEW, "4024 += %d;\n", shift_402x); - printk(BIOS_SPEW, "4028 += %d;\n", shift_402x); + printram("4024 += %d;\n", shift_402x); + printram("4028 += %d;\n", shift_402x); } static void read_training(ramctr_timing * ctrl) @@ -1882,7 +1882,7 @@ static void read_training(ramctr_timing * ctrl) if (all_high) { ctrl->timings[channel][slotrank].val_4028--; - printk(BIOS_SPEW, "4028--;\n"); + printram("4028--;\n"); FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane]. timA -= 0x40; @@ -1892,8 +1892,8 @@ static void read_training(ramctr_timing * ctrl) } else if (some_high) { ctrl->timings[channel][slotrank].val_4024++; ctrl->timings[channel][slotrank].val_4028++; - printk(BIOS_SPEW, "4024++;\n"); - printk(BIOS_SPEW, "4028++;\n"); + printram("4024++;\n"); + printram("4028++;\n"); } program_timings(ctrl, channel); @@ -1914,16 +1914,16 @@ static void read_training(ramctr_timing * ctrl) ctrl->timings[channel][slotrank].lanes[lane].timA -= mnmx.timA_min_high * 0x40; } ctrl->timings[channel][slotrank].val_4028 -= mnmx.timA_min_high; - printk(BIOS_SPEW, "4028 -= %d;\n", mnmx.timA_min_high); + printram("4028 -= %d;\n", mnmx.timA_min_high); post_timA_change(ctrl, channel, slotrank, &mnmx); - printk(BIOS_SPEW, "4/8: %d, %d, %x, %x\n", channel, slotrank, + printram("4/8: %d, %d, %x, %x\n", channel, slotrank, ctrl->timings[channel][slotrank].val_4024, ctrl->timings[channel][slotrank].val_4028); FOR_ALL_LANES - printk(BIOS_SPEW, "%d, %d, %d, %x\n", channel, slotrank, + printram("%d, %d, %d, %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timA); @@ -2050,7 +2050,7 @@ static void discover_timC(ramctr_timing * ctrl, int channel, int slotrank) statistics[lane][timC] = read32(DEFAULT_MCHBAR + 0x4340 + 4 * lane + 0x400 * channel); - printk(BIOS_SPEW, "Cstat: %d, %d, %d, %x, %x\n", + printram("Cstat: %d, %d, %d, %x, %x\n", channel, slotrank, lane, timC, statistics[lane][timC]); } @@ -2061,7 +2061,7 @@ static void discover_timC(ramctr_timing * ctrl, int channel, int slotrank) ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; if (rn.all) die("timC discovery failed"); - printk(BIOS_SPEW, "Cval: %d, %d, %d, %x\n", channel, slotrank, + printram("Cval: %d, %d, %d, %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timC); } } @@ -2079,7 +2079,7 @@ static void fill_pattern0(ramctr_timing * ctrl, int channel, u32 a, u32 b) unsigned j; unsigned channel_offset = get_precedening_channels(ctrl, channel) * 0x40; - printk(BIOS_SPEW, "channel_offset=%x\n", channel_offset); + printram("channel_offset=%x\n", channel_offset); for (j = 0; j < 16; j++) write32(0x04000000 + channel_offset + 4 * j, j & 2 ? b : a); sfence(); @@ -2259,7 +2259,7 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank) (DEFAULT_MCHBAR + lane_registers[lane] + channel * 0x100 + 4 + ((timB / 32) & 1) * 4) >> (timB % 32)) & 1); - printk(BIOS_SPEW, "Bstat: %d, %d, %d, %x, %x\n", + printram("Bstat: %d, %d, %d, %x, %x\n", channel, slotrank, lane, timB, statistics[lane][timB]); } @@ -2269,7 +2269,7 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank) ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; if (rn.all) die("timB discovery failed"); - printk(BIOS_SPEW, "Bval: %d, %d, %d, %x\n", channel, slotrank, + printram("Bval: %d, %d, %d, %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timB); } } @@ -2373,7 +2373,7 @@ static void adjust_high_timB(ramctr_timing * ctrl) get_timB_high_adjust(res) * 64; printk(BIOS_DEBUG, "High adjust %d:%016llx\n", lane, res); - printk(BIOS_SPEW, "Bval+: %d, %d, %d, %x\n", channel, + printram("Bval+: %d, %d, %d, %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane]. timB); @@ -2477,9 +2477,9 @@ static void write_training(ramctr_timing * ctrl) udelay(1); - printk(BIOS_SPEW, "CPE\n"); + printram("CPE\n"); precharge(ctrl); - printk(BIOS_SPEW, "CPF\n"); + printram("CPF\n"); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { read32(DEFAULT_MCHBAR + 0x4080 + 0x400 * channel + 4 * lane); @@ -2581,7 +2581,7 @@ static int test_320c(ramctr_timing * ctrl, int channel, int slotrank) ctrl->timings[channel][slotrank] = saved_rt; - printk(BIOS_SPEW, "3lanes: %x\n", lanes_ok); + printram("3lanes: %x\n", lanes_ok); return lanes_ok != ((1 << NUM_LANES) - 1); } @@ -2725,7 +2725,7 @@ static int try_reg_4004_b30(ramctr_timing * ctrl, int r4004b30) FOR_ALL_POPULATED_RANKS { stat[slotrank][c320c + 127] = test_320c(ctrl, channel, slotrank); - printk(BIOS_SPEW, "3stat: %d, %d, %d: %d\n", + printram("3stat: %d, %d, %d: %d\n", channel, slotrank, c320c, stat[slotrank][c320c + 127]); } @@ -2735,7 +2735,7 @@ static int try_reg_4004_b30(ramctr_timing * ctrl, int r4004b30) get_longest_zero_run(stat[slotrank], 255); ctrl->timings[channel][slotrank].val_320c = rn.middle - 127; - printk(BIOS_SPEW, "3val: %d, %d: %d\n", channel, + printram("3val: %d, %d: %d\n", channel, slotrank, ctrl->timings[channel][slotrank].val_320c); if (rn.all || rn.length < MIN_C320C_LEN) { @@ -2782,7 +2782,7 @@ static void discover_edges_real(ramctr_timing * ctrl, int channel, int slotrank, ctrl->timings[channel][slotrank].lanes[lane].falling = edge; } - printk(BIOS_SPEW, "edge %02x\n", edge); + printram("edge %02x\n", edge); program_timings(ctrl, channel); FOR_ALL_LANES { @@ -2837,7 +2837,7 @@ static void discover_edges_real(ramctr_timing * ctrl, int channel, int slotrank, edges[lane] = rn.middle; if (rn.all) die("edge discovery failed"); - printk(BIOS_SPEW, "eval %d, %d, %d, %02x\n", channel, slotrank, + printram("eval %d, %d, %d, %02x\n", channel, slotrank, lane, edges[lane]); } } @@ -3038,8 +3038,8 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel, for (pat = 0; pat < NUM_PATTERNS; pat++) { fill_pattern5(ctrl, channel, pat); write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f); - printk(BIOS_SPEW, "patterned\n"); - printk(BIOS_SPEW, "[%x] = 0x%08x\n(%d, %d)\n", + printram("patterned\n"); + printram("[%x] = 0x%08x\n(%d, %d)\n", 0x3000 + 0x100 * channel, reg3000b24[i] << 24, channel, slotrank); for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { @@ -3115,11 +3115,10 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel, ! !(raw_statistics[edge] & (1 << lane)); rn = get_longest_zero_run(statistics, MAX_EDGE_TIMING + 1); - printk(BIOS_SPEW, - "edges: %d, %d, %d: 0x%x-0x%x-0x%x, 0x%x-0x%x\n", - channel, slotrank, i, rn.start, rn.middle, - rn.end, rn.start + ctrl->edge_offset[i], - rn.end - ctrl->edge_offset[i]); + printram("edges: %d, %d, %d: 0x%x-0x%x-0x%x, 0x%x-0x%x\n", + channel, slotrank, i, rn.start, rn.middle, + rn.end, rn.start + ctrl->edge_offset[i], + rn.end - ctrl->edge_offset[i]); lower[lane] = max(rn.start + ctrl->edge_offset[i], lower[lane]); upper[lane] = @@ -3131,7 +3130,7 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel, } write32(DEFAULT_MCHBAR + 0x3000, 0); - printk(BIOS_SPEW, "CPA\n"); + printram("CPA\n"); } static void discover_edges_write(ramctr_timing * ctrl) @@ -3270,12 +3269,11 @@ static void discover_timC_write(ramctr_timing * ctrl) MAX_TIMC + 1); if (rn.all) die("timC write discovery failed"); - printk(BIOS_SPEW, - "timC: %d, %d, %d: 0x%x-0x%x-0x%x, 0x%x-0x%x\n", - channel, slotrank, i, rn.start, - rn.middle, rn.end, - rn.start + ctrl->timC_offset[i], - rn.end - ctrl->timC_offset[i]); + printram("timC: %d, %d, %d: 0x%x-0x%x-0x%x, 0x%x-0x%x\n", + channel, slotrank, i, rn.start, + rn.middle, rn.end, + rn.start + ctrl->timC_offset[i], + rn.end - ctrl->timC_offset[i]); lower[channel][slotrank][lane] = max(rn.start + ctrl->timC_offset[i], lower[channel][slotrank][lane]); @@ -3297,10 +3295,10 @@ static void discover_timC_write(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4ea8, 0); - printk(BIOS_SPEW, "CPB\n"); + printram("CPB\n"); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - printk(BIOS_SPEW, "timC [%d, %d, %d] = 0x%x\n", channel, + printram("timC [%d, %d, %d] = 0x%x\n", channel, slotrank, lane, (lower[channel][slotrank][lane] + upper[channel][slotrank][lane]) / 2); @@ -3642,12 +3640,12 @@ static void restore_timings(ramctr_timing * ctrl) 0x400 * channel) | 0x200000); } - printk(BIOS_SPEW, "CPE\n"); + printram("CPE\n"); write32(DEFAULT_MCHBAR + 0x3400, 0); write32(DEFAULT_MCHBAR + 0x4eb0, 0); - printk(BIOS_SPEW, "CP5b\n"); + printram("CP5b\n"); FOR_ALL_POPULATED_CHANNELS { program_timings(ctrl, channel); @@ -3687,7 +3685,7 @@ static void restore_timings(ramctr_timing * ctrl) /* mrs commands. */ dram_mrscommands(ctrl); - printk(BIOS_SPEW, "CP5c\n"); + printram("CP5c\n"); write32(DEFAULT_MCHBAR + 0x3000, 0); @@ -3834,15 +3832,15 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, read_training(&ctrl); write_training(&ctrl); - printk(BIOS_SPEW, "CP5a\n"); + printram("CP5a\n"); discover_edges(&ctrl); - printk(BIOS_SPEW, "CP5b\n"); + printram("CP5b\n"); command_training(&ctrl); - printk(BIOS_SPEW, "CP5c\n"); + printram("CP5c\n"); discover_edges_write(&ctrl);

1 0

New patch to review for coreboot: 1ec62f2 sandybridge: Add native sandybridge
by Vladimir Serbinenko 24 Aug '14

24 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6753 -gerrit commit 1ec62f2c8b8944648d46061bbc17b0cb58e89f24 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Aug 24 22:35:29 2014 +0200 sandybridge: Add native sandybridge Change-Id: I1b51310b4387e588c4828563620b0e2770598503 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/Makefile.inc | 1 + src/cpu/x86/smm/smmhandler_tseg.S | 2 +- src/cpu/x86/smm/smmrelocate.S | 4 ++-- src/northbridge/intel/Makefile.inc | 1 + src/northbridge/intel/sandybridge/Kconfig | 16 +++++++++++++--- src/northbridge/intel/sandybridge/Makefile.inc | 3 +++ src/southbridge/intel/bd82x6x/Makefile.inc | 1 + src/southbridge/intel/bd82x6x/usb_ehci.c | 4 ++-- 8 files changed, 24 insertions(+), 8 deletions(-) diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index a152e3f..b6e7268 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -18,6 +18,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA988B) += socket_rPGA988B subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S index 380935a..c9d78b9 100644 --- a/src/cpu/x86/smm/smmhandler_tseg.S +++ b/src/cpu/x86/smm/smmhandler_tseg.S @@ -57,7 +57,7 @@ #define SMI_UNLOCKED 1 #define __PRE_RAM__ -#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE +#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE #include <northbridge/intel/sandybridge/sandybridge.h> #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) #elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index bc90fab..6648215 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -48,7 +48,7 @@ #if CONFIG_SMM_TSEG -#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE +#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE #include <northbridge/intel/sandybridge/sandybridge.h> #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) #elif CONFIG_NORTHBRIDGE_INTEL_NEHALEM @@ -195,7 +195,7 @@ smm_relocate: xorl %edx, %edx wrmsr -#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE +#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE /* * IED base is top 4M of TSEG */ diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc index 4fb91e8..ffda444 100644 --- a/src/northbridge/intel/Makefile.inc +++ b/src/northbridge/intel/Makefile.inc @@ -14,6 +14,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += nehalem subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += sandybridge +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += sandybridge subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += sandybridge subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += sandybridge subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index cccc09e..1080724 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -25,6 +25,14 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE select DYNAMIC_CBMEM select CPU_INTEL_MODEL_206AX +config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE + bool + select CACHE_MRC_BIN + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT + select CPU_INTEL_MODEL_206AX + select HAVE_DEBUG_RAM_SETUP + config NORTHBRIDGE_INTEL_IVYBRIDGE bool select CACHE_MRC_BIN @@ -41,7 +49,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE select CPU_INTEL_MODEL_306AX select HAVE_DEBUG_RAM_SETUP -if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE +if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE config VGA_BIOS_ID string @@ -62,8 +70,10 @@ config MRC_CACHE_SIZE config DCACHE_RAM_BASE hex - default 0xff7e0000 if !NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE + default 0xff7e0000 if NORTHBRIDGE_INTEL_IVYBRIDGE + default 0xff7e0000 if NORTHBRIDGE_INTEL_SANDYBRIDGE default 0xfefe0000 if NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE + default 0xfefe0000 if NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE config DCACHE_RAM_SIZE hex @@ -79,7 +89,7 @@ config DCACHE_RAM_MRC_VAR_SIZE config HAVE_MRC bool "Add a System Agent binary" - depends on !NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE + depends on !NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE && !NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE help Select this option to add a System Agent binary to the resulting coreboot image. diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 532a970..83e9b9c 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -30,6 +30,8 @@ romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += raminit.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += raminit.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += raminit_native.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += ../../../device/dram/ddr3.c +romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += raminit_native.c +romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += ../../../device/dram/ddr3.c romstage-y += mrccache.c romstage-y += early_init.c romstage-y += report_platform.c @@ -55,6 +57,7 @@ mrc.cache-file := $(obj)/mrc.cache mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) := 0xfffd0000 mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) := 0xfffd0000 mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) := 0xfffe0000 +mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) := 0xfffe0000 mrc.cache-position := $(mrc-cache-position-y) mrc.cache-type := 0xac endif diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index fa21277..def9cd2 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -52,6 +52,7 @@ romstage-y += early_spi.c early_pch.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_me.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_me.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c +romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) IFD_BIN_PATH := $(objgenerated)/ifdfake.bin diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 97f20bd..9850fee 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -39,7 +39,7 @@ static void usb_ehci_init(struct device *dev) printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); /* For others, done in MRC. */ -#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) +#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) || IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) pci_write_config32(dev, 0x84, 0x930c8811); pci_write_config32(dev, 0x88, 0x24000d30); pci_write_config32(dev, 0xf4, 0x80408588); @@ -54,7 +54,7 @@ static void usb_ehci_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32); /* For others, done in MRC. */ -#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) +#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) || IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) struct resource *res; u8 access_cntl;

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New patch to review for coreboot: 69e3eb8 lint-stable: Skip Kconfig files in board-status.
by Vladimir Serbinenko 24 Aug '14

24 Aug '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6752 -gerrit commit 69e3eb877fbb40cb4cf42be2e3bfc27c3c49eb6a Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Aug 24 22:32:27 2014 +0200 lint-stable: Skip Kconfig files in board-status. Change-Id: I7a3a24ccdca273b9715ea73e9293b737218af443 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/lint/lint-stable-005-board-status | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/lint/lint-stable-005-board-status b/util/lint/lint-stable-005-board-status index ce222e9..1e53811 100755 --- a/util/lint/lint-stable-005-board-status +++ b/util/lint/lint-stable-005-board-status @@ -20,7 +20,7 @@ # DESCR: Check that every board has a meaningful board_info.txt LC_ALL=C export LC_ALL -for mobodir in $(git diff --name-status |grep -v "^D" |cut -c3- | sed -n 's,^$src/mainboard/[^/]*/[^/]*$.*$,\1,p'|sort|uniq); do +for mobodir in $(git diff --name-status |grep -v "^D" |cut -c3- | sed -n 's,^$src/mainboard/[^/]*/[^/]*$.*$,\1,p'|grep -v Kconfig|sort|uniq); do board_info="$mobodir/board_info.txt" if ! [ -f "$board_info" ]; then echo "No $board_info found"

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Patch merged into coreboot/master: 9f2dae4 lenovo/t530: Use GPIO defines specified in bd82x6x/pch.h header
by gerrit＠coreboot.org 24 Aug '14

24 Aug '14

the following patch was just integrated into master: commit 9f2dae4ec0a420ef76a3672dbda29d104b9da4ff Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Aug 1 20:29:40 2014 +1000 lenovo/t530: Use GPIO defines specified in bd82x6x/pch.h header Use defines of offsets rather than hard coded values. Change-Id: Id2471cd22aa402d74163473e48f86af9789cdaa7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6435 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/6435 for details. -gerrit

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Patch merged into coreboot/master: a51064e lenovo/t530/romstage.c: Trivial - move include to top
by gerrit＠coreboot.org 24 Aug '14

24 Aug '14

the following patch was just integrated into master: commit a51064eb1a7eb04accbc371f37fd80ea851ab7e4 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Aug 23 14:25:30 2014 +1000 lenovo/t530/romstage.c: Trivial - move include to top Change-Id: I6b80ad0da39e93072e28b48c40e1c71602133e7b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/6750 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/6750 for details. -gerrit

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Patch set updated for coreboot: 022c9d7 [NOTFORMERGE] device/Kconfig: Select native graphics init by default
by Paul Menzel 24 Aug '14

24 Aug '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5957 -gerrit commit 022c9d78550a7e0d85552ebdf89e299b159d6b8a Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Jun 7 21:50:21 2014 +0200 [NOTFORMERGE] device/Kconfig: Select native graphics init by default Just for build testing the native graphics patches. Change-Id: I47ed328ce8ce3516ad3997978a01d2359d9b1ca8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Signed-off-by: Francis Rowe <info(a)gluglug.org.uk> --- src/device/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 58dcc1b..3d47602 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -32,7 +32,7 @@ config MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG config MAINBOARD_DO_NATIVE_VGA_INIT bool "Use native graphics initialization" depends on MAINBOARD_HAS_NATIVE_VGA_INIT - default n + default y help Some mainboards, such as the Google Link, allow initializing the display without the need of a binary only VGA OPROM. Enabling this option may be

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Patch merged into coreboot/master: 35d5ea9 lenovo/t520: replace dumped GPIO values with gpio.h
by gerrit＠coreboot.org 24 Aug '14

24 Aug '14

the following patch was just integrated into master: commit 35d5ea97f6b1360ed36acdf0a0a5e608e3682a5c Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Fri Aug 22 16:47:07 2014 +0200 lenovo/t520: replace dumped GPIO values with gpio.h GPIO pin wireing information from schematic Change-Id: I2d8dca151b6fbc15e0184ea07596039570843cda Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Reviewed-on: http://review.coreboot.org/6740 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6740 for details. -gerrit

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coreboot-gerrit August 2014