the following patch was just integrated into master:
commit 6e3712f9e11582f98630d404ce48a538716d8fee
Author: Daniele Forsi <dforsi(a)gmail.com>
Date: Sat Jul 26 11:37:41 2014 +0200
device/oprom/yabel/vbe.c: Fix memory leak
Do not allocate memory if the bootsplash was not found.
Found by Cppcheck 1.65. Fixes:
[src/device/oprom/yabel/vbe.c:734]: (error) Memory leak: decdata
Change-Id: Ie2283165c9d7650dce9baf9e892dd055d44dcce5
Signed-off-by: Daniele Forsi <dforsi(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6377
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/6377 for details.
-gerrit
the following patch was just integrated into master:
commit f9ce88e942a70a1aaa1f0951f8fab436a2ea82f5
Author: Daniele Forsi <dforsi(a)gmail.com>
Date: Sat Jul 26 11:32:16 2014 +0200
device/oprom/realmode/x86.c: Fix memory leak
Do not allocate memory if the bootsplash was not found.
Found by Cppcheck 1.65. Fixes:
[src/device/oprom/realmode/x86.c:280]: (error) Memory leak: decdata
Change-Id: I8f8160d3d349c0c2b2a3ed84461729e9210153d8
Signed-off-by: Daniele Forsi <dforsi(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6376
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/6376 for details.
-gerrit
the following patch was just integrated into master:
commit c2519e5a06ba5f70bfcb1e2e70ade440c9552f18
Author: Daniele Forsi <dforsi(a)gmail.com>
Date: Sat Jul 26 11:17:03 2014 +0200
dmp/vortex86ex/southbridge.c: Do not access arrays out of bound
Found by Cppcheck 1.65. Fixes:
[src/southbridge/dmp/vortex86ex/southbridge.c:498]: (error) Array 'rtc[7]' accessed at index 7, which is out of bounds.
[src/southbridge/dmp/vortex86ex/southbridge.c:498]: (error) Array 'bin_rtc[7]' accessed at index 7, which is out of bounds.
Change-Id: I8939fe1b326202bbe2784639b0e591f8ee470eeb
Signed-off-by: Daniele Forsi <dforsi(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6375
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Reviewed-by: Andrew Wu <arw(a)dmp.com.tw>
See http://review.coreboot.org/6375 for details.
-gerrit
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4503
-gerrit
commit 33bcea48fbc0477cd764c9be279f180a435f79fd
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sun Dec 8 07:56:34 2013 +0200
cpu/amd (non-AGESA): Replace UPDATE_CPU_MICROCODE with SUPPORT_UCODE_IN_CBFS
Change-Id: I71e5b19bf451cef857cad2e2bb4bd8cc19d0ddd0
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/cpu/amd/microcode/Makefile.inc | 4 ++--
src/cpu/amd/model_10xxx/Kconfig | 33 +--------------------------------
src/cpu/amd/model_10xxx/Makefile.inc | 2 +-
src/cpu/amd/model_fxx/Kconfig | 1 +
src/cpu/amd/model_fxx/Makefile.inc | 2 +-
src/include/cpu/amd/microcode.h | 2 +-
6 files changed, 7 insertions(+), 37 deletions(-)
diff --git a/src/cpu/amd/microcode/Makefile.inc b/src/cpu/amd/microcode/Makefile.inc
index 48f1d0d..6da939e 100644
--- a/src/cpu/amd/microcode/Makefile.inc
+++ b/src/cpu/amd/microcode/Makefile.inc
@@ -1,2 +1,2 @@
-ramstage-y += microcode.c
-romstage-$(CONFIG_UPDATE_CPU_MICROCODE) += microcode.c
+ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c
+romstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c
diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig
index 5e45b0d..aef3d09 100644
--- a/src/cpu/amd/model_10xxx/Kconfig
+++ b/src/cpu/amd/model_10xxx/Kconfig
@@ -8,6 +8,7 @@ config CPU_AMD_MODEL_10XXX
select MMCONF_SUPPORT_DEFAULT
select TSC_SYNC_LFENCE
select UDELAY_LAPIC
+ select SUPPORT_CPU_UCODE_IN_CBFS
if CPU_AMD_MODEL_10XXX
@@ -69,36 +70,4 @@ config UDELAY_LAPIC_FIXED_FSB
int
default 200
-config UPDATE_CPU_MICROCODE
- bool
- default y
-
-config UPDATE_CPU_MICROCODE
- bool "Update CPU microcode"
- default y
- depends on EXPERT && CPU_AMD_MODEL_10XXX
- help
- Select this to apply patches to the CPU microcode provided by
- AMD without source, and distributed with coreboot, to address
- issues in the CPU post production.
-
- Microcode updates distributed with coreboot are not necessarily
- the latest version available from AMD. Updates are only applied
- if they are newer than the microcode already in your CPU.
-
- Unselect this to let Fam10h CPUs run with microcode as shipped
- from factory. No binary microcode patches will be included in the
- coreboot image in that case, which can help with creating an image
- for which complete source code is available, which in turn might
- simplify license compliance.
-
- Microcode updates intend to solve issues that have been discovered
- after CPU production. The common case is that systems work as
- intended with updated microcode, but we have also seen cases where
- issues were solved by not applying the microcode updates.
-
- Note that some operating system include these same microcode
- patches, so you may need to also disable microcode updates in
- your operating system in order for this option to matter.
-
endif # CPU_AMD_MODEL_10XXX
diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc
index f7c0727..a75ea4f 100644
--- a/src/cpu/amd/model_10xxx/Makefile.inc
+++ b/src/cpu/amd/model_10xxx/Makefile.inc
@@ -2,6 +2,6 @@ romstage-y += ../../x86/mtrr/earlymtrr.c
ramstage-y += model_10xxx_init.c
ramstage-y += processor_name.c
-romstage-$(CONFIG_UPDATE_CPU_MICROCODE) += update_microcode.c
+romstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += update_microcode.c
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig
index f577b55..4980a8f 100644
--- a/src/cpu/amd/model_fxx/Kconfig
+++ b/src/cpu/amd/model_fxx/Kconfig
@@ -8,6 +8,7 @@ config CPU_AMD_MODEL_FXX
select SSE2
select TSC_SYNC_LFENCE
select UDELAY_LAPIC
+ select SUPPORT_CPU_UCODE_IN_CBFS
if CPU_AMD_MODEL_FXX
config UDELAY_IO
diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc
index 8730f41..137b909 100644
--- a/src/cpu/amd/model_fxx/Makefile.inc
+++ b/src/cpu/amd/model_fxx/Makefile.inc
@@ -2,7 +2,7 @@ romstage-y += ../../x86/mtrr/earlymtrr.c
# no conditionals here. If you include this file from a socket, then you get all the binaries.
ramstage-y += model_fxx_init.c
-ramstage-y += model_fxx_update_microcode.c
+ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += model_fxx_update_microcode.c
ramstage-y += processor_name.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += powernow_acpi.c
diff --git a/src/include/cpu/amd/microcode.h b/src/include/cpu/amd/microcode.h
index 9876a24..cec5e58 100644
--- a/src/include/cpu/amd/microcode.h
+++ b/src/include/cpu/amd/microcode.h
@@ -1,7 +1,7 @@
#ifndef CPU_AMD_MICROCODE_H
#define CPU_AMD_MICROCODE_H
-#if CONFIG_UPDATE_CPU_MICROCODE || CONFIG_NORTHBRIDGE_AMD_AMDK8
+#if CONFIG_SUPPORT_CPU_UCODE_IN_CBFS
void update_microcode(u32 cpu_deviceid);
void amd_update_microcode_from_cbfs(u32 equivalent_processor_rev_id);
#else
the following patch was just integrated into master:
commit f8e96f07d40152a3b11a70ddbd909e9da8fabf7e
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Jul 22 15:24:15 2014 +0300
AGESA boards: Drop get_bus_conf.c files
The only remaining purpose for get_bus_conf() was to fill in obscure
bus_sb800 (etc.) arrays containing partial PCI bus enumeration. Complete
enumeration is available in devicetree and PCI configuration space so
discard these arrays.
Change-Id: I733115940afba3a50c58aedb9a04ecf5082b1234
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6360
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/6360 for details.
-gerrit