coreboot-gerrit July 2014

coreboot-gerrit@coreboot.org

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861 discussions

Patch merged into coreboot/master: b426107 AGESA f14 f15tn 16kb: Move IOAPIC ID setup out of get_bus_conf()
by gerrit＠coreboot.org 28 Jul '14

28 Jul '14

the following patch was just integrated into master: commit b426107d1db17b606a90be83ddd3bf8a1c0d8751 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jul 22 10:24:20 2014 +0300 AGESA f14 f15tn 16kb: Move IOAPIC ID setup out of get_bus_conf() Change-Id: I7fd14c17242cd3deb7a784fc918ad6fe1191bd13 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6359 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6359 for details. -gerrit

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Patch merged into coreboot/master: cdfb462 AGESA boards: Use devicetree for PCI bus enumeration
by gerrit＠coreboot.org 28 Jul '14

28 Jul '14

the following patch was just integrated into master: commit cdfb46240b4bba8a112c85a5f5d26447e90378b3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jul 22 15:24:15 2014 +0300 AGESA boards: Use devicetree for PCI bus enumeration Previously MP table contained PCI_INT entries for PCI bus behind bridge 0:14.4 even if said PCI bridge function was disabled. Remove these as invalid, indeterminate bus number could cause conflicts. PCI_INT entries with bus_sb800[2], bus_hudson[2] and bus_yangtze[2] were invalid as there is no PCI bridge hardware on device 0:14.0. Remove these as invalid, indeterminate bus number could cause conflicts. Change-Id: Ie6a3807f64c8651cf9f732612e1aa7f376a3134f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6358 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6358 for details. -gerrit

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Patch merged into coreboot/master: e5523b8 AGESA: Have IRQ routing in mptables
by gerrit＠coreboot.org 28 Jul '14

28 Jul '14

the following patch was just integrated into master: commit e5523b808b2a29a3049a21a3b0339e80fbeef42a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 25 17:33:12 2014 +0300 AGESA: Have IRQ routing in mptables MP table should be complete with IRQ routing information even when we have ACPI tables. Change-Id: Ieeaed442aea6217f4477b7ac7e06a1926eec8996 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6361 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6361 for details. -gerrit

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Patch merged into coreboot/master: 32d9e92 AGESA fam16kb: Move NB config fam16kb out of get_bus_conf()
by gerrit＠coreboot.org 28 Jul '14

28 Jul '14

the following patch was just integrated into master: commit 32d9e9296e6e7d542d18868110a419e09d8176b0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jul 22 19:27:52 2014 +0300 AGESA fam16kb: Move NB config fam16kb out of get_bus_conf() Change-Id: Iedb5e1c72afe70f63f39c2dbce4896863d1d275f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6357 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6357 for details. -gerrit

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Patch merged into coreboot/master: 526c2fb AGESA: Drop some excessive agesawrapper.h includes
by gerrit＠coreboot.org 28 Jul '14

28 Jul '14

the following patch was just integrated into master: commit 526c2fb278c6c4eccebaaaea9e1f7a00358d10e9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jul 10 22:16:58 2014 +0300 AGESA: Drop some excessive agesawrapper.h includes Change-Id: I3807912b1dc68fae8248a66e37bbe642fb92d3ae Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6262 Tested-by: build bot (Jenkins) See http://review.coreboot.org/6262 for details. -gerrit

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Patch merged into coreboot/master: 78d0cab IOAPIC: Fix missing stdint include
by gerrit＠coreboot.org 28 Jul '14

28 Jul '14

the following patch was just integrated into master: commit 78d0cab36d835c988ef6a75e0a47fb6349ca1300 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 11 09:44:54 2014 +0300 IOAPIC: Fix missing stdint include Change-Id: Ib26f48d3ac66788246834cdc25d97910cd79fe98 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6264 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6264 for details. -gerrit

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Patch set updated for coreboot: 765e943 mainboard/jetway/nf81-t56n-lf: Provide ACPI thermal zone
by Edward O'Callaghan 28 Jul '14

28 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5889 -gerrit commit 765e94315d18272b5b3eb476a0574cad9394584a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 31 16:19:40 2014 +1000 mainboard/jetway/nf81-t56n-lf: Provide ACPI thermal zone NOTFORMERGE - yet - Has a SystemIO conflict with 0x...220 - 0x...227 from somewhere else??? Change-Id: Ibb0295154fca23a3819953db0119692b26096e34 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl | 26 +++- .../jetway/nf81-t56n-lf/acpi/mainboard.asl | 1 + src/mainboard/jetway/nf81-t56n-lf/acpi/thermal.asl | 146 ++++++++++++++++++++- 3 files changed, 167 insertions(+), 6 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl index bb47ded..a30698a 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,7 +18,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -Scope(\_GPE) { /* Start Scope GPE */ +Scope(\_GPE) +{ + OperationRegion (IP, SystemIO, 0x0225, 0x02) + Field (IP, ByteAcc, NoLock, Preserve) + { + INDX, 8, + DAT0, 8 + } /* General event 3 */ Method(_L03) { @@ -31,9 +39,21 @@ Scope(\_GPE) { /* Start Scope GPE */ } /* Temp warning (TWarn) event */ - Method(_L09) { + Method(_L09, 0, NotSerialized) + { /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ + Store (GBYT (0x66), Local0) + If (LNotEqual (And (Local0, 0x02), Zero)) + { + Notify (\_TZ.THRM, 0x80) + } + } + + Method (GBYT, 1, NotSerialized) + { + Store (Arg0, INDX) + Store (DAT0, Local0) + Return (Local0) } /* USB controller PME# */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl index 1f532cf..59027b7 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl @@ -33,6 +33,7 @@ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed * Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ Name(OSV, Ones) /* Assume nothing */ Name(PMOD, One) /* Assume APIC */ +Name (TPCH, Zero) /* Thermal zone channel */ Scope(\_SB) { Method(OSFL, 0){ diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/thermal.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/thermal.asl index 2f50475..f061d0c 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/thermal.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/thermal.asl @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -15,7 +17,145 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Thermal Zones have been #if 0 for a long time. - * Removing it for now because it doesn't seem to - * do anything when enabled anyway. +/* Thermal Zones. */ + +/* + * Thermal Events + * -------------- + * + * When OSPM receives a temperature change notification, it evaluates the + * thermal zone's temperature interfaces to retrieve current temperature + * values. OSPM compares the current temperature values against the temperature + * thresholds. If any temperature is >= a corresponding "active trip point" + * (_ACx) then OSPM will preform "active cooling". If any temperature is >= a + * corresponding "passive trip point" (_PSV) then OSPM will preform "passive + * cooling". If _HOT >= _TMP then OSPM transitions into S4 sleep and if _HOT >= + * _CRT then OSPM must shutdown the system! + * + * +--+ + * |90|<----- _CRT: Critical shutdown threshold + * | | + * |75|<----- _ACT0: Fan high speed threshold + * |65|<----- _ACT1: Fan low speed threshold + * | | + * |50|<----- _PSV: Passive cooling threshold + * +--+ */ + + +Scope (\_TZ) +{ + OperationRegion (IP, SystemIO, 0x0225, 0x02) + Field (IP, ByteAcc, NoLock, Preserve) + { + INDX, 8, + DAT0, 8 + } + + // Handler for throttle requests on this platform + // 0 = Stop throttling + // 1 = Start throttling + Method (THRT, 1, Serialized) + { + If (LEqual (Arg0, 0)) { + /* Disable Power Limit */ +// \_SB.PCI0.MCHC.CTLD () + } Else { + /* Enable Power Limit */ +// \_SB.PCI0.MCHC.CTLE (\F0PW) + } + } + + ThermalZone (THRM) + { + /* TODO: Change to Super I/O event driven OSPM later.. */ +/* Done with an SCI. AML handler must execute a Notifiy(thermal_zone, 0x80) to inform OSPM a meaningful temp change occured */ +/* Do this^^^ in superio.asl */ + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + /* + * ACPI expects all temperatures to be represented in tenths of degrees + */ + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) +// Return (CTOK (STMP ())) + } + +/* + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } +*/ + + + // Returns the thermal zone's current operating temperature + Method (_TMP, 0, Serialized) + { + If (LEqual (TPCH, One)) + { + While (LGreater (GBYT (0x7A), 0x7E)) + { + Sleep (0xFA) + Store (One, Local1) + Multiply (0x0A, Local1, Local1) + Add (Local1, 0x0AAC, Local1) + Return (Local1) + } + } + + Return (CTOK (CTMP ())) + } + + Method (STMP, 0, NotSerialized) + { + Store (GBYT (0x82), Local0) + Return (Local0) + } + + Method (CTMP, 0, NotSerialized) + { + Store (GBYT (0x7A), Local0) + If (LGreaterEqual (Local0, 0x65)) + { + Store (0x30, Local0) + } + + Return (Local0) + } + + Method (GBYT, 1, NotSerialized) + { + Store (Arg0, INDX) + Store (DAT0, Local0) + Return (Local0) + } + } +}

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Patch set updated for coreboot: bf4ece6 superio/fintek/f71869ad: Provide ACPI ASL HWMON implementation
by Edward O'Callaghan 28 Jul '14

28 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6388 -gerrit commit bf4ece65993301fcaa401284df984aedbc109605 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jul 28 17:29:35 2014 +1000 superio/fintek/f71869ad: Provide ACPI ASL HWMON implementation This provides the ACPI component to the Fintek F71869AD Hardware Monitor. This lays the foundations for a proper thermal zone implementation for the Jetway NF81-T56N-LF board that uses this Super I/O. Change-Id: I7d1ce0b738cba94b8a5985cf0c04e29b568f5fb0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl | 4 +- src/superio/fintek/f71869ad/acpi/superio.asl | 185 +++++++++++++++++++++ 2 files changed, 188 insertions(+), 1 deletion(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl index 6dcb877..0a4854a 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl @@ -19,4 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "../../../../drivers/pc80/ps2_controller.asl" +#define SUPERIO_INDEX 0x2E + +#include <superio/fintek/f71869ad/acpi/superio.asl> diff --git a/src/superio/fintek/f71869ad/acpi/superio.asl b/src/superio/fintek/f71869ad/acpi/superio.asl new file mode 100644 index 0000000..4fbaa4c --- /dev/null +++ b/src/superio/fintek/f71869ad/acpi/superio.asl @@ -0,0 +1,185 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ACPI_FINTEK_ASL +#define SUPERIO_ACPI_FINTEK_ASL +/* + * include this file into a mainboard's DSDT _SB device tree and it will expose + * the F71869AD SuperIO and its functionality. + */ + +/* Define these in mainboard/xx/acpi/superio.asl */ +// #define SUPERIO_INDEX 0x2E or 0x4E + +Device(SIO) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Fintek F71869AD SuperIO")) + Name (_UID, "f71869ad") + + /* Mutex for accesses to the configuration ports (prolog and epilog + * commands are used, so synchronization is useful) + */ + Mutex(CRMX, 1) + + /* Announce the used I/O both 0x2E & 0x4E configuration ports to the OS */ + Method (_CRS) + { + Return (ResourceTemplate () { + IO (Decode16, 0x002E, 0x002E, 0x02, 0x01) + IO (Decode16, 0x004E, 0x004E, 0x01, 0x01) + }) + } + + /* Super I/O configuration region structure */ + Name (_ADR, SUPERIO_INDEX) + OperationRegion (CREG, SystemIO, SUPERIO_INDEX, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + ADDR, 8, + DATA, 8 + } + + /* Super I/O LDN configuration region structure */ + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x02), + SCNT, 8, /* Configure Control */ + Offset (0x07), + SLDN, 8, /* Logical Device Number */ + Offset (0x30), + SACT, 8, /* Activate */ + Offset (0x60), + IO0H, 8, /* Base Address 0 MSB */ + IO0L, 8, /* Base Address 0 LSB */ + Offset (0x62), + IO1H, 8, /* Base Address 1 MSB */ + IO1L, 8, /* Base Address 1 LSB */ + Offset (0x70), + IQ00, 8, /* Interrupt Select */ + } + + /* Include Super I/O LDN numbers */ +#include "../f71869ad.h" + Name (HLDN, F71869AD_HWM) /* Hardware Monitor */ + + /* Enter configuration mode (and aquire mutex) + * Method must be run before accesssing the configuration region. + */ + Method (ENTR, 0, NotSerialized) + { + Acquire (CRMX, 0xFFFF) /* aquire mutex */ + Store (0x87, ADDR) /* exit by writing 0x87 key into index port twice */ + Store (0x87, ADDR) + } + + /* Exit configuration mode (and release mutex) + * Method must be run after accessing the configuration region. + */ + Method (EXIT, 0, NotSerialized) + { + Store (0xAA, ADDR) /* exit by writing 0xAA key into index port */ + Release (CRMX) + } + + /* Parse activate register for an LDN */ + Method (ISEN, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (SACT, Local0) + EXIT () + + /* Check if it exists */ + If (LEqual (Local0, 0xFF)) + { + Return (0x00) + } + + /* Check if activated */ + If (LEqual (Local0, One)) + { + Return (0x0F) // DEVICE_PRESENT_ACTIVE (0x0F) + } + Else + { + Return (0x0D) // DEVICE_PRESENT_INACTIVE (0x0D) + } + } + + /* ===================== Keyboard Controller ===================== */ +// include common driver +#include <drivers/pc80/ps2_controller.asl> + + /* ====================== Hardware Monitor ======================= */ + Device (HMON) + { + Name (_HID, EisaId ("PNP0C02")) + Name (_STR, Unicode("Fintek F71869AD Hardware Monitor")) + Name (_UID, "f71869ad-hwmon") + Name (_ADR, 0x0225) + + OperationRegion (IP, SystemIO, 0x0225, 0x02) + Field (IP, ByteAcc, NoLock, Preserve) + { + HIDX, 8, // Hardware Monitor Address Index Register + HDAT, 8, // Hardware Monitor Address Data Register + } + + // Registers for thermal zone implementations + IndexField (HIDX, HDAT, ByteAcc, NoLock, Preserve) + { + CNF1, 8, // Configuration Register index 01 - p. 71 datasheet + CNF2, 8, // Configuration Register index 02 + CNF3, 8, // Configuration Register index 03 + Offset (0x60), + PMEE, 8, // PME# Enable Register - p. 79 datasheet + TINS, 8, // Tempature Interrupt Status Register (idx 0x61) + TRTS, 8, // Tempature Real-Time Status Register + TBER, 8, // Tempature BEEP Enable Register + TOV1, 8, // T1 OVT and High Limit Tempature Select Register + TOVA, 8, // OVT and Alert Output Enable Register 1 + Offset (0x6B), + TSTR, 8, // Tempature Sensor Type Register (idx 0x6B) + Offset (0x72), + TIN1, 8, // TMPIN1 Reading + TIN2, 8, // TMPIN2 Reading + TIN3, 8, // TMPIN3 Reading + } + + Method (_STA, 0, NotSerialized) { + Return (ISEN (HLDN)) + } + + // _CRS: Current Resource Setting + Name (_CRS, ResourceTemplate () + { + // v min v max v align v length + IO (Decode16, 0x0225, 0x0225, 0x00, 0x01) + }) + + // _PRS: Possible Resource Settings - Same as _CRS + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x0225, 0x0225, 0x00, 0x01) + + }) + } +} + +#endif /* SUPERIO_ACPI_FINTEK_ASL */

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New patch to review for coreboot: b67feb6 superio/fintek/f71869ad: Provide ACPI ASL HWMON implementation
by Edward O'Callaghan 28 Jul '14

28 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6388 -gerrit commit b67feb63fd791c2aab92d6eed7b59011305941f4 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jul 28 17:29:35 2014 +1000 superio/fintek/f71869ad: Provide ACPI ASL HWMON implementation This provides the ACPI component to the Fintek F71869AD Hardware Monitor. This lays the foundations for a proper thermal zone implementation for the Jetway NF81-T56N-LF board that uses this Super I/O. Change-Id: I7d1ce0b738cba94b8a5985cf0c04e29b568f5fb0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl | 4 +- src/superio/fintek/f71869ad/acpi/superio.asl | 184 +++++++++++++++++++++ 2 files changed, 187 insertions(+), 1 deletion(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl index 6dcb877..88cb5dd 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl @@ -19,4 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "../../../../drivers/pc80/ps2_controller.asl" +SUPERIO_INDEX(0x2E) + +#include <superio/fintek/f71869ad/acpi/superio.asl> diff --git a/src/superio/fintek/f71869ad/acpi/superio.asl b/src/superio/fintek/f71869ad/acpi/superio.asl new file mode 100644 index 0000000..7a9ead0 --- /dev/null +++ b/src/superio/fintek/f71869ad/acpi/superio.asl @@ -0,0 +1,184 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ACPI_FINTEK_ASL +#define SUPERIO_ACPI_FINTEK_ASL +/* + * include this file into a mainboard's DSDT _SB device tree and it will expose + * the F71869AD SuperIO and its functionality. + */ + +/* Define these in mainboard/xx/acpi/superio.asl */ +#define SUPERIO_INDEX(idx) idx + +Device(SIO) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Fintek F71869AD SuperIO")) + Name (_UID, "f71869ad") + + /* Announce the used I/O both 0x2E & 0x4E configuration ports to the OS */ + Method (_CRS) + { + Return (ResourceTemplate () { + IO (Decode16, 0x002E, 0x002E, 0x02, 0x01) + IO (Decode16, 0x004E, 0x004E, 0x01, 0x01) + }) + } + + /* Super I/O configuration region structure */ + Name (_ADR, idx) + OperationRegion (CREG, SystemIO, idx, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + ADDR, 8, + DATA, 8 + } + + /* Super I/O LDN configuration region structure */ + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x02), + SCNT, 8, /* Configure Control */ + Offset (0x07), + SLDN, 8, /* Logical Device Number */ + Offset (0x30), + SACT, 8, /* Activate */ + Offset (0x60), + IO0H, 8, /* Base Address 0 MSB */ + IO0L, 8, /* Base Address 0 LSB */ + Offset (0x62), + IO1H, 8, /* Base Address 1 MSB */ + IO1L, 8, /* Base Address 1 LSB */ + Offset (0x70), + IQ00, 8, /* Interrupt Select */ + } + + /* Include Super I/O LDN numbers */ +#include "../f71869ad.h" + Name (HMON, F71869AD_HWM) /* Hardware Monitor */ + + /* Enter configuration mode (and aquire mutex) + * Method must be run before accesssing the configuration region. + * Parameter is the LDN which should be accessed. Values >= 0xFF mean + * no LDN switch should be done. + */ + Method (ENTR, 1) + { + Acquire (CRMX, 0xFFFF) /* aquire mutex */ + Store (0x87, ADDR) /* exit by writing 0x87 key into index port twice */ + Store (0x87, ADDR) + If (LLess(Arg0, 0xFF)) { + Store(Arg0, LDN) + } + } + + /* Exit configuration mode (and release mutex) + * Method must be run after accessing the configuration region. + */ + Method (EXIT, 0, NotSerialized) + { + Store (0xAA, ADDR) /* exit by writing 0xAA key into index port */ + Release (CRMX) + } + + /* Parse activate register for an LDN */ + Method (ISEN, 1, NotSerialized) + { + ENTR () + Store (Arg0, SLDN) + Store (SACT, Local0) + EXIT () + + /* Check if it exists */ + If (LEqual (Local0, 0xFF)) + { + Return (0x00) + } + + /* Check if activated */ + If (LEqual (Local0, One)) + { + Return (0x0F) // DEVICE_PRESENT_ACTIVE (0x0F) + } + Else + { + Return (0x0D) // DEVICE_PRESENT_INACTIVE (0x0D) + } + } + + /* ===================== Keyboard Controller ===================== */ +// include common driver +#include <drivers/pc80/ps2_controller.asl> + + /* ====================== Hardware Monitor ======================= */ + Device (HMON) + { + Name (_HID, EisaId ("PNP0C02")) + Name (_STR, Unicode("Fintek F71869AD Hardware Monitor")) + Name (_UID, "f71869ad-hwmon") + Name (_ADR, 0x0225) + + OperationRegion (IP, SystemIO, 0x0225, 0x02) + Field (IP, ByteAcc, NoLock, Preserve) + { + HIDX, 8, // Hardware Monitor Address Index Register + HDAT, 8, // Hardware Monitor Address Data Register + } + + // Registers for thermal zone implementations + IndexField (HIDX, HDAT, ByteAcc, NoLock, Preserve) + { + CNF1, 8, // Configuration Register index 01 - p. 71 datasheet + CNF2, 8, // Configuration Register index 02 + CNF3, 8, // Configuration Register index 03 + Offset (0x60), + PMEE, 8, // PME# Enable Register - p. 79 datasheet + TINS, 8, // Tempature Interrupt Status Register (idx 0x61) + TRTS, 8, // Tempature Real-Time Status Register + TBER, 8, // Tempature BEEP Enable Register + TOV1, 8, // T1 OVT and High Limit Tempature Select Register + TOVA, 8, // OVT and Alert Output Enable Register 1 + Offset (0x6B), + TSTR, 8, // Tempature Sensor Type Register (idx 0x6B) + Offset (0x72), + TIN1, 8, // TMPIN1 Reading + TIN2, 8, // TMPIN2 Reading + TIN3, 8, // TMPIN3 Reading + } + + Method (_STA, 0, NotSerialized) { + Return (ISEN (HMON)) + } + + // _CRS: Current Resource Setting + Name (_CRS, ResourceTemplate () + { + // v min v max v align v length + IO (Decode16, 0x0225, 0x0225, 0x00, 0x01) + }) + + // _PRS: Possible Resource Settings - Same as _CRS + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x0225, 0x0225, 0x00, 0x01) + + }) + } + +#endif /* SUPERIO_ACPI_FINTEK_ASL */

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Patch set updated for coreboot: 203a386 mainboard/jetway/nf81-t56n-lf: Provide ACPI thermal zone
by Edward O'Callaghan 28 Jul '14

28 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5889 -gerrit commit 203a38652ac51c0419dbc18e66fa695408e8a414 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 31 16:19:40 2014 +1000 mainboard/jetway/nf81-t56n-lf: Provide ACPI thermal zone NOTFORMERGE - yet - Has a SystemIO conflict with 0x...220 - 0x...227 from somewhere else??? Change-Id: Ibb0295154fca23a3819953db0119692b26096e34 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl | 26 +++++++- .../jetway/nf81-t56n-lf/acpi/mainboard.asl | 1 + src/mainboard/jetway/nf81-t56n-lf/acpi/thermal.asl | 74 ++++++++++++++++++++-- 3 files changed, 94 insertions(+), 7 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl index bb47ded..a30698a 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,7 +18,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -Scope(\_GPE) { /* Start Scope GPE */ +Scope(\_GPE) +{ + OperationRegion (IP, SystemIO, 0x0225, 0x02) + Field (IP, ByteAcc, NoLock, Preserve) + { + INDX, 8, + DAT0, 8 + } /* General event 3 */ Method(_L03) { @@ -31,9 +39,21 @@ Scope(\_GPE) { /* Start Scope GPE */ } /* Temp warning (TWarn) event */ - Method(_L09) { + Method(_L09, 0, NotSerialized) + { /* DBGO("\\_GPE\\_L09\n") */ - /* Notify (\_TZ.TZ00, 0x80) */ + Store (GBYT (0x66), Local0) + If (LNotEqual (And (Local0, 0x02), Zero)) + { + Notify (\_TZ.THRM, 0x80) + } + } + + Method (GBYT, 1, NotSerialized) + { + Store (Arg0, INDX) + Store (DAT0, Local0) + Return (Local0) } /* USB controller PME# */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl index 1f532cf..59027b7 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl @@ -33,6 +33,7 @@ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed * Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ Name(OSV, Ones) /* Assume nothing */ Name(PMOD, One) /* Assume APIC */ +Name (TPCH, Zero) /* Thermal zone channel */ Scope(\_SB) { Method(OSFL, 0){ diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/thermal.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/thermal.asl index 2f50475..058a23f 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/thermal.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/thermal.asl @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -15,7 +17,71 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Thermal Zones have been #if 0 for a long time. - * Removing it for now because it doesn't seem to - * do anything when enabled anyway. - */ +/* Thermal Zones. */ + +Scope (\_TZ) +{ + OperationRegion (IP, SystemIO, 0x0225, 0x02) + Field (IP, ByteAcc, NoLock, Preserve) + { + INDX, 8, + DAT0, 8 + } + + ThermalZone (THRM) + { + Method (KELV, 1, NotSerialized) + { + Store (Arg0, Local1) + Multiply (0x0A, Local1, Local1) + Add (Local1, 0x0AAC, Local1) + Return (Local1) + } + + Method (_TMP, 0, NotSerialized) // _TMP: Temperature + { + If (LEqual (TPCH, One)) + { + While (LGreater (GBYT (0x7A), 0x7E)) + { + Sleep (0xFA) + Store (One, Local1) + Multiply (0x0A, Local1, Local1) + Add (Local1, 0x0AAC, Local1) + Return (Local1) + } + } + + Return (KELV (CTMP ())) + } + + Method (_CRT, 0, NotSerialized) // _CRT: Critical Temperature + { + Return (KELV (STMP ())) + } + + Method (STMP, 0, NotSerialized) + { + Store (GBYT (0x82), Local0) + Return (Local0) + } + + Method (CTMP, 0, NotSerialized) + { + Store (GBYT (0x7A), Local0) + If (LGreaterEqual (Local0, 0x65)) + { + Store (0x30, Local0) + } + + Return (Local0) + } + + Method (GBYT, 1, NotSerialized) + { + Store (Arg0, INDX) + Store (DAT0, Local0) + Return (Local0) + } + } +}

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coreboot-gerrit July 2014