Patch set updated for coreboot: bf4ece6 superio/fintek/f71869ad: Provide ACPI ASL HWMON implementation

[Edward O'Callaghan]

Edward O'Callaghan ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6388

-gerrit

commit bf4ece65993301fcaa401284df984aedbc109605
Author: Edward O'Callaghan 
Date:   Mon Jul 28 17:29:35 2014 +1000

superio/fintek/f71869ad: Provide ACPI ASL HWMON implementation

This provides the ACPI component to the Fintek F71869AD Hardware
    Monitor. This lays the foundations for a proper thermal zone
    implementation for the Jetway NF81-T56N-LF board that uses this Super
    I/O.

Change-Id: I7d1ce0b738cba94b8a5985cf0c04e29b568f5fb0
    Signed-off-by: Edward O'Callaghan 
---
 src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl |   4 +-
 src/superio/fintek/f71869ad/acpi/superio.asl       | 185 +++++++++++++++++++++
 2 files changed, 188 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl
index 6dcb877..0a4854a 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl
+++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/superio.asl
@@ -19,4 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */

-#include "../../../../drivers/pc80/ps2_controller.asl"
+#define SUPERIO_INDEX 0x2E
+
+#include <superio/fintek/f71869ad/acpi/superio.asl>
diff --git a/src/superio/fintek/f71869ad/acpi/superio.asl b/src/superio/fintek/f71869ad/acpi/superio.asl
new file mode 100644
index 0000000..4fbaa4c
--- /dev/null
+++ b/src/superio/fintek/f71869ad/acpi/superio.asl
@@ -0,0 +1,185 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SUPERIO_ACPI_FINTEK_ASL
+#define SUPERIO_ACPI_FINTEK_ASL
+/*
+ * include this file into a mainboard's DSDT _SB device tree and it will expose
+ * the F71869AD SuperIO and its functionality.
+ */
+
+/* Define these in mainboard/xx/acpi/superio.asl */
+// #define SUPERIO_INDEX 0x2E or 0x4E
+
+Device(SIO) {
+	Name (_HID, EisaId("PNP0A05"))
+	Name (_STR, Unicode("Fintek F71869AD SuperIO"))
+	Name (_UID, "f71869ad")
+
+	/* Mutex for accesses to the configuration ports (prolog and epilog
+	 * commands are used, so synchronization is useful)
+	 */
+	Mutex(CRMX, 1)
+
+	/* Announce the used I/O both 0x2E & 0x4E configuration ports to the OS */
+	Method (_CRS)
+	{
+		Return (ResourceTemplate () {
+		IO (Decode16, 0x002E, 0x002E, 0x02, 0x01)
+		IO (Decode16, 0x004E, 0x004E, 0x01, 0x01)
+		})
+	}
+
+	/* Super I/O configuration region structure */
+	Name (_ADR, SUPERIO_INDEX)
+	OperationRegion (CREG, SystemIO, SUPERIO_INDEX, 0x02)
+	Field (CREG, ByteAcc, NoLock, Preserve)
+	{
+		ADDR,   8,
+		DATA,   8
+	}
+
+	/* Super I/O LDN configuration region structure */
+	IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve)
+	{
+		Offset (0x02),
+		SCNT, 8,	/* Configure Control */
+		Offset (0x07),
+		SLDN, 8,	/* Logical Device Number */
+		Offset (0x30),
+		SACT, 8,	/* Activate */
+		Offset (0x60),
+		IO0H, 8,	/* Base Address 0 MSB */
+		IO0L, 8,	/* Base Address 0 LSB */
+		Offset (0x62),
+		IO1H, 8,	/* Base Address 1 MSB */
+		IO1L, 8,	/* Base Address 1 LSB */
+		Offset (0x70),
+		IQ00, 8,	/* Interrupt Select */
+	}
+
+	/* Include Super I/O LDN numbers */
+#include "../f71869ad.h"
+	Name (HLDN, F71869AD_HWM)	/* Hardware Monitor */
+
+	/* Enter configuration mode (and aquire mutex)
+	 * Method must be run before accesssing the configuration region.
+	 */
+	Method (ENTR, 0, NotSerialized)
+	{
+		Acquire (CRMX, 0xFFFF) /* aquire mutex */
+		Store (0x87, ADDR) /* exit by writing 0x87 key into index port twice */
+		Store (0x87, ADDR)
+	}
+
+	/* Exit configuration mode (and release mutex)
+	 * Method must be run after accessing the configuration region.
+	 */
+	Method (EXIT, 0, NotSerialized)
+	{
+		Store (0xAA, ADDR) /* exit by writing 0xAA key into index port */
+		Release (CRMX)
+	}
+
+	/* Parse activate register for an LDN */
+	Method (ISEN, 1, NotSerialized)
+	{
+		ENTR ()
+		Store (Arg0, SLDN)
+		Store (SACT, Local0)
+		EXIT ()
+
+		/* Check if it exists */
+		If (LEqual (Local0, 0xFF))
+		{
+			Return (0x00)
+		}
+
+		/* Check if activated */
+		If (LEqual (Local0, One))
+		{
+			Return (0x0F) // DEVICE_PRESENT_ACTIVE (0x0F)
+		}
+		Else
+		{
+			Return (0x0D) // DEVICE_PRESENT_INACTIVE (0x0D)
+		}
+	}
+
+	/* ===================== Keyboard Controller ===================== */
+// include common driver
+#include <drivers/pc80/ps2_controller.asl>
+
+	/* ====================== Hardware Monitor ======================= */
+	Device (HMON)
+	{
+		Name (_HID, EisaId ("PNP0C02"))
+		Name (_STR, Unicode("Fintek F71869AD Hardware Monitor"))
+		Name (_UID, "f71869ad-hwmon")
+		Name (_ADR, 0x0225)
+
+		OperationRegion (IP, SystemIO, 0x0225, 0x02)
+		Field (IP, ByteAcc, NoLock, Preserve)
+		{
+			HIDX, 8,  // Hardware Monitor Address Index Register
+			HDAT, 8,  // Hardware Monitor Address Data Register
+		}
+
+		// Registers for thermal zone implementations
+		IndexField (HIDX, HDAT, ByteAcc, NoLock, Preserve)
+		{
+			CNF1, 8,  // Configuration Register index 01 - p. 71 datasheet
+			CNF2, 8,  // Configuration Register index 02
+			CNF3, 8,  // Configuration Register index 03
+			Offset (0x60),
+			PMEE, 8,  // PME# Enable Register - p. 79 datasheet
+			TINS, 8,  // Tempature Interrupt Status Register (idx 0x61)
+			TRTS, 8,  // Tempature Real-Time Status Register
+			TBER, 8,  // Tempature BEEP Enable Register
+			TOV1, 8,  // T1 OVT and High Limit Tempature Select Register
+			TOVA, 8,  // OVT and Alert Output Enable Register 1
+			Offset (0x6B),
+			TSTR, 8,  // Tempature Sensor Type Register (idx 0x6B)
+			Offset (0x72),
+			TIN1, 8,  // TMPIN1 Reading
+			TIN2, 8,  // TMPIN2 Reading
+			TIN3, 8,  // TMPIN3 Reading
+		}
+
+		Method (_STA, 0, NotSerialized) {
+			Return (ISEN (HLDN))
+		}
+
+		// _CRS: Current Resource Setting
+		Name (_CRS, ResourceTemplate ()
+		{
+			//            v min   v max  v align   v length
+			IO (Decode16, 0x0225, 0x0225, 0x00, 0x01)
+		})
+
+		// _PRS: Possible Resource Settings - Same as _CRS
+		Name (_PRS, ResourceTemplate ()
+		{
+			IO (Decode16, 0x0225, 0x0225, 0x00, 0x01)
+
+		})
+	}
+}
+
+#endif /* SUPERIO_ACPI_FINTEK_ASL */