coreboot-gerrit June 2014

coreboot-gerrit@coreboot.org

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922 discussions

Patch set updated for coreboot: ed6e901 Intel 945 boards: romstage.c: Use define for `BSM`
by Paul Menzel 07 Jun '14

07 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5929 -gerrit commit ed6e901e3b3e7a305ce4467cf5c38033218df3a2 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 08:50:17 2014 +0200 Intel 945 boards: romstage.c: Use define for `BSM` Change-Id: Ia58d8b410a145f27f0b267c115714580c366e063 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/getac/p470/romstage.c | 2 +- src/mainboard/ibase/mb899/romstage.c | 2 +- src/mainboard/intel/d945gclf/romstage.c | 2 +- src/mainboard/kontron/986lcd-m/romstage.c | 2 +- src/mainboard/lenovo/t60/romstage.c | 2 +- src/mainboard/lenovo/x60/romstage.c | 2 +- src/mainboard/roda/rk886ex/romstage.c | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index a081a8a..33b6726 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -347,7 +347,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 418b6e4..9dfd364 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -298,7 +298,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 69d4232..a0621ce 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -258,7 +258,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 4acd734..0ad7a2a 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -410,7 +410,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index dae917c..c5bb2f3 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -309,7 +309,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 1198fb2..1fed5f5 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -311,7 +311,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index ad323f5..2af294c 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -334,7 +334,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000);

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Patch set updated for coreboot: 6f056d0 lenovo/x60/i915.c: Log `PGETBL_CTL` programming
by Paul Menzel 07 Jun '14

07 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5934 -gerrit commit 6f056d0f67b641520a7826528867568a60bdeb91 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 09:38:39 2014 +0200 lenovo/x60/i915.c: Log `PGETBL_CTL` programming Correctly setting up `PGETBL_CTL` is essential for the operating system driver to work correctly. Therefore log it more verbosely. Change-Id: I9b3dfa52f91c13e768c2ef980e5871173a85fcfe Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 016217f..95b836a 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -141,13 +141,16 @@ int gtt_setup(unsigned int mmiobase) write32(mmiobase + GFX_FLSH_CNTL, 0); + printk(BIOS_DEBUG, "%s: Write %lx to PGETBL_CTL ...", __func__, pgetbl_ctl); write32(mmiobase + PGETBL_CTL, pgetbl_ctl); /* verify */ - if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) { - printk(BIOS_DEBUG, "gtt_setup is enabled.\n"); + pgetbl_ctl = read32(mmiobase + PGETBL_CTL); + printk(BIOS_DEBUG, " read back %lx ...", pgetbl_ctl); + if (pgetbl_ctl & PGETBL_ENABLED) { + printk(BIOS_DEBUG, " GM mappings enabled ... GTT setup successful.\n"); } else { - printk(BIOS_DEBUG, "gtt_setup failed!!!\n"); + printk(BIOS_DEBUG, " GM mappings disabled ... GTT setup failed.\n"); return 1; } write32(mmiobase + GFX_FLSH_CNTL, 0);

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Patch set updated for coreboot: bfc444c lenovo/x60/i915.c: Use define for `BSM`
by Paul Menzel 07 Jun '14

07 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5932 -gerrit commit bfc444c08d9d67eb092ae750abf88502c119f36e Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 08:50:17 2014 +0200 lenovo/x60/i915.c: Use define for `BSM` Although it builds without any further changes, including the header src/northbridge/intel/i945/i945.h where `BSM` is defined, would be useful. Unfortunately that conflicts with the already included header `southbridge/intel/bd82x6x/pch.h`, so it is left as is. Change-Id: I7c0a795338c34038169e082446907987364a0e88 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index b41a0ba..8fbd2a1 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -138,7 +138,7 @@ int gtt_setup(unsigned int mmiobase) PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; PGETBL_save |= PGETBL_ENABLED; - PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000; + PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfffff000; PGETBL_save |= 2; /* set GTT to 256kb */ write32(mmiobase + GFX_FLSH_CNTL, 0);

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Patch set updated for coreboot: d5354a9 lenovo/x60/i915.c: Rename variable `PGETBL_save` to `pgetbl_ctl`
by Paul Menzel 07 Jun '14

07 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5933 -gerrit commit d5354a9476a5817c82d3f7a82b4cbc5a75f03bad Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 09:41:06 2014 +0200 lenovo/x60/i915.c: Rename variable `PGETBL_save` to `pgetbl_ctl` The name was taken from the function `intel_gtt_init()` in `drivers/char/agp/intel-gtt.c` in the Linux kernel. It is used differently here `gtt_setup()`, so rename it. Change-Id: I16896fc9383a5e40992a24fa096fd373db66e436 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 6e67bff..016217f 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -131,17 +131,17 @@ setgtt(int start, int end, unsigned long base, int inc) int gtt_setup(unsigned int mmiobase); int gtt_setup(unsigned int mmiobase) { - unsigned long PGETBL_save; + unsigned long pgetbl_ctl; - PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; - PGETBL_save |= PGETBL_ENABLED; + pgetbl_ctl = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; + pgetbl_ctl |= PGETBL_ENABLED; - PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfffff000; - PGETBL_save |= 2; /* set GTT to 256kb */ + pgetbl_ctl |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfffff000; + pgetbl_ctl |= 2; /* set GTT to 256kb */ write32(mmiobase + GFX_FLSH_CNTL, 0); - write32(mmiobase + PGETBL_CTL, PGETBL_save); + write32(mmiobase + PGETBL_CTL, pgetbl_ctl); /* verify */ if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) {

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Patch set updated for coreboot: 55e80d1 lenovo/x60: Fix build issue with DO_NATIVE_VGA_INIT
by Stefan Tauner 07 Jun '14

07 Jun '14

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5893 -gerrit commit 55e80d15cbe15e3755b7234248719be1e6e245e2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat May 31 17:08:40 2014 +0300 lenovo/x60: Fix build issue with DO_NATIVE_VGA_INIT Use the value from hardware for uma_memory_base. Change-Id: I70351166db6634ef3bca2bf12051ccc3730cab8e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/i945/gma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 1cf80a9..0c45cb3 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -64,6 +64,7 @@ static void gma_func0_init(struct device *dev) ); int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); + u32 uma_memory_base = pci_read_config32(dev, BSM) & ~((1<<20) - 1); int lightup_ok = i915lightup(uma_memory_base, iobase, mmiobase, graphics_base); if (lightup_ok) gfx_set_init_done(1);

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Patch set updated for coreboot: 86faf54 ibexpeak: Set number of USB ports.
by Vladimir Serbinenko 07 Jun '14

07 Jun '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5956 -gerrit commit 86faf54c3fcfeffd81e09cb29f41259178004db8 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jun 7 16:41:14 2014 +0200 ibexpeak: Set number of USB ports. Change-Id: Ife3febcc88967386dfae624cd237562a34a68471 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/ibexpeak/usb_ehci.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index 21a257f..868a068 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -30,6 +30,8 @@ static void usb_ehci_init(struct device *dev) { u32 reg32; + struct resource *res; + u8 access_cntl; /* Disable Wake on Disconnect in RMH */ reg32 = RCBA32(0x35b0); @@ -50,6 +52,21 @@ static void usb_ehci_init(struct device *dev) //reg32 |= PCI_COMMAND_SERR; pci_write_config32(dev, PCI_COMMAND, reg32); + access_cntl = pci_read_config8(dev, 0x80); + + /* Enable writes to protected registers. */ + pci_write_config8(dev, 0x80, access_cntl | 1); + + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + /* Number of ports and companion controllers. */ + reg32 = read32(res->base + 4); + write32(res->base + 4, (reg32 & 0xfff00000) | 2); + } + + /* Restore protection. */ + pci_write_config8(dev, 0x80, access_cntl); + printk(BIOS_DEBUG, "done.\n"); }

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Patch set updated for coreboot: 0d447a7 nehalem: Move cbmem_recovery call to raminit.
by Vladimir Serbinenko 07 Jun '14

07 Jun '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5954 -gerrit commit 0d447a771b1a4aa11bb44ffa89fe21a8ebf3641b Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jun 7 16:27:27 2014 +0200 nehalem: Move cbmem_recovery call to raminit. Currently cbmem_recovery is done in raminit only on non-S3-resume path do it on both paths to reduce confusion. Change-Id: I16161ad449b9802a855fcf834aa721f4f65c0bb4 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/romstage.c | 10 ---------- src/mainboard/packardbell/ms2290/romstage.c | 10 ---------- src/northbridge/intel/nehalem/raminit.c | 15 +++++++++++++++ 3 files changed, 15 insertions(+), 20 deletions(-) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 1237a5c..232b3d8 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -323,16 +323,6 @@ void main(unsigned long bist) if (s3resume) { void *resume_backup_memory; - /* For non-S3-resume, CBMEM is inited in raminit code. */ - if (cbmem_recovery(1)) { - printk(BIOS_ERR, "Failed S3 resume.\n"); - ram_check(0x100000, 0x200000); - - /* Failed S3 resume, reset to come up cleanly */ - outb(0xe, 0xcf9); - hlt(); - } - resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 6a18dd6..d3744a5 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -300,16 +300,6 @@ void main(unsigned long bist) if (s3resume) { void *resume_backup_memory; - /* For non-S3-resume, CBMEM is inited in raminit code. */ - if (cbmem_recovery(1)) { - printk(BIOS_ERR, "Failed S3 resume.\n"); - ram_check(0x100000, 0x200000); - - /* Failed S3 resume, reset to come up cleanly */ - outb(0xe, 0xcf9); - hlt(); - } - resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 978ffbf..6545305 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -4977,6 +4977,21 @@ void raminit(const int s3resume, const u8 *spd_addrmap) dump_timings(&info); if (!s3resume) save_timings(&info); + if (s3resume) { + if (cbmem_recovery(1)) { + u32 reg32; + printk(BIOS_ERR, "Failed S3 resume.\n"); + ram_check(0x100000, 0x200000); + + /* Clear SLP_TYPE. */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + + /* Failed S3 resume, reset to come up cleanly */ + outb(0xe, 0xcf9); + hlt(); + } + } #endif }

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Patch set updated for coreboot: af22e2d ibrexpeak: Remove some dead code.
by Vladimir Serbinenko 07 Jun '14

07 Jun '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5955 -gerrit commit af22e2d01c32ba3db300531413448c5ce48c7dc4 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jun 7 16:30:35 2014 +0200 ibrexpeak: Remove some dead code. Change-Id: I68ae49d20a2524f03c4503f2b3be93f07b9cb6e3 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/ibexpeak/me.c | 125 ----------------------------------- src/southbridge/intel/ibexpeak/smi.c | 6 -- 2 files changed, 131 deletions(-) diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index bc56012..0e1b5b8 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -377,125 +377,7 @@ static int mkhi_end_of_post(void) printk(BIOS_INFO, "ME: END OF POST message successful\n"); return 0; } -#endif - -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) && (CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) -/* Get ME firmware version */ -static int mkhi_get_fw_version(void) -{ - struct me_fw_version version; - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_GEN, - .command = MKHI_GET_FW_VERSION, - }; - struct mei_header mei = { - .is_complete = 1, - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - .length = sizeof(mkhi), - }; - - /* Send request and wait for response */ - if (mei_sendrecv(&mei, &mkhi, NULL, &version, sizeof(version)) < 0) { - printk(BIOS_ERR, "ME: GET FW VERSION message failed\n"); - return -1; - } - - printk(BIOS_INFO, "ME: Firmware Version %u.%u.%u.%u (code) " - "%u.%u.%u.%u (recovery)\n", - version.code_major, version.code_minor, - version.code_build_number, version.code_hot_fix, - version.recovery_major, version.recovery_minor, - version.recovery_build_number, version.recovery_hot_fix); - - return 0; -} - -static inline void print_cap(const char *name, int state) -{ - printk(BIOS_DEBUG, "ME Capability: %-30s : %sabled\n", - name, state ? "en" : "dis"); -} - -/* Get ME Firmware Capabilities */ -static int mkhi_get_fwcaps(void) -{ - u32 rule_id = 0; - struct me_fwcaps cap; - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_FWCAPS, - .command = MKHI_FWCAPS_GET_RULE, - }; - struct mei_header mei = { - .is_complete = 1, - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - .length = sizeof(mkhi) + sizeof(rule_id), - }; - - /* Send request and wait for response */ - if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap, sizeof(cap)) < 0) { - printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); - return -1; - } - - print_cap("Full Network manageability", cap.caps_sku.full_net); - print_cap("Regular Network manageability", cap.caps_sku.std_net); - print_cap("Manageability", cap.caps_sku.manageability); - print_cap("Small business technology", cap.caps_sku.small_business); - print_cap("Level III manageability", cap.caps_sku.l3manageability); - print_cap("IntelR Anti-Theft (AT)", cap.caps_sku.intel_at); - print_cap("IntelR Capability Licensing Service (CLS)", - cap.caps_sku.intel_cls); - print_cap("IntelR Power Sharing Technology (MPC)", - cap.caps_sku.intel_mpc); - print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp); - print_cap("IPV6", cap.caps_sku.ipv6); - print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm); - print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och); - print_cap("Virtual LAN (VLAN)", cap.caps_sku.vlan); - print_cap("TLS", cap.caps_sku.tls); - print_cap("Wireless LAN (WLAN)", cap.caps_sku.wlan); - - return 0; -} -#endif -#if CONFIG_CHROMEOS && 0 /* DISABLED */ -/* Tell ME to issue a global reset */ -int mkhi_global_reset(void) -{ - struct me_global_reset reset = { - .request_origin = GLOBAL_RESET_BIOS_POST, - .reset_type = CBM_RR_GLOBAL_RESET, - }; - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_CBM, - .command = MKHI_GLOBAL_RESET, - }; - struct mei_header mei = { - .is_complete = 1, - .length = sizeof(mkhi) + sizeof(reset), - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - }; - - printk(BIOS_NOTICE, "ME: Requesting global reset\n"); - - /* Send request and wait for response */ - if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) { - /* No response means reset will happen shortly... */ - hlt(); - } - - /* If the ME responded it rejected the reset request */ - printk(BIOS_ERR, "ME: Global Reset failed\n"); - return -1; -} -#endif - -#ifdef __SMM__ static void intel_me7_finalize_smm(void) { struct me_hfs hfs; @@ -723,13 +605,6 @@ static void intel_me_init(device_t dev) if (intel_mei_setup(dev) < 0) break; -#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && (CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) - /* Print ME firmware version */ - mkhi_get_fw_version(); - /* Print ME firmware capabilities */ - mkhi_get_fwcaps(); -#endif - /* * Leave the ME unlocked in this path. * It will be locked via SMI command later. diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c index 981be3b..2ce9072 100644 --- a/src/southbridge/intel/ibexpeak/smi.c +++ b/src/southbridge/intel/ibexpeak/smi.c @@ -31,13 +31,7 @@ #include <string.h> #include "pch.h" -#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE -#include "northbridge/intel/sandybridge/sandybridge.h" -#endif - -#if CONFIG_NORTHBRIDGE_INTEL_NEHALEM #include "northbridge/intel/nehalem/nehalem.h" -#endif extern unsigned char _binary_smm_start; extern unsigned char _binary_smm_end;

1 0

Patch set updated for coreboot: cae6a08 ibexpeak: Set number of USB ports.
by Vladimir Serbinenko 07 Jun '14

07 Jun '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5956 -gerrit commit cae6a0871cdbfef2bad0ebc27bdfa7180a65ad76 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jun 7 16:41:14 2014 +0200 ibexpeak: Set number of USB ports. Change-Id: Ife3febcc88967386dfae624cd237562a34a68471 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/ibexpeak/usb_ehci.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index 21a257f..868a068 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -30,6 +30,8 @@ static void usb_ehci_init(struct device *dev) { u32 reg32; + struct resource *res; + u8 access_cntl; /* Disable Wake on Disconnect in RMH */ reg32 = RCBA32(0x35b0); @@ -50,6 +52,21 @@ static void usb_ehci_init(struct device *dev) //reg32 |= PCI_COMMAND_SERR; pci_write_config32(dev, PCI_COMMAND, reg32); + access_cntl = pci_read_config8(dev, 0x80); + + /* Enable writes to protected registers. */ + pci_write_config8(dev, 0x80, access_cntl | 1); + + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) { + /* Number of ports and companion controllers. */ + reg32 = read32(res->base + 4); + write32(res->base + 4, (reg32 & 0xfff00000) | 2); + } + + /* Restore protection. */ + pci_write_config8(dev, 0x80, access_cntl); + printk(BIOS_DEBUG, "done.\n"); }

1 0

Patch set updated for coreboot: 0a3cc5f x230: Deploy VBT
by Vladimir Serbinenko 07 Jun '14

07 Jun '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5396 -gerrit commit 0a3cc5faec109f51442fcf18a09ab5ef871f35bb Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 23 00:13:56 2014 +0100 x230: Deploy VBT Change-Id: Ide31a56bfdbc31cd3b87993dfb4ed8ef0107cdba Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/gma/intel_bios.h | 733 +++++++++++++++++++++ .../intel/sandybridge/gma_ivybridge_lvds.c | 84 +++ 2 files changed, 817 insertions(+) diff --git a/src/drivers/intel/gma/intel_bios.h b/src/drivers/intel/gma/intel_bios.h new file mode 100644 index 0000000..36426d8 --- /dev/null +++ b/src/drivers/intel/gma/intel_bios.h @@ -0,0 +1,733 @@ +/* + * Copyright © 2006 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Eric Anholt <eric(a)anholt.net> + * + */ + +#ifndef _I830_BIOS_H_ +#define _I830_BIOS_H_ + +struct vbt_header { + u8 signature[20]; /**< Always starts with 'VBT$' */ + u16 version; /**< decimal */ + u16 header_size; /**< in bytes */ + u16 vbt_size; /**< in bytes */ + u8 vbt_checksum; + u8 reserved0; + u32 bdb_offset; /**< from beginning of VBT */ + u32 aim_offset[4]; /**< from beginning of VBT */ +} __attribute__((packed)); + +struct bdb_header { + u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */ + u16 version; /**< decimal */ + u16 header_size; /**< in bytes */ + u16 bdb_size; /**< in bytes */ +}; + +/* strictly speaking, this is a "skip" block, but it has interesting info */ +struct vbios_data { + u8 type; /* 0 == desktop, 1 == mobile */ + u8 relstage; + u8 chipset; + u8 lvds_present:1; + u8 tv_present:1; + u8 rsvd2:6; /* finish byte */ + u8 rsvd3[4]; + u8 signon[155]; + u8 copyright[61]; + u16 code_segment; + u8 dos_boot_mode; + u8 bandwidth_percent; + u8 rsvd4; /* popup memory size */ + u8 resize_pci_bios; + u8 rsvd5; /* is crt already on ddc2 */ +} __attribute__((packed)); + +/* + * There are several types of BIOS data blocks (BDBs), each block has + * an ID and size in the first 3 bytes (ID in first, size in next 2). + * Known types are listed below. + */ +#define BDB_GENERAL_FEATURES 1 +#define BDB_GENERAL_DEFINITIONS 2 +#define BDB_OLD_TOGGLE_LIST 3 +#define BDB_MODE_SUPPORT_LIST 4 +#define BDB_GENERIC_MODE_TABLE 5 +#define BDB_EXT_MMIO_REGS 6 +#define BDB_SWF_IO 7 +#define BDB_SWF_MMIO 8 +#define BDB_DOT_CLOCK_TABLE 9 +#define BDB_MODE_REMOVAL_TABLE 10 +#define BDB_CHILD_DEVICE_TABLE 11 +#define BDB_DRIVER_FEATURES 12 +#define BDB_DRIVER_PERSISTENCE 13 +#define BDB_EXT_TABLE_PTRS 14 +#define BDB_DOT_CLOCK_OVERRIDE 15 +#define BDB_DISPLAY_SELECT 16 +/* 17 rsvd */ +#define BDB_DRIVER_ROTATION 18 +#define BDB_DISPLAY_REMOVE 19 +#define BDB_OEM_CUSTOM 20 +#define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */ +#define BDB_SDVO_LVDS_OPTIONS 22 +#define BDB_SDVO_PANEL_DTDS 23 +#define BDB_SDVO_LVDS_PNP_IDS 24 +#define BDB_SDVO_LVDS_POWER_SEQ 25 +#define BDB_TV_OPTIONS 26 +#define BDB_EDP 27 +#define BDB_LVDS_OPTIONS 40 +#define BDB_LVDS_LFP_DATA_PTRS 41 +#define BDB_LVDS_LFP_DATA 42 +#define BDB_LVDS_BACKLIGHT 43 +#define BDB_LVDS_POWER 44 +#define BDB_MIPI 50 +#define BDB_SKIP 254 /* VBIOS private block, ignore */ + +struct bdb_general_features { + /* bits 1 */ + u8 panel_fitting:2; + u8 flexaim:1; + u8 msg_enable:1; + u8 clear_screen:3; + u8 color_flip:1; + + /* bits 2 */ + u8 download_ext_vbt:1; + u8 enable_ssc:1; + u8 ssc_freq:1; + u8 enable_lfp_on_override:1; + u8 disable_ssc_ddt:1; + u8 rsvd7:1; + u8 display_clock_mode:1; + u8 rsvd8:1; /* finish byte */ + + /* bits 3 */ + u8 disable_smooth_vision:1; + u8 single_dvi:1; + u8 rsvd9:1; + u8 fdi_rx_polarity_inverted:1; + u8 rsvd10:4; /* finish byte */ + + /* bits 4 */ + u8 legacy_monitor_detect; + + /* bits 5 */ + u8 int_crt_support:1; + u8 int_tv_support:1; + u8 int_efp_support:1; + u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ + u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ + u8 rsvd11:3; /* finish byte */ +} __attribute__((packed)); + +/* pre-915 */ +#define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ +#define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ +#define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ +#define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ + +/* Pre 915 */ +#define DEVICE_TYPE_NONE 0x00 +#define DEVICE_TYPE_CRT 0x01 +#define DEVICE_TYPE_TV 0x09 +#define DEVICE_TYPE_EFP 0x12 +#define DEVICE_TYPE_LFP 0x22 +/* On 915+ */ +#define DEVICE_TYPE_CRT_DPMS 0x6001 +#define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 +#define DEVICE_TYPE_TV_COMPOSITE 0x0209 +#define DEVICE_TYPE_TV_MACROVISION 0x0289 +#define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c +#define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 +#define DEVICE_TYPE_TV_SCART 0x0209 +#define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 +#define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 +#define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 +#define DEVICE_TYPE_EFP_DVI_I 0x6053 +#define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 +#define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 +#define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 +#define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 +#define DEVICE_TYPE_LFP_PANELLINK 0x5012 +#define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 +#define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 +#define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 +#define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 + +#define DEVICE_CFG_NONE 0x00 +#define DEVICE_CFG_12BIT_DVOB 0x01 +#define DEVICE_CFG_12BIT_DVOC 0x02 +#define DEVICE_CFG_24BIT_DVOBC 0x09 +#define DEVICE_CFG_24BIT_DVOCB 0x0a +#define DEVICE_CFG_DUAL_DVOB 0x11 +#define DEVICE_CFG_DUAL_DVOC 0x12 +#define DEVICE_CFG_DUAL_DVOBC 0x13 +#define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 +#define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a + +#define DEVICE_WIRE_NONE 0x00 +#define DEVICE_WIRE_DVOB 0x01 +#define DEVICE_WIRE_DVOC 0x02 +#define DEVICE_WIRE_DVOBC 0x03 +#define DEVICE_WIRE_DVOBB 0x05 +#define DEVICE_WIRE_DVOCC 0x06 +#define DEVICE_WIRE_DVOB_MASTER 0x0d +#define DEVICE_WIRE_DVOC_MASTER 0x0e + +#define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ +#define DEVICE_PORT_DVOB 0x01 +#define DEVICE_PORT_DVOC 0x02 + +/* We used to keep this struct but without any version control. We should avoid + * using it in the future, but it should be safe to keep using it in the old + * code. */ +struct old_child_dev_config { + u16 handle; + u16 device_type; + u8 device_id[10]; /* ascii string */ + u16 addin_offset; + u8 dvo_port; /* See Device_PORT_* above */ + u8 i2c_pin; + u8 slave_addr; + u8 ddc_pin; + u16 edid_ptr; + u8 dvo_cfg; /* See DEVICE_CFG_* above */ + u8 dvo2_port; + u8 i2c2_pin; + u8 slave2_addr; + u8 ddc2_pin; + u8 capabilities; + u8 dvo_wiring;/* See DEVICE_WIRE_* above */ + u8 dvo2_wiring; + u16 extended_type; + u8 dvo_function; +} __attribute__((packed)); + +/* This one contains field offsets that are known to be common for all BDB + * versions. Notice that the meaning of the contents contents may still change, + * but at least the offsets are consistent. */ +struct common_child_dev_config { + u16 handle; + u16 device_type; + u8 not_common1[12]; + u8 dvo_port; + u8 not_common2[2]; + u8 ddc_pin; + u16 edid_ptr; +} __attribute__((packed)); + +/* This field changes depending on the BDB version, so the most reliable way to + * read it is by checking the BDB version and reading the raw pointer. */ +union child_device_config { + /* This one is safe to be used anywhere, but the code should still check + * the BDB version. */ + u8 raw[33]; + /* This one should only be kept for legacy code. */ + struct old_child_dev_config old; + /* This one should also be safe to use anywhere, even without version + * checks. */ + struct common_child_dev_config common; +}; + +struct bdb_general_definitions { + /* DDC GPIO */ + u8 crt_ddc_gmbus_pin; + + /* DPMS bits */ + u8 dpms_acpi:1; + u8 skip_boot_crt_detect:1; + u8 dpms_aim:1; + u8 rsvd1:5; /* finish byte */ + + /* boot device bits */ + u8 boot_display[2]; + u8 child_dev_size; + + /* + * Device info: + * If TV is present, it'll be at devices[0]. + * LVDS will be next, either devices[0] or [1], if present. + * On some platforms the number of device is 6. But could be as few as + * 4 if both TV and LVDS are missing. + * And the device num is related with the size of general definition + * block. It is obtained by using the following formula: + * number = (block_size - sizeof(bdb_general_definitions))/ + * sizeof(child_device_config); + */ + union child_device_config devices[0]; +} __attribute__((packed)); + +struct bdb_lvds_options { + u8 panel_type; + u8 rsvd1; + /* LVDS capabilities, stored in a dword */ + u8 pfit_mode:2; + u8 pfit_text_mode_enhanced:1; + u8 pfit_gfx_mode_enhanced:1; + u8 pfit_ratio_auto:1; + u8 pixel_dither:1; + u8 lvds_edid:1; + u8 rsvd2:1; + u8 rsvd4; +} __attribute__((packed)); + +/* LFP pointer table contains entries to the struct below */ +struct bdb_lvds_lfp_data_ptr { + u16 fp_timing_offset; /* offsets are from start of bdb */ + u8 fp_table_size; + u16 dvo_timing_offset; + u8 dvo_table_size; + u16 panel_pnp_id_offset; + u8 pnp_table_size; +} __attribute__((packed)); + +struct bdb_lvds_lfp_data_ptrs { + u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ + struct bdb_lvds_lfp_data_ptr ptr[16]; +} __attribute__((packed)); + +/* LFP data has 3 blocks per entry */ +struct lvds_fp_timing { + u16 x_res; + u16 y_res; + u32 lvds_reg; + u32 lvds_reg_val; + u32 pp_on_reg; + u32 pp_on_reg_val; + u32 pp_off_reg; + u32 pp_off_reg_val; + u32 pp_cycle_reg; + u32 pp_cycle_reg_val; + u32 pfit_reg; + u32 pfit_reg_val; + u16 terminator; +} __attribute__((packed)); + +struct lvds_dvo_timing { + u16 clock; /**< In 10khz */ + u8 hactive_lo; + u8 hblank_lo; + u8 hblank_hi:4; + u8 hactive_hi:4; + u8 vactive_lo; + u8 vblank_lo; + u8 vblank_hi:4; + u8 vactive_hi:4; + u8 hsync_off_lo; + u8 hsync_pulse_width; + u8 vsync_pulse_width:4; + u8 vsync_off:4; + u8 rsvd0:6; + u8 hsync_off_hi:2; + u8 h_image; + u8 v_image; + u8 max_hv; + u8 h_border; + u8 v_border; + u8 rsvd1:3; + u8 digital:2; + u8 vsync_positive:1; + u8 hsync_positive:1; + u8 rsvd2:1; +} __attribute__((packed)); + +struct lvds_pnp_id { + u16 mfg_name; + u16 product_code; + u32 serial; + u8 mfg_week; + u8 mfg_year; +} __attribute__((packed)); + +struct bdb_lvds_lfp_data_entry { + struct lvds_fp_timing fp_timing; + struct lvds_dvo_timing dvo_timing; + struct lvds_pnp_id pnp_id; +} __attribute__((packed)); + +struct bdb_lvds_lfp_data { + struct bdb_lvds_lfp_data_entry data[16]; +} __attribute__((packed)); + +struct aimdb_header { + char signature[16]; + char oem_device[20]; + u16 aimdb_version; + u16 aimdb_header_size; + u16 aimdb_size; +} __attribute__((packed)); + +struct aimdb_block { + u8 aimdb_id; + u16 aimdb_size; +} __attribute__((packed)); + +struct vch_panel_data { + u16 fp_timing_offset; + u8 fp_timing_size; + u16 dvo_timing_offset; + u8 dvo_timing_size; + u16 text_fitting_offset; + u8 text_fitting_size; + u16 graphics_fitting_offset; + u8 graphics_fitting_size; +} __attribute__((packed)); + +struct vch_bdb_22 { + struct aimdb_block aimdb_block; + struct vch_panel_data panels[16]; +} __attribute__((packed)); + +struct bdb_sdvo_lvds_options { + u8 panel_backlight; + u8 h40_set_panel_type; + u8 panel_type; + u8 ssc_clk_freq; + u16 als_low_trip; + u16 als_high_trip; + u8 sclalarcoeff_tab_row_num; + u8 sclalarcoeff_tab_row_size; + u8 coefficient[8]; + u8 panel_misc_bits_1; + u8 panel_misc_bits_2; + u8 panel_misc_bits_3; + u8 panel_misc_bits_4; +} __attribute__((packed)); + + +#define BDB_DRIVER_FEATURE_NO_LVDS 0 +#define BDB_DRIVER_FEATURE_INT_LVDS 1 +#define BDB_DRIVER_FEATURE_SDVO_LVDS 2 +#define BDB_DRIVER_FEATURE_EDP 3 + +struct bdb_driver_features { + u8 boot_dev_algorithm:1; + u8 block_display_switch:1; + u8 allow_display_switch:1; + u8 hotplug_dvo:1; + u8 dual_view_zoom:1; + u8 int15h_hook:1; + u8 sprite_in_clone:1; + u8 primary_lfp_id:1; + + u16 boot_mode_x; + u16 boot_mode_y; + u8 boot_mode_bpp; + u8 boot_mode_refresh; + + u16 enable_lfp_primary:1; + u16 selective_mode_pruning:1; + u16 dual_frequency:1; + u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ + u16 nt_clone_support:1; + u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ + u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ + u16 cui_aspect_scaling:1; + u16 preserve_aspect_ratio:1; + u16 sdvo_device_power_down:1; + u16 crt_hotplug:1; + u16 lvds_config:2; + u16 tv_hotplug:1; + u16 hdmi_config:2; + + u8 static_display:1; + u8 reserved2:7; + u16 legacy_crt_max_x; + u16 legacy_crt_max_y; + u8 legacy_crt_max_refresh; + + u8 hdmi_termination; + u8 custom_vbt_version; +} __attribute__((packed)); + +#define EDP_18BPP 0 +#define EDP_24BPP 1 +#define EDP_30BPP 2 +#define EDP_RATE_1_62 0 +#define EDP_RATE_2_7 1 +#define EDP_LANE_1 0 +#define EDP_LANE_2 1 +#define EDP_LANE_4 3 +#define EDP_PREEMPHASIS_NONE 0 +#define EDP_PREEMPHASIS_3_5dB 1 +#define EDP_PREEMPHASIS_6dB 2 +#define EDP_PREEMPHASIS_9_5dB 3 +#define EDP_VSWING_0_4V 0 +#define EDP_VSWING_0_6V 1 +#define EDP_VSWING_0_8V 2 +#define EDP_VSWING_1_2V 3 + +struct edp_power_seq { + u16 t1_t3; + u16 t8; + u16 t9; + u16 t10; + u16 t11_t12; +} __attribute__ ((packed)); + +struct edp_link_params { + u8 rate:4; + u8 lanes:4; + u8 preemphasis:4; + u8 vswing:4; +} __attribute__ ((packed)); + +struct bdb_edp { + struct edp_power_seq power_seqs[16]; + u32 color_depth; + struct edp_link_params link_params[16]; + u32 sdrrs_msa_timing_delay; + + /* ith bit indicates enabled/disabled for (i+1)th panel */ + u16 edp_s3d_feature; + u16 edp_t3_optimization; +} __attribute__ ((packed)); + +/* + * Driver<->VBIOS interaction occurs through scratch bits in + * GR18 & SWF*. + */ + +/* GR18 bits are set on display switch and hotkey events */ +#define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */ +#define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */ +#define GR18_HK_NONE (0x0<<3) +#define GR18_HK_LFP_STRETCH (0x1<<3) +#define GR18_HK_TOGGLE_DISP (0x2<<3) +#define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */ +#define GR18_HK_POPUP_DISABLED (0x6<<3) +#define GR18_HK_POPUP_ENABLED (0x7<<3) +#define GR18_HK_PFIT (0x8<<3) +#define GR18_HK_APM_CHANGE (0xa<<3) +#define GR18_HK_MULTIPLE (0xc<<3) +#define GR18_USER_INT_EN (1<<2) +#define GR18_A0000_FLUSH_EN (1<<1) +#define GR18_SMM_EN (1<<0) + +/* Set by driver, cleared by VBIOS */ +#define SWF00_YRES_SHIFT 16 +#define SWF00_XRES_SHIFT 0 +#define SWF00_RES_MASK 0xffff + +/* Set by VBIOS at boot time and driver at runtime */ +#define SWF01_TV2_FORMAT_SHIFT 8 +#define SWF01_TV1_FORMAT_SHIFT 0 +#define SWF01_TV_FORMAT_MASK 0xffff + +#define SWF10_VBIOS_BLC_I2C_EN (1<<29) +#define SWF10_GTT_OVERRIDE_EN (1<<28) +#define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */ +#define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24) +#define SWF10_OLD_TOGGLE 0x0 +#define SWF10_TOGGLE_LIST_1 0x1 +#define SWF10_TOGGLE_LIST_2 0x2 +#define SWF10_TOGGLE_LIST_3 0x3 +#define SWF10_TOGGLE_LIST_4 0x4 +#define SWF10_PANNING_EN (1<<23) +#define SWF10_DRIVER_LOADED (1<<22) +#define SWF10_EXTENDED_DESKTOP (1<<21) +#define SWF10_EXCLUSIVE_MODE (1<<20) +#define SWF10_OVERLAY_EN (1<<19) +#define SWF10_PLANEB_HOLDOFF (1<<18) +#define SWF10_PLANEA_HOLDOFF (1<<17) +#define SWF10_VGA_HOLDOFF (1<<16) +#define SWF10_ACTIVE_DISP_MASK 0xffff +#define SWF10_PIPEB_LFP2 (1<<15) +#define SWF10_PIPEB_EFP2 (1<<14) +#define SWF10_PIPEB_TV2 (1<<13) +#define SWF10_PIPEB_CRT2 (1<<12) +#define SWF10_PIPEB_LFP (1<<11) +#define SWF10_PIPEB_EFP (1<<10) +#define SWF10_PIPEB_TV (1<<9) +#define SWF10_PIPEB_CRT (1<<8) +#define SWF10_PIPEA_LFP2 (1<<7) +#define SWF10_PIPEA_EFP2 (1<<6) +#define SWF10_PIPEA_TV2 (1<<5) +#define SWF10_PIPEA_CRT2 (1<<4) +#define SWF10_PIPEA_LFP (1<<3) +#define SWF10_PIPEA_EFP (1<<2) +#define SWF10_PIPEA_TV (1<<1) +#define SWF10_PIPEA_CRT (1<<0) + +#define SWF11_MEMORY_SIZE_SHIFT 16 +#define SWF11_SV_TEST_EN (1<<15) +#define SWF11_IS_AGP (1<<14) +#define SWF11_DISPLAY_HOLDOFF (1<<13) +#define SWF11_DPMS_REDUCED (1<<12) +#define SWF11_IS_VBE_MODE (1<<11) +#define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */ +#define SWF11_DPMS_MASK 0x07 +#define SWF11_DPMS_OFF (1<<2) +#define SWF11_DPMS_SUSPEND (1<<1) +#define SWF11_DPMS_STANDBY (1<<0) +#define SWF11_DPMS_ON 0 + +#define SWF14_GFX_PFIT_EN (1<<31) +#define SWF14_TEXT_PFIT_EN (1<<30) +#define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */ +#define SWF14_POPUP_EN (1<<28) +#define SWF14_DISPLAY_HOLDOFF (1<<27) +#define SWF14_DISP_DETECT_EN (1<<26) +#define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */ +#define SWF14_DRIVER_STATUS (1<<24) +#define SWF14_OS_TYPE_WIN9X (1<<23) +#define SWF14_OS_TYPE_WINNT (1<<22) +/* 21:19 rsvd */ +#define SWF14_PM_TYPE_MASK 0x00070000 +#define SWF14_PM_ACPI_VIDEO (0x4 << 16) +#define SWF14_PM_ACPI (0x3 << 16) +#define SWF14_PM_APM_12 (0x2 << 16) +#define SWF14_PM_APM_11 (0x1 << 16) +#define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */ + /* if GR18 indicates a display switch */ +#define SWF14_DS_PIPEB_LFP2_EN (1<<15) +#define SWF14_DS_PIPEB_EFP2_EN (1<<14) +#define SWF14_DS_PIPEB_TV2_EN (1<<13) +#define SWF14_DS_PIPEB_CRT2_EN (1<<12) +#define SWF14_DS_PIPEB_LFP_EN (1<<11) +#define SWF14_DS_PIPEB_EFP_EN (1<<10) +#define SWF14_DS_PIPEB_TV_EN (1<<9) +#define SWF14_DS_PIPEB_CRT_EN (1<<8) +#define SWF14_DS_PIPEA_LFP2_EN (1<<7) +#define SWF14_DS_PIPEA_EFP2_EN (1<<6) +#define SWF14_DS_PIPEA_TV2_EN (1<<5) +#define SWF14_DS_PIPEA_CRT2_EN (1<<4) +#define SWF14_DS_PIPEA_LFP_EN (1<<3) +#define SWF14_DS_PIPEA_EFP_EN (1<<2) +#define SWF14_DS_PIPEA_TV_EN (1<<1) +#define SWF14_DS_PIPEA_CRT_EN (1<<0) + /* if GR18 indicates a panel fitting request */ +#define SWF14_PFIT_EN (1<<0) /* 0 means disable */ + /* if GR18 indicates an APM change request */ +#define SWF14_APM_HIBERNATE 0x4 +#define SWF14_APM_SUSPEND 0x3 +#define SWF14_APM_STANDBY 0x1 +#define SWF14_APM_RESTORE 0x0 + +/* Add the device class for LFP, TV, HDMI */ +#define DEVICE_TYPE_INT_LFP 0x1022 +#define DEVICE_TYPE_INT_TV 0x1009 +#define DEVICE_TYPE_HDMI 0x60D2 +#define DEVICE_TYPE_DP 0x68C6 +#define DEVICE_TYPE_eDP 0x78C6 + +#define DEVICE_TYPE_CLASS_EXTENSION (1 << 15) +#define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14) +#define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13) +#define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12) +#define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11) +#define DEVICE_TYPE_MIPI_OUTPUT (1 << 10) +#define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9) +#define DEVICE_TYPE_DUAL_CHANNEL (1 << 8) +#define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6) +#define DEVICE_TYPE_LVDS_SINGALING (1 << 5) +#define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4) +#define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3) +#define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2) +#define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1) +#define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0) + +/* + * Bits we care about when checking for DEVICE_TYPE_eDP + * Depending on the system, the other bits may or may not + * be set for eDP outputs. + */ +#define DEVICE_TYPE_eDP_BITS \ + (DEVICE_TYPE_INTERNAL_CONNECTOR | \ + DEVICE_TYPE_NOT_HDMI_OUTPUT | \ + DEVICE_TYPE_MIPI_OUTPUT | \ + DEVICE_TYPE_COMPOSITE_OUTPUT | \ + DEVICE_TYPE_DUAL_CHANNEL | \ + DEVICE_TYPE_LVDS_SINGALING | \ + DEVICE_TYPE_TMDS_DVI_SIGNALING | \ + DEVICE_TYPE_VIDEO_SIGNALING | \ + DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ + DEVICE_TYPE_DIGITAL_OUTPUT | \ + DEVICE_TYPE_ANALOG_OUTPUT) + +/* define the DVO port for HDMI output type */ +#define DVO_B 1 +#define DVO_C 2 +#define DVO_D 3 + +/* define the PORT for DP output type */ +#define PORT_IDPB 7 +#define PORT_IDPC 8 +#define PORT_IDPD 9 + +/* Possible values for the "DVO Port" field for versions >= 155: */ +#define DVO_PORT_HDMIA 0 +#define DVO_PORT_HDMIB 1 +#define DVO_PORT_HDMIC 2 +#define DVO_PORT_HDMID 3 +#define DVO_PORT_LVDS 4 +#define DVO_PORT_TV 5 +#define DVO_PORT_CRT 6 +#define DVO_PORT_DPB 7 +#define DVO_PORT_DPC 8 +#define DVO_PORT_DPD 9 +#define DVO_PORT_DPA 10 + +/* MIPI DSI panel info */ +struct bdb_mipi { + u16 panel_id; + u16 bridge_revision; + + /* General params */ + u32 dithering:1; + u32 bpp_pixel_format:1; + u32 rsvd1:1; + u32 dphy_valid:1; + u32 resvd2:28; + + u16 port_info; + u16 rsvd3:2; + u16 num_lanes:2; + u16 rsvd4:12; + + /* DSI config */ + u16 virt_ch_num:2; + u16 vtm:2; + u16 rsvd5:12; + + u32 dsi_clock; + u32 bridge_ref_clk; + u16 rsvd_pwr; + + /* Dphy Params */ + u32 prepare_cnt:5; + u32 rsvd6:3; + u32 clk_zero_cnt:8; + u32 trail_cnt:5; + u32 rsvd7:3; + u32 exit_zero_cnt:6; + u32 rsvd8:2; + + u32 hl_switch_cnt; + u32 lp_byte_clk; + u32 clk_lane_switch_cnt; +} __attribute__((packed)); + +#endif /* _I830_BIOS_H_ */ diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index 1f53a74..2a03054 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -26,13 +26,64 @@ #include <drivers/intel/gma/edid.h> #include <drivers/intel/gma/i915.h> +#include <drivers/intel/gma/intel_bios.h> #include "gma.h" #include "chip.h" #include <pc80/vga.h> #include <pc80/vga_io.h> +#include <device/pci_def.h> +#include <device/pci_rom.h> #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) +static size_t generate_vbt(const struct northbridge_intel_sandybridge_config *conf, + void *vbt) +{ + struct vbt_header *head = vbt; + struct bdb_header *bdb_head; + struct bdb_general_features *genfeat; + u8 *ptr; + + memset(head, 0, sizeof (*head)); + + memcpy(head->signature, "$VBT SNB/IVB-MOBILE ", 20); + head->version = 100; + head->header_size = sizeof (*head); + head->bdb_offset = sizeof (*head); + + bdb_head = (struct bdb_header *) (head + 1); + memset(bdb_head, 0, sizeof (*bdb_head)); + memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); + bdb_head->version = 0xa8; + bdb_head->header_size = sizeof (*bdb_head); + + ptr = (u8 *) (bdb_head + 1); + + ptr[0] = BDB_GENERAL_FEATURES; + ptr[1] = sizeof (*genfeat); + ptr[2] = sizeof (*genfeat) >> 8; + ptr += 3; + + genfeat = (struct bdb_general_features *) ptr; + memset(genfeat, 0, sizeof (*genfeat)); + genfeat->panel_fitting = 3; + genfeat->flexaim = 1; + genfeat->download_ext_vbt = 1; + genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock; + genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz; + genfeat->rsvd10 = 0x4; + genfeat->legacy_monitor_detect = 1; + genfeat->int_crt_support = 1; + genfeat->dp_ssc_enb = 1; + + ptr += sizeof (*genfeat); + + bdb_head->bdb_size = ptr - (u8 *)bdb_head; + head->vbt_size = ptr - (u8 *)head; + head->vbt_checksum = 0; + return ptr - (u8 *)head; +} + static void link_train(u32 mmio) { write32(mmio+0xf000c,0x40); @@ -509,6 +560,39 @@ int i915lightup(const struct northbridge_intel_sandybridge_config *info, memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4); set_vbe_mode_info_valid(&edid, lfb); #endif + + /* Linux relies on VBT for panel info. */ + if (read16(PCI_VGA_RAM_IMAGE_START) != OPROM_SIGNATURE) { + optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; + optionrom_pcir_t *pcir; + size_t vbt_size; + size_t fake_oprom_size; + struct device *dev; + + dev = dev_find_slot(0, PCI_DEVFN(2, 0)); + + memset(oh, 0, 8192); + + oh->signature = OPROM_SIGNATURE; + oh->pcir_offset = 0x40; + oh->vbt_offset = 0x80; + + pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40); + pcir->signature = 0x52494350; // PCIR + pcir->vendor = dev->vendor; + pcir->device = dev->device; + pcir->length = sizeof(*pcir); + pcir->revision = dev->class; + pcir->classcode[0] = dev->class >> 8; + pcir->classcode[1] = dev->class >> 16; + pcir->classcode[2] = dev->class >> 24; + pcir->indicator = 0x80; + + vbt_size = generate_vbt (info, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80)); + fake_oprom_size = (0x80 + vbt_size + 511) / 512; + oh->size = fake_oprom_size; + pcir->imagelength = fake_oprom_size; + } return 1; }

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coreboot-gerrit June 2014