coreboot-gerrit June 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 08cbd53 lenovo/x60/i915.c: Use `FRAME_BUFFER_PAGES` in `set_gtt()`
by Paul Menzel 08 Jun '14

08 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5938 -gerrit commit 08cbd532e4698ae875dadc1a874aecf3c08b7e63 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 21:36:18 2014 +0200 lenovo/x60/i915.c: Use `FRAME_BUFFER_PAGES` in `set_gtt()` The define FRAME_BUFFER_PAGES = (1024 * 768)/1024 is exactly the amount of needed pages. Change-Id: Ifae2a50080b0fbcdd0d3489c8da1535cbbb05eef Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 328b0cb..831f469 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -352,7 +352,7 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, return 0; } - setgtt(0, 800, physbase, 4096); + setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096); temp = READ32(PGETBL_CTL); printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp);

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Patch set updated for coreboot: 85c5907 [NOTFORMERGE] lenovo/x60/Kconfig: Select native graphics init
by Paul Menzel 08 Jun '14

08 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5957 -gerrit commit 85c5907c356500e98a0c1033737ec5afaaef9b32 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Jun 7 21:50:21 2014 +0200 [NOTFORMERGE] lenovo/x60/Kconfig: Select native graphics init Just for build testing the native graphics patches. Change-Id: I47ed328ce8ce3516ad3997978a01d2359d9b1ca8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 5abb14c..2d7a933 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select USE_OPTION_TABLE select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_DO_NATIVE_VGA_INIT select EARLY_CBMEM_INIT select H8_DOCK_EARLY_INIT

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Patch set updated for coreboot: 81317b6 lenovo/x60/i915.c: Fix coding style and embellish log messages
by Paul Menzel 08 Jun '14

08 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5937 -gerrit commit 81317b6351c61e86c45cc265e37a06bda1798ba1 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 21:29:13 2014 +0200 lenovo/x60/i915.c: Fix coding style and embellish log messages Change-Id: I4227832dba439469f738f7894e1c73e2a5bd5e7a Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 95b836a..328b0cb 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -348,19 +348,19 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, */ if (gtt_setup(pmmio)) { - printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n"); + printk(BIOS_ERR, "ERROR: GTT setup failed!!!\n"); return 0; } - setgtt(0, 800 , physbase, 4096); + setgtt(0, 800, physbase, 4096); temp = READ32(PGETBL_CTL); printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp); if (temp & 1) - printk(BIOS_INFO, "GTT Enabled\n"); + printk(BIOS_INFO, "GTT enabled.\n"); else - printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n"); + printk(BIOS_ERR, "ERROR: GTT is still disabled!!!\n"); printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", (void *)graphics, FRAME_BUFFER_BYTES);

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Patch set updated for coreboot: bcad4dc lenovo/x60: Fix build issue with DO_NATIVE_VGA_INIT
by Paul Menzel 08 Jun '14

08 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5893 -gerrit commit bcad4dcd79ddb64f794e30d5ed3b80ba0c507bcc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat May 31 17:08:40 2014 +0300 lenovo/x60: Fix build issue with DO_NATIVE_VGA_INIT Use the value from hardware for uma_memory_base. Change-Id: I70351166db6634ef3bca2bf12051ccc3730cab8e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/northbridge/intel/i945/gma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 1cf80a9..2197186 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -64,6 +64,7 @@ static void gma_func0_init(struct device *dev) ); int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); + u32 uma_memory_base = pci_read_config32(dev, BSM) & ~((1 << 20) - 1); int lightup_ok = i915lightup(uma_memory_base, iobase, mmiobase, graphics_base); if (lightup_ok) gfx_set_init_done(1);

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Patch set updated for coreboot: aee779e lenovo/x60/i915.c: Place GTT below top of memory
by Paul Menzel 08 Jun '14

08 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5927 -gerrit commit aee779ef4cedb1546b597460b557b6e8264f1e3e Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 22:45:35 2014 +0200 lenovo/x60/i915.c: Place GTT below top of memory PGETBL_CTL differs between Video BIOS (-) and native graphics init (+). - PGETBL_CTL: 0x3ffc0001 + PGETBL_CTL: 0x3f800001 Currently it is set above the base address of stolen memory. The Video BIOS sets it below. The Linux Intel driver expects it to be below top of memory so do it this way. Using the GTT address in `setgtt` instead of `physbase` setgtt(0, FRAME_BUFFER_PAGES, temp & 0xfffff000, 4096); causes corruptions in GRUB. There is still an error thrown but 3D works with Linux 3.12+. Change-Id: I0a5b04c2c5300f5056cb48075aa5804984bc9948 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 14 +++++++++++--- src/mainboard/lenovo/x60/i915_reg.h | 2 ++ 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 43efb08..d25d66f 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -139,11 +139,19 @@ int gtt_setup(unsigned int mmiobase); int gtt_setup(unsigned int mmiobase) { unsigned long pgetbl_ctl; + unsigned long tom; pgetbl_ctl = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; pgetbl_ctl |= PGETBL_ENABLED; - pgetbl_ctl |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfff00000; + /* The Video BIOS places the GTT right below top of memory. + * It is not documented in the datasheet, but the Intel developers said + * that it is normally placed there. + * + * TODO: Add option table value to make the GTT size runtime configurable. + */ + tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24; + pgetbl_ctl |= tom - 256 * KiB; pgetbl_ctl |= PGETBL_GTT_SIZE_256KB << 1; /* set GTT to 256kb */ write32(mmiobase + GFX_FLSH_CNTL, 0); @@ -359,11 +367,11 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, return 0; } - setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096); - temp = READ32(PGETBL_CTL); printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp); + setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096); + if (temp & 1) printk(BIOS_INFO, "GTT enabled.\n"); else diff --git a/src/mainboard/lenovo/x60/i915_reg.h b/src/mainboard/lenovo/x60/i915_reg.h index 382b822..a12ba55 100644 --- a/src/mainboard/lenovo/x60/i915_reg.h +++ b/src/mainboard/lenovo/x60/i915_reg.h @@ -27,6 +27,8 @@ #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) +#define TOLUD 0x9c + /* * The Bridge device's PCI config space has information about the * fb aperture size and the amount of pre-reserved memory.

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Patch set updated for coreboot: ab4bc2b lenovo/x60/i915.c: Add defines for GTT sizes and use them
by Paul Menzel 08 Jun '14

08 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5940 -gerrit commit ab4bc2b3196f10cdeb641a47511e6f66abcac442 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 22:22:24 2014 +0200 lenovo/x60/i915.c: Add defines for GTT sizes and use them Change-Id: Ia0de8802c6f48eefe1d48e30b5bc07290a407667 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index e96eaf9..43efb08 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -58,6 +58,13 @@ static unsigned int physbase; #define PGETBL_CTL 0x2020 #define PGETBL_ENABLED 0x00000001 +#define PGETBL_GTT_SIZE 0x00001110 +#define PGETBL_GTT_SIZE_512KB 0x0 +#define PGETBL_GTT_SIZE_256KB 0x1 +#define PGETBL_GTT_SIZE_128KB 0x2 +#define PGETBL_GTT_SIZE_1MB 0x3 +#define PGETBL_GTT_SIZE_2MB 0x4 +#define PGETBL_GTT_SIZE_1_5MB 0x5 static u32 htotal, hblank, hsync, vtotal, vblank, vsync; @@ -137,7 +144,7 @@ int gtt_setup(unsigned int mmiobase) pgetbl_ctl |= PGETBL_ENABLED; pgetbl_ctl |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfff00000; - pgetbl_ctl |= 2; /* set GTT to 256kb */ + pgetbl_ctl |= PGETBL_GTT_SIZE_256KB << 1; /* set GTT to 256kb */ write32(mmiobase + GFX_FLSH_CNTL, 0);

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Patch set updated for coreboot: 2b5b63c lenovo/x60/i915.c: Remove `PGETLB_CTL` define with typo in name
by Paul Menzel 08 Jun '14

08 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5930 -gerrit commit 2b5b63c45068aa380dde00bf53105eb67f66e6c7 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 09:04:40 2014 +0200 lenovo/x60/i915.c: Remove `PGETLB_CTL` define with typo in name Currently there are the two defines `PGETBL_CTL` and `PGETLB_CTL`. Use the one using TBL as the abbreviation for *table* and which is the name used in the Intel 965 datasheet. [1] https://01.org/linuxgraphics/sites/default/files/documentation/965_g35_vol_… Intel ® 965 Express Chipset Family and Intel ® G35 Express Chipset Graphics Controller Programmer’s Reference Manual Volume 1: Graphics Core Revision 1.0a Change-Id: I459c2576d91e80accaae313b34875cc7b8c446ad Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 8fbd2a1..6e67bff 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -48,8 +48,6 @@ enum { vmsg = 1, vio = 2, vspin = 4, }; -#define PGETLB_CTL 0x2020 - static int verbose = 0; static unsigned int *mmio; @@ -353,8 +351,8 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, setgtt(0, 800 , physbase, 4096); - temp = READ32(PGETLB_CTL); - printk(BIOS_INFO, "GTT PGETLB_CTL register: 0x%lx\n", temp); + temp = READ32(PGETBL_CTL); + printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp); if (temp & 1) printk(BIOS_INFO, "GTT Enabled\n");

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Patch set updated for coreboot: 0d01062 Intel 945 boards: romstage.c: Use define for `BSM`
by Paul Menzel 08 Jun '14

08 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5929 -gerrit commit 0d01062539b12be1aa7a8c3368e65991a0b0c9fc Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 08:50:17 2014 +0200 Intel 945 boards: romstage.c: Use define for `BSM` Change-Id: Ia58d8b410a145f27f0b267c115714580c366e063 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/getac/p470/romstage.c | 2 +- src/mainboard/ibase/mb899/romstage.c | 2 +- src/mainboard/intel/d945gclf/romstage.c | 2 +- src/mainboard/kontron/986lcd-m/romstage.c | 2 +- src/mainboard/lenovo/t60/romstage.c | 2 +- src/mainboard/lenovo/x60/romstage.c | 2 +- src/mainboard/roda/rk886ex/romstage.c | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index a081a8a..33b6726 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -347,7 +347,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 418b6e4..9dfd364 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -298,7 +298,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 69d4232..a0621ce 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -258,7 +258,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 4acd734..0ad7a2a 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -410,7 +410,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index dae917c..c5bb2f3 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -309,7 +309,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 1198fb2..1fed5f5 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -311,7 +311,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index ad323f5..2af294c 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -334,7 +334,7 @@ void main(unsigned long bist) { /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + u32 tom = pci_read_config32(PCI_DEV(0,2,0), BSM); printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000);

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Patch set updated for coreboot: e69a4e1 lenovo/x60/i915.c: Log `PGETBL_CTL` programming
by Paul Menzel 08 Jun '14

08 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5934 -gerrit commit e69a4e11fce01a088b98348bbadd225be930e9a7 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 09:38:39 2014 +0200 lenovo/x60/i915.c: Log `PGETBL_CTL` programming Correctly setting up `PGETBL_CTL` is essential for the operating system driver to work correctly. Therefore log it more verbosely. Change-Id: I9b3dfa52f91c13e768c2ef980e5871173a85fcfe Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 016217f..95b836a 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -141,13 +141,16 @@ int gtt_setup(unsigned int mmiobase) write32(mmiobase + GFX_FLSH_CNTL, 0); + printk(BIOS_DEBUG, "%s: Write %lx to PGETBL_CTL ...", __func__, pgetbl_ctl); write32(mmiobase + PGETBL_CTL, pgetbl_ctl); /* verify */ - if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) { - printk(BIOS_DEBUG, "gtt_setup is enabled.\n"); + pgetbl_ctl = read32(mmiobase + PGETBL_CTL); + printk(BIOS_DEBUG, " read back %lx ...", pgetbl_ctl); + if (pgetbl_ctl & PGETBL_ENABLED) { + printk(BIOS_DEBUG, " GM mappings enabled ... GTT setup successful.\n"); } else { - printk(BIOS_DEBUG, "gtt_setup failed!!!\n"); + printk(BIOS_DEBUG, " GM mappings disabled ... GTT setup failed.\n"); return 1; } write32(mmiobase + GFX_FLSH_CNTL, 0);

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Patch set updated for coreboot: e4019bd lenovo/x60/i915.c: Use define for `BSM`
by Paul Menzel 08 Jun '14

08 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5932 -gerrit commit e4019bda927df8a59bdbce22c6a9065d14940dc2 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 08:50:17 2014 +0200 lenovo/x60/i915.c: Use define for `BSM` Although it builds without any further changes, including the header src/northbridge/intel/i945/i945.h where `BSM` is defined, would be useful. Unfortunately that conflicts with the already included header `southbridge/intel/bd82x6x/pch.h`, so it is left as is. Change-Id: I7c0a795338c34038169e082446907987364a0e88 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index b41a0ba..8fbd2a1 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -138,7 +138,7 @@ int gtt_setup(unsigned int mmiobase) PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; PGETBL_save |= PGETBL_ENABLED; - PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000; + PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfffff000; PGETBL_save |= 2; /* set GTT to 256kb */ write32(mmiobase + GFX_FLSH_CNTL, 0);

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coreboot-gerrit June 2014