coreboot-gerrit June 2014

coreboot-gerrit@coreboot.org

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922 discussions

Patch set updated for coreboot: 33ab4a7 lenovo/x60/i915.c: Rename variable `PGETBL_save` to `pgetbl_ctl`
by Paul Menzel 08 Jun '14

08 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5933 -gerrit commit 33ab4a77db87fee47327a96d17165bde3fd07bc1 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 09:41:06 2014 +0200 lenovo/x60/i915.c: Rename variable `PGETBL_save` to `pgetbl_ctl` The name was taken from the function `intel_gtt_init()` in `drivers/char/agp/intel-gtt.c` in the Linux kernel. It is used differently here `gtt_setup()`, so rename it. Change-Id: I16896fc9383a5e40992a24fa096fd373db66e436 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 6e67bff..016217f 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -131,17 +131,17 @@ setgtt(int start, int end, unsigned long base, int inc) int gtt_setup(unsigned int mmiobase); int gtt_setup(unsigned int mmiobase) { - unsigned long PGETBL_save; + unsigned long pgetbl_ctl; - PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; - PGETBL_save |= PGETBL_ENABLED; + pgetbl_ctl = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; + pgetbl_ctl |= PGETBL_ENABLED; - PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfffff000; - PGETBL_save |= 2; /* set GTT to 256kb */ + pgetbl_ctl |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfffff000; + pgetbl_ctl |= 2; /* set GTT to 256kb */ write32(mmiobase + GFX_FLSH_CNTL, 0); - write32(mmiobase + PGETBL_CTL, PGETBL_save); + write32(mmiobase + PGETBL_CTL, pgetbl_ctl); /* verify */ if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) {

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New patch to review for coreboot: 03a90a9 Makefile.inc: Only include SeaBIOS config files when SeaBIOS payload is selected
by Paul Menzel 07 Jun '14

07 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5958 -gerrit commit 03a90a932883e0db6e581d70b60b08119098d985 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Jun 7 22:35:18 2014 +0200 Makefile.inc: Only include SeaBIOS config files when SeaBIOS payload is selected Currently, building a board selecting `SEABIOS_PS2_TIMEOUT` in its Kconfig file, the SeaBIOS config file `etc/ps2-keyboard-spinup` is included in CBFS even if no payload or another payload than SeaBIOS is chosen. […] PAYLOAD none (as specified by user) SeaBIOS Wait up to 3000 ms for PS/2 keyboard controller initialization CONFIG .config CBFSPRINT coreboot.rom coreboot.rom: 2048 kB, bootblocksize 1424, romsize 2097152, offset 0x0 alignment: 64 bytes Name Offset Type Size cmos_layout.bin 0x0 cmos_layout 1828 cmos.default 0x780 cmos_default 256 cpu_microcode_blob.bin 0x8c0 microcode 94208 etc/ps2-keyboard-spinup 0x17900 raw 8 […] So add guards to only add the SeaBIOS config file, when SeaBIOS is selected as the payload during build. Change-Id: Ib770c9148285963db8056c1cc9fd7435630f2782 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index b9a3fe9..ed18e29 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -509,12 +509,14 @@ ifneq ($(CONFIG_PAYLOAD_FILE),) @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) $(ADDITIONAL_PAYLOAD_CONFIG) endif +ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup endif endif +endif ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) @printf " CONFIG $(DOTCONFIG)\n" if [ -f $(DOTCONFIG) ]; then \

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New patch to review for coreboot: 3102a17 [NOTFORMERGE] lenovo/x60/Kconfig: Select native graphics init
by Paul Menzel 07 Jun '14

07 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5957 -gerrit commit 3102a177b2cf5ad972e5ef30573db23930d97fbe Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Jun 7 21:50:21 2014 +0200 [NOTFORMERGE] lenovo/x60/Kconfig: Select native graphics init Just for build testing the native graphics patches. Change-Id: I47ed328ce8ce3516ad3997978a01d2359d9b1ca8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 5abb14c..2d7a933 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select USE_OPTION_TABLE select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_DO_NATIVE_VGA_INIT select EARLY_CBMEM_INIT select H8_DOCK_EARLY_INIT

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Patch set updated for coreboot: e7da7d5 lenovo/x60/i915.c: Mask BSM register correctly
by Paul Menzel 07 Jun '14

07 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5939 -gerrit commit e7da7d5f10789f2862f829d1239a632c9a06f962 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 22:27:24 2014 +0200 lenovo/x60/i915.c: Mask BSM register correctly Base of Stolen Memory are (BSM) are bits 31:20. This does make any difference as the bits 19:0 are read only and 0 by default. Change-Id: I82d087184a8550e95dca2ac2991ed48b06031536 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 831f469..e96eaf9 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -136,7 +136,7 @@ int gtt_setup(unsigned int mmiobase) pgetbl_ctl = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; pgetbl_ctl |= PGETBL_ENABLED; - pgetbl_ctl |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfffff000; + pgetbl_ctl |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfff00000; pgetbl_ctl |= 2; /* set GTT to 256kb */ write32(mmiobase + GFX_FLSH_CNTL, 0);

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Patch set updated for coreboot: 60b6015 lenovo/x60/i915.c: Use `FRAME_BUFFER_PAGES` in `set_gtt()`
by Paul Menzel 07 Jun '14

07 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5938 -gerrit commit 60b60159bc9b7a95e5a243c5c51f67be5579ad18 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 21:36:18 2014 +0200 lenovo/x60/i915.c: Use `FRAME_BUFFER_PAGES` in `set_gtt()` The define FRAME_BUFFER_PAGES = (1024 * 768)/1024 is exactly the amount of needed pages. Change-Id: Ifae2a50080b0fbcdd0d3489c8da1535cbbb05eef Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 328b0cb..831f469 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -352,7 +352,7 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, return 0; } - setgtt(0, 800, physbase, 4096); + setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096); temp = READ32(PGETBL_CTL); printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp);

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Patch set updated for coreboot: 985b27d lenovo/x60/i915.c: Fix coding style and embellish log messages
by Paul Menzel 07 Jun '14

07 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5937 -gerrit commit 985b27d3e4c09fd0f68f9f5b5c47a9781deefd13 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 21:29:13 2014 +0200 lenovo/x60/i915.c: Fix coding style and embellish log messages Change-Id: I4227832dba439469f738f7894e1c73e2a5bd5e7a Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 95b836a..328b0cb 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -348,19 +348,19 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, */ if (gtt_setup(pmmio)) { - printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n"); + printk(BIOS_ERR, "ERROR: GTT setup failed!!!\n"); return 0; } - setgtt(0, 800 , physbase, 4096); + setgtt(0, 800, physbase, 4096); temp = READ32(PGETBL_CTL); printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp); if (temp & 1) - printk(BIOS_INFO, "GTT Enabled\n"); + printk(BIOS_INFO, "GTT enabled.\n"); else - printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n"); + printk(BIOS_ERR, "ERROR: GTT is still disabled!!!\n"); printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", (void *)graphics, FRAME_BUFFER_BYTES);

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Patch set updated for coreboot: 9e632c6 lenovo/x60: Fix build issue with DO_NATIVE_VGA_INIT
by Paul Menzel 07 Jun '14

07 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5893 -gerrit commit 9e632c62cd6fcba96d74252bd9a17a12823fd4d1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat May 31 17:08:40 2014 +0300 lenovo/x60: Fix build issue with DO_NATIVE_VGA_INIT Use the value from hardware for uma_memory_base. Change-Id: I70351166db6634ef3bca2bf12051ccc3730cab8e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/i945/gma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 1cf80a9..0c45cb3 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -64,6 +64,7 @@ static void gma_func0_init(struct device *dev) ); int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); + u32 uma_memory_base = pci_read_config32(dev, BSM) & ~((1<<20) - 1); int lightup_ok = i915lightup(uma_memory_base, iobase, mmiobase, graphics_base); if (lightup_ok) gfx_set_init_done(1);

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Patch set updated for coreboot: b91bb1b lenovo/x60/i915.c: Place GTT below top of memory
by Paul Menzel 07 Jun '14

07 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5927 -gerrit commit b91bb1bc4f92444b687eaedeb9fcc11093c78f34 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 22:45:35 2014 +0200 lenovo/x60/i915.c: Place GTT below top of memory PGETBL_CTL differs between Video BIOS (-) and native graphics init (+). - PGETBL_CTL: 0x3ffc0001 + PGETBL_CTL: 0x3f800001 Currently it is set above the base address of stolen memory. The Video BIOS sets it below. The Linux Intel driver expects it to be below top of memory so do it this way. Also adapt setgtt() to use the new address. There is still an error thrown but 3D works with Linux 3.12+. Change-Id: I0a5b04c2c5300f5056cb48075aa5804984bc9948 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 14 +++++++++++--- src/mainboard/lenovo/x60/i915_reg.h | 2 ++ 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 43efb08..640dcda 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -139,11 +139,19 @@ int gtt_setup(unsigned int mmiobase); int gtt_setup(unsigned int mmiobase) { unsigned long pgetbl_ctl; + unsigned long tom; pgetbl_ctl = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; pgetbl_ctl |= PGETBL_ENABLED; - pgetbl_ctl |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfff00000; + /* The Video BIOS places the GTT right below top of memory. + * It is not documented in the datasheet, but the Intel developers said + * that it is normally placed there. + * + * TODO: Add option table value to make the GTT size runtime configurable. + */ + tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24; + pgetbl_ctl |= tom - 256 * KiB; pgetbl_ctl |= PGETBL_GTT_SIZE_256KB << 1; /* set GTT to 256kb */ write32(mmiobase + GFX_FLSH_CNTL, 0); @@ -359,11 +367,11 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, return 0; } - setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096); - temp = READ32(PGETBL_CTL); printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp); + setgtt(0, FRAME_BUFFER_PAGES, temp & 0xfffff000, 4096); + if (temp & 1) printk(BIOS_INFO, "GTT enabled.\n"); else diff --git a/src/mainboard/lenovo/x60/i915_reg.h b/src/mainboard/lenovo/x60/i915_reg.h index 382b822..a12ba55 100644 --- a/src/mainboard/lenovo/x60/i915_reg.h +++ b/src/mainboard/lenovo/x60/i915_reg.h @@ -27,6 +27,8 @@ #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) +#define TOLUD 0x9c + /* * The Bridge device's PCI config space has information about the * fb aperture size and the amount of pre-reserved memory.

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Patch set updated for coreboot: 2c5e666 lenovo/x60/i915.c: Add defines for GTT sizes and use them
by Paul Menzel 07 Jun '14

07 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5940 -gerrit commit 2c5e6660487c694eb7777dbd2d3f49b280228079 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 22:22:24 2014 +0200 lenovo/x60/i915.c: Add defines for GTT sizes and use them Change-Id: Ia0de8802c6f48eefe1d48e30b5bc07290a407667 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index e96eaf9..43efb08 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -58,6 +58,13 @@ static unsigned int physbase; #define PGETBL_CTL 0x2020 #define PGETBL_ENABLED 0x00000001 +#define PGETBL_GTT_SIZE 0x00001110 +#define PGETBL_GTT_SIZE_512KB 0x0 +#define PGETBL_GTT_SIZE_256KB 0x1 +#define PGETBL_GTT_SIZE_128KB 0x2 +#define PGETBL_GTT_SIZE_1MB 0x3 +#define PGETBL_GTT_SIZE_2MB 0x4 +#define PGETBL_GTT_SIZE_1_5MB 0x5 static u32 htotal, hblank, hsync, vtotal, vblank, vsync; @@ -137,7 +144,7 @@ int gtt_setup(unsigned int mmiobase) pgetbl_ctl |= PGETBL_ENABLED; pgetbl_ctl |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfff00000; - pgetbl_ctl |= 2; /* set GTT to 256kb */ + pgetbl_ctl |= PGETBL_GTT_SIZE_256KB << 1; /* set GTT to 256kb */ write32(mmiobase + GFX_FLSH_CNTL, 0);

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Patch set updated for coreboot: 0837d50 lenovo/x60/i915.c: Remove `PGETLB_CTL` define with typo in name
by Paul Menzel 07 Jun '14

07 Jun '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5930 -gerrit commit 0837d50c9292dcdbc5045f1edd714683a2f1a779 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Jun 5 09:04:40 2014 +0200 lenovo/x60/i915.c: Remove `PGETLB_CTL` define with typo in name Currently there are the two defines `PGETBL_CTL` and `PGETLB_CTL`. Use the one using TBL as the abbreviation for *table* and which is the name used in the Intel 965 datasheet. [1] https://01.org/linuxgraphics/sites/default/files/documentation/965_g35_vol_… Intel ® 965 Express Chipset Family and Intel ® G35 Express Chipset Graphics Controller Programmer’s Reference Manual Volume 1: Graphics Core Revision 1.0a Change-Id: I459c2576d91e80accaae313b34875cc7b8c446ad Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/lenovo/x60/i915.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 8fbd2a1..6e67bff 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -48,8 +48,6 @@ enum { vmsg = 1, vio = 2, vspin = 4, }; -#define PGETLB_CTL 0x2020 - static int verbose = 0; static unsigned int *mmio; @@ -353,8 +351,8 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, setgtt(0, 800 , physbase, 4096); - temp = READ32(PGETLB_CTL); - printk(BIOS_INFO, "GTT PGETLB_CTL register: 0x%lx\n", temp); + temp = READ32(PGETBL_CTL); + printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp); if (temp & 1) printk(BIOS_INFO, "GTT Enabled\n");

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coreboot-gerrit June 2014