coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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1066 discussions

New patch to review for coreboot: 38cccf0 drivers/intel/fsp: update enable_mrc_cache with fast boot
by Martin Roth 19 May '14

19 May '14

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5794 -gerrit commit 38cccf03aafcf3c59c2d78dcb4b7b89aeee073c3 Author: Martin Roth <gaumless(a)gmail.com> Date: Mon May 19 15:30:00 2014 -0600 drivers/intel/fsp: update enable_mrc_cache with fast boot When going from a configuration with fast boot disabled to one with it enabled, ENABLE_MRC_CACHE was not being enabled properly. This forces it on with ENABLE_FSP_FAST_BOOT. Change-Id: If7b6374e0c0a1d5403a50a1b0a958cea6f96cc88 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/drivers/intel/fsp/Kconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp/Kconfig b/src/drivers/intel/fsp/Kconfig index 3e16266..bde7312 100644 --- a/src/drivers/intel/fsp/Kconfig +++ b/src/drivers/intel/fsp/Kconfig @@ -30,6 +30,10 @@ config HAVE_FSP_BIN Note: Without this binary, coreboot builds relying on the FSP will not boot +config FSP_SPECIFIC_OPTIONS + def_bool y + select ENABLE_MRC_CACHE if ENABLE_FSP_FAST_BOOT + config DCACHE_RAM_BASE hex default 0xfef00000 @@ -62,7 +66,7 @@ config ENABLE_FSP_FAST_BOOT config ENABLE_MRC_CACHE bool - default ENABLE_FSP_FAST_BOOT + default n help Enabling this feature will cause MRC data to be cached in NV storage. This can either be used for fast boot, or just because the FSP wants

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New patch to review for coreboot: 579ee1a cpu/intel/fsp_model_206ax: change realpath to readlink
by Martin Roth 19 May '14

19 May '14

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5793 -gerrit commit 579ee1a579b1511e46ef5c000db6e227ca254f7c Author: Martin Roth <gaumless(a)gmail.com> Date: Mon May 19 15:28:00 2014 -0600 cpu/intel/fsp_model_206ax: change realpath to readlink realpath and readlink can be used to do the same thing - in this case we're turning path1/path2/../path3/path4 into path1/path3/path4 so that the makefile's wildcard routine can evaluate it. Debian derivitaves don't seem to include realpath. Change-Id: I0a80a1d9b563810bdf96aea9d5de79ce1cea457a Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/cpu/intel/fsp_model_206ax/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc index c6d7339..cb7f2a8 100644 --- a/src/cpu/intel/fsp_model_206ax/Makefile.inc +++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc @@ -8,7 +8,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),) -ifneq ($(wildcard $(shell realpath -L "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),) +ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),) CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH) endif endif

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Patch set updated for coreboot: 9e7ddf2 device_romstage: Add a way to move to the next device
by Martin Roth 19 May '14

19 May '14

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5732 -gerrit commit 9e7ddf28ce72b4fb0700eed8e08fbf8b05cfbd18 Author: Martin Roth <gaumless(a)gmail.com> Date: Mon May 12 17:38:59 2014 -0600 device_romstage: Add a way to move to the next device When trying to loop through all the devices in romstage, there was no function to just go from one to the next. This allows an easy way to go all the way down the chain of devices. Change-Id: Id205b24610d75de060b0d48fa283a2ab92d1df0a Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/device/device_romstage.c | 24 ++++++++++++++++++++++++ src/include/device/device.h | 2 ++ 2 files changed, 26 insertions(+) diff --git a/src/device/device_romstage.c b/src/device/device_romstage.c index 591cf88..6dcf6d2 100644 --- a/src/device/device_romstage.c +++ b/src/device/device_romstage.c @@ -55,6 +55,30 @@ ROMSTAGE_CONST struct device *dev_find_slot(unsigned int bus, } /** + * Given a device pointer, find the next PCI device. + * + * @param previous_dev A pointer to a PCI device structure. + * @return Pointer to the next device structure (if found), 0 otherwise. + */ +ROMSTAGE_CONST struct device *dev_find_next_pci_device( + ROMSTAGE_CONST struct device *previous_dev) +{ + ROMSTAGE_CONST struct device *dev, *result; + + if (previous_dev == NULL) + previous_dev = all_devices; + + result = 0; + for (dev = previous_dev->next; dev; dev = dev->next) { + if (dev->path.type == DEVICE_PATH_PCI) { + result = dev; + break; + } + } + return result; +} + +/** * Given an SMBus bus and a device number, find the device structure. * * @param bus The bus number. diff --git a/src/include/device/device.h b/src/include/device/device.h index a4ef456..dcd93f6 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -236,6 +236,8 @@ u32 find_pci_tolm(struct bus *bus); ROMSTAGE_CONST struct device * dev_find_slot (unsigned int bus, unsigned int devfn); +ROMSTAGE_CONST struct device *dev_find_next_pci_device( + ROMSTAGE_CONST struct device *previous_dev); ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus, unsigned int addr);

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Patch set updated for coreboot: 3e9565b PCI IRQs: Swizzle PCI IRQs for PCI bridges
by Martin Roth 19 May '14

19 May '14

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5734 -gerrit commit 3e9565b95fcf27db5c691e7a0ad35f884dbfce75 Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Mon May 12 21:46:31 2014 -0600 PCI IRQs: Swizzle PCI IRQs for PCI bridges The PCI Specification states that devices that implement a bridge and a secondary bus must swizzle (rotate) the interrupt pins according to the table below: Child Dev # Child PIN Parent PIN 0,4,8,12... A/B/C/D A/B/C/D 1,5,9,13... A/B/C/D B/C/D/A 2,6,10,14.. A/B/C/D C/D/A/B 3,7,11,15.. A/B/C/D D/A/B/C Which is also described by this equation: PIN_parent = (Pin_child + Dev_child) % 4 When a device is found and its bus number is greater than 0, it is on a bridge and needs to be swizzled. Following the string of parents up to the root bus and swizzling as we go gives us the desired swizzling result. When BIOS_SPEW is defined, it will print out each step of the swizzling process. Change-Id: Icafeadd01983282c86e25f560c831c9482c74e68 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/device/pci_device.c | 150 +++++++++++++++++++++++++++++++++++++++++++++++ src/include/device/pci.h | 2 + 2 files changed, 152 insertions(+) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index f09fcaa..d80225f 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1303,6 +1303,156 @@ unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) return max; } +/** + * Take an INT_PIN number (0, 1 - 4) and convert + * it to a string ("NO PIN", "PIN A" - "PIN D") + * + * @param pin PCI Interrupt Pin number (0, 1 - 4) + * @return A string corresponding to the pin number or "Invalid" + */ +const char *pin_to_str(int pin) +{ + const char *str[5] = { + "NO PIN", + "PIN A", + "PIN B", + "PIN C", + "PIN D", + }; + + if (pin >= 0 || pin <= 4) + return str[pin]; + else + return "Invalid PIN, not 0 - 4"; +} + +/** + * Get the PCI INT_PIN swizzle for a device defined as: + * pin_parent = (pin_child + devn_child) % 4 + 1 + * where PIN A = 1 ... PIN_D = 4 + * + * Given a PCI device structure 'dev', find the interrupt pin + * that will be triggered on its parent bridge device when + * generating an interrupt. For example: Device 1:3.2 may + * use INT_PIN A but will trigger PIN D on its parent bridge + * device. In this case, this function will return 4 (PIN D). + * + * @param dev A PCI device structure to swizzle interrupt pins for + * @param *parent_bdg The PCI device structure for the bridge + * device 'dev' is attached to + * @return The interrupt pin number (1 - 4) that 'dev' will + * trigger when generating an interrupt + */ +static int swizzle_irq_pins(device_t dev, device_t *parent_bridge) +{ + device_t parent; /* Our current device's parent device */ + device_t child; /* The child device of the parent */ + int parent_bus = 0; /* Parent Bus number */ + int parent_devfn = 0; /* Parent Device and Function number */ + int child_devfn = 0; /* Child Device and Function number */ + int swizzled_pin = 0; /* Pin swizzled across a bridge */ + + /* Start with PIN A = 0 ... D = 3 */ + swizzled_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN) - 1; + + /* While our current device has parent devices */ + child = dev; + for (parent = child->bus->dev; parent; parent = parent->bus->dev) { + parent_bus = parent->bus->secondary; + parent_devfn = parent->path.pci.devfn; + child_devfn = child->path.pci.devfn; + + /* Swizzle the INT_PIN for any bridges not on root bus */ + swizzled_pin = (PCI_SLOT(child_devfn) + swizzled_pin) % 4; + printk(BIOS_SPEW, "\tWith INT_PIN swizzled to %s\n" + "\tAttached to bridge device %01X:%02Xh.%02Xh\n", + pin_to_str(swizzled_pin + 1), parent_bus, + PCI_SLOT(parent_devfn), PCI_FUNC(parent_devfn)); + + /* Continue until we find the root bus */ + if (parent_bus > 0) { + /* + * We will go on to the next parent so this parent + * becomes the child + */ + child = parent; + continue; + } else { + /* + * Found the root bridge device, + * fill in the structure and exit + */ + *parent_bridge = parent; + break; + } + } + + /* End with PIN A = 1 ... D = 4 */ + return swizzled_pin + 1; +} + +/** + * Given a device structure 'dev', find its interrupt pin + * and its parent bridge 'parent_bdg' device structure. + * If it is behind a bridge, it will return the interrupt + * pin number (1 - 4) of the parent bridge that the device + * interrupt pin has been swizzled to, otherwise it will + * return the interrupt pin that is programmed into the + * PCI config space of the target device. If 'dev' is + * behind a bridge, it will fill in 'parent_bdg' with the + * device structure of the bridge it is behind, otherwise + * it will copy 'dev' into 'parent_bdg'. + * + * @param dev A PCI device structure to get interrupt pins for. + * @param *parent_bdg The PCI device structure for the bridge + * device 'dev' is attached to. + * @return The interrupt pin number (1 - 4) that 'dev' will + * trigger when generating an interrupt. + * Errors: -1 is returned if the device is not enabled + * -2 is returned if a parent bridge could not be found. + */ +int get_irq_pins(device_t dev, device_t *parent_bdg) +{ + int bus = 0; /* The bus this device is on */ + int devfn = 0; /* This device's device and function numbers */ + int int_pin = 0; /* Interrupt pin used by the device */ + int target_pin = 0; /* Interrupt pin we want to assign an IRQ to */ + + bus = dev->bus->secondary; + devfn = dev->path.pci.devfn; + + /* Make sure this device is enabled */ + if (!(dev->enabled && (dev->path.type == DEVICE_PATH_PCI))) + return -1; + + /* Get and validate the interrupt pin used. Only 1-4 are allowed */ + int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); + if (int_pin < 1 || int_pin > 4) + return -1; + + printk(BIOS_SPEW, "PCI IRQ: Found device %01X:%02Xh.%02Xh using %s\n", + bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pin_to_str(int_pin)); + + /* If this device is on a bridge, swizzle its INT_PIN */ + if (bus) { + /* Swizzle its INT_PINs */ + target_pin = swizzle_irq_pins(dev, parent_bdg); + + /* Make sure the swizzle returned valid structures */ + if (parent_bdg == NULL) { + printk(BIOS_WARNING, + "Warning: Could not find parent bridge for this device!\n"); + return -2; + } + } else { /* Device is not behind a bridge */ + target_pin = int_pin; /* Return its own interrupt pin */ + *parent_bdg = dev; /* Return its own structure */ + } + + /* Target pin is the interrupt pin we want to assign an IRQ to */ + return target_pin; +} + #if CONFIG_PC80_SYSTEM /** * Assign IRQ numbers. diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 5594d29..ee9e84d 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -82,6 +82,8 @@ void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device); void pci_dev_init(struct device *dev); unsigned int pci_match_simple_dev(device_t dev, pci_devfn_t sdev); +const char * pin_to_str(int pin); +int get_irq_pins(device_t dev, device_t *parent_bdg); void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]);

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Patch set updated for coreboot: 27e6c1b add rtc_init() to romstage
by Martin Roth 19 May '14

19 May '14

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5735 -gerrit commit 27e6c1b3ced2f43b13d7cb232dcaf94c4e11fade Author: Martin Roth <gaumless(a)gmail.com> Date: Mon May 12 21:52:54 2014 -0600 add rtc_init() to romstage The FSP clears the bit that tells us whether or not the RTC has lost power when it sets up memory. Because of this, we need to initialize the RTC in romstage instead of ramstage. Change-Id: I158e4339fc539d32cfb2428042df6156d312a5f4 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/drivers/pc80/Kconfig | 6 ++++++ src/drivers/pc80/Makefile.inc | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/src/drivers/pc80/Kconfig b/src/drivers/pc80/Kconfig index 1348dd4..6fb379d 100644 --- a/src/drivers/pc80/Kconfig +++ b/src/drivers/pc80/Kconfig @@ -23,3 +23,9 @@ config TPM Enable this option to enable TPM support in coreboot. If unsure, say N. + +config ROMSTAGE_RTC_INIT + bool + default n + help + Enable this option to use rtc_init() in romstage diff --git a/src/drivers/pc80/Makefile.inc b/src/drivers/pc80/Makefile.inc index 4d0a280..cf62132 100644 --- a/src/drivers/pc80/Makefile.inc +++ b/src/drivers/pc80/Makefile.inc @@ -1,4 +1,8 @@ +ifeq ($(CONFIG_ROMSTAGE_RTC_INIT),) ramstage-y += mc146818rtc.c +else +romstage-y += mc146818rtc.c +endif ramstage-y += isa-dma.c ramstage-y += i8254.c ramstage-y += i8259.c

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Patch set updated for coreboot: 8250671 vendorcode/.../fsp/baytrail: remove duplicate prototype
by Martin Roth 19 May '14

19 May '14

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5736 -gerrit commit 8250671ea9c460914ac2ea2f1a5b2cee7be5ddc8 Author: Martin Roth <gaumless(a)gmail.com> Date: Tue May 13 14:33:37 2014 -0600 vendorcode/.../fsp/baytrail: remove duplicate prototype There were two copies of the GetFspReservedMemoryFromGuid prototype in the fspplatform.h file for some reason. Change-Id: Id121f1e3ddf5aad28b954c873c93f921ce35624f Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/vendorcode/intel/fsp/baytrail/include/fspplatform.h | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/src/vendorcode/intel/fsp/baytrail/include/fspplatform.h b/src/vendorcode/intel/fsp/baytrail/include/fspplatform.h index 1b5fca1..81f7b66 100644 --- a/src/vendorcode/intel/fsp/baytrail/include/fspplatform.h +++ b/src/vendorcode/intel/fsp/baytrail/include/fspplatform.h @@ -75,11 +75,4 @@ GetLowMemorySize ( uint32_t *LowMemoryLength ); -void -GetFspReservedMemoryFromGuid ( - uint32_t *FspMemoryBase, - uint32_t *FspMemoryLength, - EFI_GUID FspReservedMemoryGuid - ); - -#endif \ No newline at end of file +#endif

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Patch merged into coreboot/master: 8dd407a vendorcode/amd/agesa: Logic typo in GfxPowerPlayLocateTdp
by gerrit＠coreboot.org 19 May '14

19 May '14

the following patch was just integrated into master: commit 8dd407a878e8e4f86591ecde0af44400eb3fa098 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 15 19:37:24 2014 +1000 vendorcode/amd/agesa: Logic typo in GfxPowerPlayLocateTdp The function GfxPowerPlayLocateTdp() sets MinDeltaSclk to a maximum sentinel value and checks DeltaSclk in a loop to minimize MinDeltaSclk. However, MinDeltaSclk incorrectly self-assigns. Change-Id: Id01c792057681516bba411adec268769a3549aa8 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5752 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> See http://review.coreboot.org/5752 for details. -gerrit

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Patch merged into coreboot/master: b2d6897 amd/agesa: Implicit assigment between enum without cast
by gerrit＠coreboot.org 19 May '14

19 May '14

the following patch was just integrated into master: commit b2d68976c830c3b4eddf78ea788f02cfa6d25ffc Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 15 21:23:51 2014 +1000 amd/agesa: Implicit assigment between enum without cast Change-Id: I31632948ce69b2d1ff63b6c920016ed6fdf9e2f8 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5760 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/5760 for details. -gerrit

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Patch merged into coreboot/master: e1845b3 amd/agesa/f*: Strip tailing white-spaces from gcc-intrin.h
by gerrit＠coreboot.org 19 May '14

19 May '14

the following patch was just integrated into master: commit e1845b38c7cd4c6e18b07d82d2ba6aebd9b8170f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue May 20 04:36:41 2014 +1000 amd/agesa/f*: Strip tailing white-spaces from gcc-intrin.h Change-Id: I1d801b9d8387e267feeb95563e55910b30ebbc34 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5790 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/5790 for details. -gerrit

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Patch set updated for coreboot: c51a9cc mainboard/ibase/mb899: Indent devicetree.cb
by Edward O'Callaghan 19 May '14

19 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5778 -gerrit commit c51a9ccda9debe86fe5f32772ff66fe7466f1509 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun May 18 10:33:31 2014 +1000 mainboard/ibase/mb899: Indent devicetree.cb Change-Id: I29037c322dac5ed9ebc36b95bc1981acf21e5bd0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/ibase/mb899/devicetree.cb | 92 ++++++++++++++++----------------- 1 file changed, 44 insertions(+), 48 deletions(-) diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 7e5076d..c304908 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -1,18 +1,17 @@ chip northbridge/intel/i945 + device cpu_cluster 0 on + chip cpu/intel/socket_mFCPGA478 + device lapic 0 on end + end + end - device cpu_cluster 0 on - chip cpu/intel/socket_mFCPGA478 - device lapic 0 on end - end - end - - device domain 0 on - device pci 00.0 on end # host bridge + device domain 0 on + device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port device pci 02.0 on end # vga controller device pci 02.1 on end # display controller - chip southbridge/intel/i82801gx + chip southbridge/intel/i82801gx register "pirqa_routing" = "0x05" register "pirqb_routing" = "0x07" register "pirqc_routing" = "0x05" @@ -28,44 +27,42 @@ chip northbridge/intel/i945 # 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "1" - register "ide_legacy_combined" = "0x0" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x1" - #device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe - device pci 1c.1 on end # PCIe - device pci 1c.2 on end # PCIe + #device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe + device pci 1c.1 on end # PCIe + device pci 1c.2 on end # PCIe #device pci 1c.3 off end # PCIe port 4 #device pci 1c.4 off end # PCIe port 5 #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on end # PCI bridge #device pci 1e.2 off end # AC'97 Audio #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge - chip superio/winbond/w83627ehg - device pnp 4e.0 off # Floppy - end - device pnp 4e.1 off # Parport + device pci 1f.0 on # LPC bridge + chip superio/winbond/w83627ehg + device pnp 4e.0 off end # Floppy + device pnp 4e.1 off end # Parport + device pnp 4e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - device pnp 4e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + device pnp 4e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end + end device pnp 4e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 + io 0x60 = 0x60 + io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 irq 0xf0 = 0x82 # HW accel A20. @@ -97,14 +94,13 @@ chip northbridge/intel/i945 io 0x60 = 0x290 irq 0x70 = 0 end - - end - - end + end # chip superio/winbond/w83627ehg + end # LPC bridge device pci 1f.1 on end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - #device pci 1f.4 off end # Realtek ID Codec - end - end -end + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMBus + # device pci 1f.4 off end # Realtek ID Codec + end # chip southbridge/intel/i82801gx + + end # device domain0 +end # chip northbridge/intel/i945

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coreboot-gerrit May 2014