coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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1066 discussions

New patch to review for coreboot: f9efa0a baytrail: Fix some minor errors in FSP
by David Hendricks 20 May '14

20 May '14

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5798 -gerrit commit f9efa0afb75fb0f1e2884b434c6dc4f04540369e Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue May 20 15:52:08 2014 -0700 baytrail: Fix some minor errors in FSP - Duplicate declaration of GetFspReservedMemoryFromGuid - Corrupt line that was only compiled for a southbridge that no board in coreboot currently uses. (thanks for Mike Hibbett <mhibbett(a)ircona.com> for pointing this out) Change-Id: I847e807272acbaa93c87a89c0d2f94829c9121e6 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c | 2 +- src/vendorcode/intel/fsp/baytrail/include/fspplatform.h | 9 +-------- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c index f7bb023..0537c54 100644 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c @@ -89,7 +89,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) /* Initialize the UPD Data */ - GetUpdDefaultFromFsp (fsp_ptr, fsp_upd_data);/home/martin/extra/git/coreboot + GetUpdDefaultFromFsp (fsp_ptr, fsp_upd_data); ConfigureDefaultUpdData(fsp_upd_data); #else pFspRtBuffer->Platform.MemoryConfig = &MemoryConfig; diff --git a/src/vendorcode/intel/fsp/baytrail/include/fspplatform.h b/src/vendorcode/intel/fsp/baytrail/include/fspplatform.h index 1b5fca1..81f7b66 100644 --- a/src/vendorcode/intel/fsp/baytrail/include/fspplatform.h +++ b/src/vendorcode/intel/fsp/baytrail/include/fspplatform.h @@ -75,11 +75,4 @@ GetLowMemorySize ( uint32_t *LowMemoryLength ); -void -GetFspReservedMemoryFromGuid ( - uint32_t *FspMemoryBase, - uint32_t *FspMemoryLength, - EFI_GUID FspReservedMemoryGuid - ); - -#endif \ No newline at end of file +#endif

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Patch set updated for coreboot: cb5f354 mainboard/ibase/mb899: Break out superio hwm conf from mainboard.c
by Edward O'Callaghan 20 May '14

20 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5797 -gerrit commit cb5f354ceffb3434fffc49fb68224764b066a0dd Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed May 21 07:00:48 2014 +1000 mainboard/ibase/mb899: Break out superio hwm conf from mainboard.c Break out the PNP Super I/O HWM configuration from mainboard.c Change-Id: Ib4c7f26c7fa2a9845250a61a23c75cb9e440ab93 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/ibase/mb899/Makefile.inc | 1 + src/mainboard/ibase/mb899/mainboard.c | 136 +-------------------------- src/mainboard/ibase/mb899/superio_hwm.c | 160 ++++++++++++++++++++++++++++++++ src/mainboard/ibase/mb899/superio_hwm.h | 25 +++++ 4 files changed, 188 insertions(+), 134 deletions(-) diff --git a/src/mainboard/ibase/mb899/Makefile.inc b/src/mainboard/ibase/mb899/Makefile.inc new file mode 100644 index 0000000..c4e781b --- /dev/null +++ b/src/mainboard/ibase/mb899/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += superio_hwm.c diff --git a/src/mainboard/ibase/mb899/mainboard.c b/src/mainboard/ibase/mb899/mainboard.c index c7b846f..3730984 100644 --- a/src/mainboard/ibase/mb899/mainboard.c +++ b/src/mainboard/ibase/mb899/mainboard.c @@ -27,6 +27,8 @@ #include <arch/io.h> #include <arch/interrupt.h> +#include "superio_hwm.h" + #if CONFIG_VGA_ROM_RUN static int int15_handler(void) { @@ -63,140 +65,6 @@ static int int15_handler(void) } #endif -/* Hardware Monitor */ - -static u16 hwm_base = 0x290; - -static void hwm_write(u8 reg, u8 value) -{ - outb(reg, hwm_base + 0x05); - outb(value, hwm_base + 0x06); -} - -static void hwm_bank(u8 bank) -{ - hwm_write(0x4e, bank); -} - -#define FAN_CRUISE_CONTROL_DISABLED 0 -#define FAN_CRUISE_CONTROL_SPEED 1 -#define FAN_CRUISE_CONTROL_THERMAL 2 - -#define FAN_SPEED_5625 0 -//#define FAN_TEMPERATURE_30DEGC 0 - -struct fan_speed { - u8 fan_in; - u16 fan_speed; -}; - -// FANIN Target Speed Register -// FANIN = 337500 / RPM -struct fan_speed fan_speeds[] = { - { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, - { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, - { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 }, - { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 } -}; - -struct temperature { - u8 deg_celsius; - u8 deg_fahrenheit; -}; - -struct temperature temperatures[] = { - { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 }, - { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 }, - { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 }, - { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 } -}; - -static void hwm_setup(void) -{ - int cpufan_control = 0, sysfan_control = 0; - int cpufan_speed = 0, sysfan_speed = 0; - int cpufan_temperature = 0, sysfan_temperature = 0; - - if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS) - cpufan_control = FAN_CRUISE_CONTROL_DISABLED; - if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS) - cpufan_speed = FAN_SPEED_5625; - //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS) - // cpufan_temperature = FAN_TEMPERATURE_30DEGC; - - if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS) - sysfan_control = FAN_CRUISE_CONTROL_DISABLED; - if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS) - sysfan_speed = FAN_SPEED_5625; - //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) - // sysfan_temperature = FAN_TEMPERATURE_30DEGC; - - // hwm_write(0x31, 0x20); // AVCC high limit - // hwm_write(0x34, 0x06); // VIN2 low limit - - hwm_bank(0); - hwm_write(0x59, 0x20); // Diode Selection - hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor - - hwm_bank(4); - hwm_write(0x54, 0xf1); // SYSTIN temperature offset - hwm_write(0x55, 0x19); // CPUTIN temperature offset - hwm_write(0x56, 0xfc); // AUXTIN temperature offset - - hwm_bank(0x80); // Default - - u8 fan_config = 0; - // 00 FANOUT is Manual Mode - // 01 FANOUT is Thermal Cruise Mode - // 10 FANOUT is Fan Speed Cruise Mode - switch (cpufan_control) { - case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; - case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; - } - switch (sysfan_control) { - case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; - case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; - } - // This register must be written first - hwm_write(0x04, fan_config); - - switch (cpufan_control) { - case FAN_CRUISE_CONTROL_SPEED: - printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", - fan_speeds[cpufan_speed].fan_speed); - hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed - break; - case FAN_CRUISE_CONTROL_THERMAL: - printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", - temperatures[cpufan_temperature].deg_celsius, - temperatures[cpufan_temperature].deg_fahrenheit); - hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature - break; - } - - switch (sysfan_control) { - case FAN_CRUISE_CONTROL_SPEED: - printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", - fan_speeds[sysfan_speed].fan_speed); - hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed - break; - case FAN_CRUISE_CONTROL_THERMAL: - printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", - temperatures[sysfan_temperature].deg_celsius, - temperatures[sysfan_temperature].deg_fahrenheit); - hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature - break; - } - - hwm_write(0x0e, 0x02); // Fan Output Step Down Time - hwm_write(0x0f, 0x02); // Fan Output Step Up Time - - hwm_write(0x47, 0xaf); // FAN divisor register - hwm_write(0x4b, 0x84); // AUXFANIN speed divisor - - hwm_write(0x40, 0x01); // Init, but no SMI# -} - /* Audio Setup */ extern u32 * cim_verb_data; diff --git a/src/mainboard/ibase/mb899/superio_hwm.c b/src/mainboard/ibase/mb899/superio_hwm.c new file mode 100644 index 0000000..2d14c2c --- /dev/null +++ b/src/mainboard/ibase/mb899/superio_hwm.c @@ -0,0 +1,160 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <device/device.h> +#include <console/console.h> +#include <arch/io.h> + +#include "superio_hwm.h" + +/* Hardware Monitor */ + +#define FAN_CRUISE_CONTROL_DISABLED 0 +#define FAN_CRUISE_CONTROL_SPEED 1 +#define FAN_CRUISE_CONTROL_THERMAL 2 + +#define FAN_SPEED_5625 0 +//#define FAN_TEMPERATURE_30DEGC 0 + +#define HWM_BASE 0x290 + +static void hwm_write(u8 reg, u8 value) +{ + outb(reg, HWM_BASE + 0x05); + outb(value, HWM_BASE + 0x06); +} + +static void hwm_bank(u8 bank) +{ + hwm_write(0x4e, bank); +} + +struct fan_speed { + u8 fan_in; + u16 fan_speed; +}; + +// FANIN Target Speed Register +// FANIN = 337500 / RPM +struct fan_speed fan_speeds[] = { + { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, + { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, + { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 }, + { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 } +}; + +struct temperature { + u8 deg_celsius; + u8 deg_fahrenheit; +}; + +struct temperature temperatures[] = { + { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 }, + { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 }, + { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 }, + { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 } +}; + +void hwm_setup(void) +{ + int cpufan_control = 0, sysfan_control = 0; + int cpufan_speed = 0, sysfan_speed = 0; + int cpufan_temperature = 0, sysfan_temperature = 0; + + if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS) + cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS) + cpufan_speed = FAN_SPEED_5625; + //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS) + // cpufan_temperature = FAN_TEMPERATURE_30DEGC; + + if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS) + sysfan_control = FAN_CRUISE_CONTROL_DISABLED; + if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS) + sysfan_speed = FAN_SPEED_5625; + //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) + // sysfan_temperature = FAN_TEMPERATURE_30DEGC; + + // hwm_write(0x31, 0x20); // AVCC high limit + // hwm_write(0x34, 0x06); // VIN2 low limit + + hwm_bank(0); + hwm_write(0x59, 0x20); // Diode Selection + hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor + + hwm_bank(4); + hwm_write(0x54, 0xf1); // SYSTIN temperature offset + hwm_write(0x55, 0x19); // CPUTIN temperature offset + hwm_write(0x56, 0xfc); // AUXTIN temperature offset + + hwm_bank(0x80); // Default + + u8 fan_config = 0; + // 00 FANOUT is Manual Mode + // 01 FANOUT is Thermal Cruise Mode + // 10 FANOUT is Fan Speed Cruise Mode + switch (cpufan_control) { + case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; + case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; + } + switch (sysfan_control) { + case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; + case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; + } + // This register must be written first + hwm_write(0x04, fan_config); + + switch (cpufan_control) { + case FAN_CRUISE_CONTROL_SPEED: + printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", + fan_speeds[cpufan_speed].fan_speed); + hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed + break; + case FAN_CRUISE_CONTROL_THERMAL: + printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", + temperatures[cpufan_temperature].deg_celsius, + temperatures[cpufan_temperature].deg_fahrenheit); + hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature + break; + } + + switch (sysfan_control) { + case FAN_CRUISE_CONTROL_SPEED: + printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", + fan_speeds[sysfan_speed].fan_speed); + hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed + break; + case FAN_CRUISE_CONTROL_THERMAL: + printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", + temperatures[sysfan_temperature].deg_celsius, + temperatures[sysfan_temperature].deg_fahrenheit); + hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature + break; + } + + hwm_write(0x0e, 0x02); // Fan Output Step Down Time + hwm_write(0x0f, 0x02); // Fan Output Step Up Time + + hwm_write(0x47, 0xaf); // FAN divisor register + hwm_write(0x4b, 0x84); // AUXFANIN speed divisor + + hwm_write(0x40, 0x01); // Init, but no SMI# +} diff --git a/src/mainboard/ibase/mb899/superio_hwm.h b/src/mainboard/ibase/mb899/superio_hwm.h new file mode 100644 index 0000000..346b97c --- /dev/null +++ b/src/mainboard/ibase/mb899/superio_hwm.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_HWM_H +#define SUPERIO_HWM_H + +void hwm_setup(void); + +#endif /* SUPERIO_HWM_H */

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New patch to review for coreboot: e1a1361 mainboard/ibase/mb899: Break out superio hwm conf from mainboard
by Edward O'Callaghan 20 May '14

20 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5797 -gerrit commit e1a1361232deebf79fb771bd2aa95063f3374944 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed May 21 07:00:48 2014 +1000 mainboard/ibase/mb899: Break out superio hwm conf from mainboard Break out the PNP Super I/O HWM configuration from mainboard.c Change-Id: Ib4c7f26c7fa2a9845250a61a23c75cb9e440ab93 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/ibase/mb899/mainboard.c | 136 +-------------------------- src/mainboard/ibase/mb899/superio_hwm.c | 160 ++++++++++++++++++++++++++++++++ src/mainboard/ibase/mb899/superio_hwm.h | 25 +++++ 3 files changed, 187 insertions(+), 134 deletions(-) diff --git a/src/mainboard/ibase/mb899/mainboard.c b/src/mainboard/ibase/mb899/mainboard.c index c7b846f..3730984 100644 --- a/src/mainboard/ibase/mb899/mainboard.c +++ b/src/mainboard/ibase/mb899/mainboard.c @@ -27,6 +27,8 @@ #include <arch/io.h> #include <arch/interrupt.h> +#include "superio_hwm.h" + #if CONFIG_VGA_ROM_RUN static int int15_handler(void) { @@ -63,140 +65,6 @@ static int int15_handler(void) } #endif -/* Hardware Monitor */ - -static u16 hwm_base = 0x290; - -static void hwm_write(u8 reg, u8 value) -{ - outb(reg, hwm_base + 0x05); - outb(value, hwm_base + 0x06); -} - -static void hwm_bank(u8 bank) -{ - hwm_write(0x4e, bank); -} - -#define FAN_CRUISE_CONTROL_DISABLED 0 -#define FAN_CRUISE_CONTROL_SPEED 1 -#define FAN_CRUISE_CONTROL_THERMAL 2 - -#define FAN_SPEED_5625 0 -//#define FAN_TEMPERATURE_30DEGC 0 - -struct fan_speed { - u8 fan_in; - u16 fan_speed; -}; - -// FANIN Target Speed Register -// FANIN = 337500 / RPM -struct fan_speed fan_speeds[] = { - { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, - { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, - { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 }, - { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 } -}; - -struct temperature { - u8 deg_celsius; - u8 deg_fahrenheit; -}; - -struct temperature temperatures[] = { - { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 }, - { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 }, - { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 }, - { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 } -}; - -static void hwm_setup(void) -{ - int cpufan_control = 0, sysfan_control = 0; - int cpufan_speed = 0, sysfan_speed = 0; - int cpufan_temperature = 0, sysfan_temperature = 0; - - if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS) - cpufan_control = FAN_CRUISE_CONTROL_DISABLED; - if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS) - cpufan_speed = FAN_SPEED_5625; - //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS) - // cpufan_temperature = FAN_TEMPERATURE_30DEGC; - - if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS) - sysfan_control = FAN_CRUISE_CONTROL_DISABLED; - if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS) - sysfan_speed = FAN_SPEED_5625; - //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) - // sysfan_temperature = FAN_TEMPERATURE_30DEGC; - - // hwm_write(0x31, 0x20); // AVCC high limit - // hwm_write(0x34, 0x06); // VIN2 low limit - - hwm_bank(0); - hwm_write(0x59, 0x20); // Diode Selection - hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor - - hwm_bank(4); - hwm_write(0x54, 0xf1); // SYSTIN temperature offset - hwm_write(0x55, 0x19); // CPUTIN temperature offset - hwm_write(0x56, 0xfc); // AUXTIN temperature offset - - hwm_bank(0x80); // Default - - u8 fan_config = 0; - // 00 FANOUT is Manual Mode - // 01 FANOUT is Thermal Cruise Mode - // 10 FANOUT is Fan Speed Cruise Mode - switch (cpufan_control) { - case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; - case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; - } - switch (sysfan_control) { - case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; - case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; - } - // This register must be written first - hwm_write(0x04, fan_config); - - switch (cpufan_control) { - case FAN_CRUISE_CONTROL_SPEED: - printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", - fan_speeds[cpufan_speed].fan_speed); - hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed - break; - case FAN_CRUISE_CONTROL_THERMAL: - printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", - temperatures[cpufan_temperature].deg_celsius, - temperatures[cpufan_temperature].deg_fahrenheit); - hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature - break; - } - - switch (sysfan_control) { - case FAN_CRUISE_CONTROL_SPEED: - printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", - fan_speeds[sysfan_speed].fan_speed); - hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed - break; - case FAN_CRUISE_CONTROL_THERMAL: - printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", - temperatures[sysfan_temperature].deg_celsius, - temperatures[sysfan_temperature].deg_fahrenheit); - hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature - break; - } - - hwm_write(0x0e, 0x02); // Fan Output Step Down Time - hwm_write(0x0f, 0x02); // Fan Output Step Up Time - - hwm_write(0x47, 0xaf); // FAN divisor register - hwm_write(0x4b, 0x84); // AUXFANIN speed divisor - - hwm_write(0x40, 0x01); // Init, but no SMI# -} - /* Audio Setup */ extern u32 * cim_verb_data; diff --git a/src/mainboard/ibase/mb899/superio_hwm.c b/src/mainboard/ibase/mb899/superio_hwm.c new file mode 100644 index 0000000..2d14c2c --- /dev/null +++ b/src/mainboard/ibase/mb899/superio_hwm.c @@ -0,0 +1,160 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <device/device.h> +#include <console/console.h> +#include <arch/io.h> + +#include "superio_hwm.h" + +/* Hardware Monitor */ + +#define FAN_CRUISE_CONTROL_DISABLED 0 +#define FAN_CRUISE_CONTROL_SPEED 1 +#define FAN_CRUISE_CONTROL_THERMAL 2 + +#define FAN_SPEED_5625 0 +//#define FAN_TEMPERATURE_30DEGC 0 + +#define HWM_BASE 0x290 + +static void hwm_write(u8 reg, u8 value) +{ + outb(reg, HWM_BASE + 0x05); + outb(value, HWM_BASE + 0x06); +} + +static void hwm_bank(u8 bank) +{ + hwm_write(0x4e, bank); +} + +struct fan_speed { + u8 fan_in; + u16 fan_speed; +}; + +// FANIN Target Speed Register +// FANIN = 337500 / RPM +struct fan_speed fan_speeds[] = { + { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, + { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, + { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 }, + { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 } +}; + +struct temperature { + u8 deg_celsius; + u8 deg_fahrenheit; +}; + +struct temperature temperatures[] = { + { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 }, + { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 }, + { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 }, + { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 } +}; + +void hwm_setup(void) +{ + int cpufan_control = 0, sysfan_control = 0; + int cpufan_speed = 0, sysfan_speed = 0; + int cpufan_temperature = 0, sysfan_temperature = 0; + + if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS) + cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS) + cpufan_speed = FAN_SPEED_5625; + //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS) + // cpufan_temperature = FAN_TEMPERATURE_30DEGC; + + if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS) + sysfan_control = FAN_CRUISE_CONTROL_DISABLED; + if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS) + sysfan_speed = FAN_SPEED_5625; + //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) + // sysfan_temperature = FAN_TEMPERATURE_30DEGC; + + // hwm_write(0x31, 0x20); // AVCC high limit + // hwm_write(0x34, 0x06); // VIN2 low limit + + hwm_bank(0); + hwm_write(0x59, 0x20); // Diode Selection + hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor + + hwm_bank(4); + hwm_write(0x54, 0xf1); // SYSTIN temperature offset + hwm_write(0x55, 0x19); // CPUTIN temperature offset + hwm_write(0x56, 0xfc); // AUXTIN temperature offset + + hwm_bank(0x80); // Default + + u8 fan_config = 0; + // 00 FANOUT is Manual Mode + // 01 FANOUT is Thermal Cruise Mode + // 10 FANOUT is Fan Speed Cruise Mode + switch (cpufan_control) { + case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; + case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; + } + switch (sysfan_control) { + case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; + case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; + } + // This register must be written first + hwm_write(0x04, fan_config); + + switch (cpufan_control) { + case FAN_CRUISE_CONTROL_SPEED: + printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", + fan_speeds[cpufan_speed].fan_speed); + hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed + break; + case FAN_CRUISE_CONTROL_THERMAL: + printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", + temperatures[cpufan_temperature].deg_celsius, + temperatures[cpufan_temperature].deg_fahrenheit); + hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature + break; + } + + switch (sysfan_control) { + case FAN_CRUISE_CONTROL_SPEED: + printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", + fan_speeds[sysfan_speed].fan_speed); + hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed + break; + case FAN_CRUISE_CONTROL_THERMAL: + printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", + temperatures[sysfan_temperature].deg_celsius, + temperatures[sysfan_temperature].deg_fahrenheit); + hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature + break; + } + + hwm_write(0x0e, 0x02); // Fan Output Step Down Time + hwm_write(0x0f, 0x02); // Fan Output Step Up Time + + hwm_write(0x47, 0xaf); // FAN divisor register + hwm_write(0x4b, 0x84); // AUXFANIN speed divisor + + hwm_write(0x40, 0x01); // Init, but no SMI# +} diff --git a/src/mainboard/ibase/mb899/superio_hwm.h b/src/mainboard/ibase/mb899/superio_hwm.h new file mode 100644 index 0000000..346b97c --- /dev/null +++ b/src/mainboard/ibase/mb899/superio_hwm.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_HWM_H +#define SUPERIO_HWM_H + +void hwm_setup(void); + +#endif /* SUPERIO_HWM_H */

1 0

New patch to review for coreboot: 816f54b mainboard/ibase/mb899: Sanitize headers
by Edward O'Callaghan 20 May '14

20 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5796 -gerrit commit 816f54bc915b3536c28cbadcada89aa212577c5a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed May 21 06:51:15 2014 +1000 mainboard/ibase/mb899: Sanitize headers These are not local headers. Change-Id: Ie0b0a682565a08dbfa089986dc7860fdb0846949 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/ibase/mb899/irq_tables.c | 1 - src/mainboard/ibase/mb899/mainboard.c | 1 - src/mainboard/ibase/mb899/romstage.c | 6 +++--- src/mainboard/ibase/mb899/smihandler.c | 4 +--- 4 files changed, 4 insertions(+), 8 deletions(-) diff --git a/src/mainboard/ibase/mb899/irq_tables.c b/src/mainboard/ibase/mb899/irq_tables.c index c206bf1..9c275d5 100644 --- a/src/mainboard/ibase/mb899/irq_tables.c +++ b/src/mainboard/ibase/mb899/irq_tables.c @@ -58,4 +58,3 @@ unsigned long write_pirq_routing_table(unsigned long addr) { return copy_pirq_routing_table(addr, &intel_irq_routing_table); } - diff --git a/src/mainboard/ibase/mb899/mainboard.c b/src/mainboard/ibase/mb899/mainboard.c index f6d2456..c7b846f 100644 --- a/src/mainboard/ibase/mb899/mainboard.c +++ b/src/mainboard/ibase/mb899/mainboard.c @@ -225,4 +225,3 @@ static void mainboard_enable(device_t dev) struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; - diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 067d25b..0957795 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -32,9 +32,9 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> -#include "northbridge/intel/i945/i945.h" -#include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) #define DUMMY_DEV PNP_DEV(0x4e, 0) diff --git a/src/mainboard/ibase/mb899/smihandler.c b/src/mainboard/ibase/mb899/smihandler.c index 064109b..d1f4f7b 100644 --- a/src/mainboard/ibase/mb899/smihandler.c +++ b/src/mainboard/ibase/mb899/smihandler.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include "southbridge/intel/i82801gx/nvs.h" +#include <southbridge/intel/i82801gx/nvs.h> /* The southbridge SMI handler checks whether gnvs has a * valid pointer before calling the trap handler @@ -47,5 +47,3 @@ int mainboard_io_trap_handler(int smif) //gnvs->smif = 0; return 1; } - -

1 0

Patch set updated for coreboot: 2c69fa7 console: Add console for GDB
by Kyösti Mälkki 20 May '14

20 May '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5343 -gerrit commit 2c69fa78cdbcd8b9745f49fbca041eacb0dd413a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Apr 4 15:05:28 2014 +0300 console: Add console for GDB Connection of UARTs to GDB stub got lost in the console transition process, bring it back. In theory, GDB stub should work also over usbdebug, but that solution is not really tested at all yet. Change-Id: I90e05e8132889e788b92e055ee191f35add43bbc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/c_start.S | 1 + src/arch/x86/lib/exception.c | 13 +++++++++++-- src/console/console.c | 24 ++++++++++++++++++++++++ src/include/console/streams.h | 6 ++++++ src/include/console/uart.h | 8 ++++++++ src/include/console/usb.h | 16 ++++++++++++++-- 6 files changed, 64 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S index faea22d..675a09c 100644 --- a/src/arch/x86/lib/c_start.S +++ b/src/arch/x86/lib/c_start.S @@ -86,6 +86,7 @@ _start: post_code(POST_PRE_HARDWAREMAIN) /* post fe */ #if CONFIG_GDB_WAIT + call gdb_hw_init call gdb_stub_breakpoint #endif call main diff --git a/src/arch/x86/lib/exception.c b/src/arch/x86/lib/exception.c index 9756949..f64b2e7 100644 --- a/src/arch/x86/lib/exception.c +++ b/src/arch/x86/lib/exception.c @@ -1,4 +1,5 @@ #include <console/console.h> +#include <console/streams.h> #include <string.h> #if CONFIG_GDB_STUB @@ -217,12 +218,17 @@ static char out_buffer[BUFMAX]; static inline void stub_putc(int ch) { - console_tx_byte(ch); + gdb_tx_byte(ch); +} + +static inline void stub_flush(void) +{ + gdb_tx_flush(); } static inline int stub_getc(void) { - return console_rx_byte(); + return gdb_rx_byte(); } static int hex(char ch) @@ -322,9 +328,11 @@ static int get_packet(char *buffer) if (checksum != xmitcsum) { stub_putc('-'); /* failed checksum */ + stub_flush(); } else { stub_putc('+'); /* successful transfer */ + stub_flush(); } } } while(checksum != xmitcsum); @@ -353,6 +361,7 @@ static void put_packet(char *buffer) stub_putc('#'); stub_putc(hexchars[checksum >> 4]); stub_putc(hexchars[checksum % 16]); + stub_flush(); } while ((stub_getc() & 0x7f) != '+'); diff --git a/src/console/console.c b/src/console/console.c index 9b1c255..bd03144 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <rules.h> #include <console/streams.h> #include <console/cbmem_console.h> #include <console/uart.h> @@ -53,3 +54,26 @@ void console_tx_flush(void) __ne2k_tx_flush(); __usb_tx_flush(); } + + +#if CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) +void gdb_hw_init(void) +{ + __gdb_hw_init(); +} + +void gdb_tx_byte(unsigned char byte) +{ + __gdb_tx_byte(byte); +} + +void gdb_tx_flush(void) +{ + __gdb_tx_flush(); +} + +unsigned char gdb_rx_byte(void) +{ + return __gdb_rx_byte(); +} +#endif diff --git a/src/include/console/streams.h b/src/include/console/streams.h index 9d4d3fc..fb168da 100644 --- a/src/include/console/streams.h +++ b/src/include/console/streams.h @@ -22,6 +22,12 @@ void console_hw_init(void); void console_tx_byte(unsigned char byte); void console_tx_flush(void); +/* For remote GDB debugging. */ +void gdb_hw_init(void); +void gdb_tx_byte(unsigned char byte); +void gdb_tx_flush(void); +unsigned char gdb_rx_byte(void); + /* Helpers for ROMCC console. */ void console_tx_nibble(unsigned nibble); void console_tx_hex8(unsigned char value); diff --git a/src/include/console/uart.h b/src/include/console/uart.h index b08cd9b..d4020c3 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -69,6 +69,14 @@ static inline void __uart_tx_byte(u8 data) {} static inline void __uart_tx_flush(void) {} #endif +#if CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) +#define CONFIG_UART_FOR_GDB CONFIG_UART_FOR_CONSOLE +static inline void __gdb_hw_init(void) { uart_init(CONFIG_UART_FOR_GDB); } +static inline void __gdb_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_GDB, data); } +static inline void __gdb_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_GDB); } +static inline u8 __gdb_rx_byte(void) { return uart_rx_byte(CONFIG_UART_FOR_GDB); } +#endif + #endif /* __ROMCC__ */ #endif /* CONSOLE_UART_H */ diff --git a/src/include/console/usb.h b/src/include/console/usb.h index 57ea4eb..b5aab66 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -34,14 +34,26 @@ int usb_can_rx_byte(int idx); #define __CONSOLE_USB_ENABLE__ CONFIG_CONSOLE_USB && \ ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE) +#define USB_PIPE_FOR_CONSOLE 0 +#define USB_PIPE_FOR_GDB 0 + #if __CONSOLE_USB_ENABLE__ static inline void __usbdebug_init(void) { usbdebug_init(); } -static inline void __usb_tx_byte(u8 data) { usb_tx_byte(0, data); } -static inline void __usb_tx_flush(void) { usb_tx_flush(0); } +static inline void __usb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_CONSOLE, data); } +static inline void __usb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_CONSOLE); } #else static inline void __usbdebug_init(void) {} static inline void __usb_tx_byte(u8 data) {} static inline void __usb_tx_flush(void) {} #endif +/* */ +#if 0 && CONFIG_GDB_STUB && \ + ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE) +static inline void __gdb_hw_init(void) { usbdebug_init(); } +static inline void __gdb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_GDB, data); } +static inline void __gdb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_GDB); } +static inline u8 __gdb_rx_byte(void) { return usb_rx_byte(USB_PIPE_FOR_GDB); } +#endif + #endif /* _CONSOLE_USB_H_ */

1 0

Patch set updated for coreboot: 939a38b payloads/external/SeaBIOS: Bump version to 1.7.5-rc1
by Edward O'Callaghan 20 May '14

20 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5795 -gerrit commit 939a38bbdb8376a2e09d1a037499e92b907cfd30 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed May 21 00:27:18 2014 +1000 payloads/external/SeaBIOS: Bump version to 1.7.5-rc1 NOTFORMERGE - _yet_ waiting on 1.7.5 proper. Change-Id: I43fd860eab8a6e770741c749a1a67de3ed5cbde0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- payloads/external/SeaBIOS/Makefile.inc | 2 +- src/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 042df0a..edf1eaa 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=88cb66ea542906ffff8a80ef397b9e3adbb33116 +TAG-$(CONFIG_SEABIOS_STABLE)=b1d4dc908401719c5de78c25313cf82c7cd1d602 unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG diff --git a/src/Kconfig b/src/Kconfig index 53a23bb..32e7f98 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -599,7 +599,7 @@ choice depends on PAYLOAD_SEABIOS config SEABIOS_STABLE - bool "1.7.2.1" + bool "1.7.5-rc1" help Stable SeaBIOS version config SEABIOS_MASTER

1 0

New patch to review for coreboot: 34d11fe payloads/external/SeaBIOS: Bump version to 1.7.4
by Edward O'Callaghan 20 May '14

20 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5795 -gerrit commit 34d11fe6856e2e047b2c7d703054ebeae3c12151 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed May 21 00:27:18 2014 +1000 payloads/external/SeaBIOS: Bump version to 1.7.4 Change-Id: I43fd860eab8a6e770741c749a1a67de3ed5cbde0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- payloads/external/SeaBIOS/Makefile.inc | 2 +- src/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 042df0a..48ca582 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=88cb66ea542906ffff8a80ef397b9e3adbb33116 +TAG-$(CONFIG_SEABIOS_STABLE)=96917a8ed761f017fc8c72ba3b9181fbac03ac59 unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG diff --git a/src/Kconfig b/src/Kconfig index 53a23bb..061f63e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -599,7 +599,7 @@ choice depends on PAYLOAD_SEABIOS config SEABIOS_STABLE - bool "1.7.2.1" + bool "1.7.4" help Stable SeaBIOS version config SEABIOS_MASTER

1 0

Patch merged into coreboot/master: 61113de mainboard/ibase/mb899: Indent devicetree.cb
by gerrit＠coreboot.org 20 May '14

20 May '14

the following patch was just integrated into master: commit 61113de9234f1b933a084c90097ec125fc12f55d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun May 18 10:33:31 2014 +1000 mainboard/ibase/mb899: Indent devicetree.cb Change-Id: I29037c322dac5ed9ebc36b95bc1981acf21e5bd0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5778 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/5778 for details. -gerrit

1 0

Patch merged into coreboot/master: fb8df32 drivers: Drop GbE stub drivers
by gerrit＠coreboot.org 20 May '14

20 May '14

the following patch was just integrated into master: commit fb8df3240f5ac80a39b36ca8b5bad291156437a3 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun May 18 09:42:46 2014 +1000 drivers: Drop GbE stub drivers These NIC stub drivers were to initialize the Gigabit Ethernet adapters just enough to keep coreboot from trying to execute an option ROM. However this is no longer required as non-VGA option roms are not ran; See: b32816e Remove PCI_ROM_RUN option Change-Id: Idc44619767c631c5fcf550a5948c8947bde5e218 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5777 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/5777 for details. -gerrit

1 0

Patch set updated for coreboot: 019c772 drivers: Drop GbE stub drivers
by Edward O'Callaghan 19 May '14

19 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5777 -gerrit commit 019c772917f85184cae555cb51e5a517c7809ed0 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun May 18 09:42:46 2014 +1000 drivers: Drop GbE stub drivers These NIC stub drivers were to initialize the Gigabit Ethernet adapters just enough to keep coreboot from trying to execute an option ROM. However this is no longer required as non-VGA option roms are not ran; See: b32816e Remove PCI_ROM_RUN option Change-Id: Idc44619767c631c5fcf550a5948c8947bde5e218 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/drivers/Kconfig | 1 - src/drivers/Makefile.inc | 1 - src/drivers/realtek/Kconfig | 6 ----- src/drivers/realtek/Makefile.inc | 20 -------------- src/drivers/realtek/rtl8168.c | 49 ---------------------------------- src/mainboard/getac/p470/Kconfig | 1 - src/mainboard/ibase/mb899/Makefile.inc | 20 -------------- src/mainboard/ibase/mb899/mv88e8053.c | 49 ---------------------------------- src/mainboard/intel/d945gclf/Kconfig | 1 - src/mainboard/kontron/986lcd-m/Kconfig | 1 - src/mainboard/roda/rk886ex/Kconfig | 1 - src/mainboard/roda/rk9/Kconfig | 1 - 12 files changed, 151 deletions(-) diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index 1a5f8ff..874ec75 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -31,7 +31,6 @@ source src/drivers/parade/Kconfig if PC80_SYSTEM source src/drivers/pc80/Kconfig endif -source src/drivers/realtek/Kconfig source src/drivers/sil/Kconfig source src/drivers/spi/Kconfig source src/drivers/ti/Kconfig diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index f11e4b8..66fe7b8 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -26,7 +26,6 @@ subdirs-y += intel subdirs-y += maxim subdirs-y += net subdirs-y += parade -subdirs-y += realtek subdirs-y += sil subdirs-y += trident subdirs-$(CONFIG_DRIVERS_UART) += uart diff --git a/src/drivers/realtek/Kconfig b/src/drivers/realtek/Kconfig deleted file mode 100644 index 0799445..0000000 --- a/src/drivers/realtek/Kconfig +++ /dev/null @@ -1,6 +0,0 @@ -config RTL8168_ROM_DISABLE - bool "Disable RTL8168 ROM" - default n - help - Just enough of a driver to make coreboot not look for an Option ROM. - No configuration is necessary for the OS to pick up the device. diff --git a/src/drivers/realtek/Makefile.inc b/src/drivers/realtek/Makefile.inc deleted file mode 100644 index d7f39ac..0000000 --- a/src/drivers/realtek/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2012 secunet Security Networks AG -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ramstage-$(CONFIG_RTL8168_ROM_DISABLE) += rtl8168.c diff --git a/src/drivers/realtek/rtl8168.c b/src/drivers/realtek/rtl8168.c deleted file mode 100644 index 655b72f..0000000 --- a/src/drivers/realtek/rtl8168.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This code should work for all ICH* southbridges with a NIC. */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> - -static void nic_init(struct device *dev) -{ - printk(BIOS_DEBUG, "Initializing RTL8168 Gigabit Ethernet\n"); - // Nothing to do yet, but this has to be here to keep - // coreboot from trying to execute an option ROM. -} - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .scan_bus = 0, -}; - -static const struct pci_driver rtl8169_nic __pci_driver = { - .ops = &nic_ops, - .vendor = 0x10ec, - .device = 0x8168, -}; - - diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index 1ccf39e..78b76ba 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -39,7 +39,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_LAPIC select BOARD_ROMSIZE_KB_1024 select CHANNEL_XOR_RANDOMIZATION - select RTL8168_ROM_DISABLE config MAINBOARD_DIR string diff --git a/src/mainboard/ibase/mb899/Makefile.inc b/src/mainboard/ibase/mb899/Makefile.inc deleted file mode 100644 index 4fb55f5..0000000 --- a/src/mainboard/ibase/mb899/Makefile.inc +++ /dev/null @@ -1,20 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -ramstage-y += mv88e8053.c diff --git a/src/mainboard/ibase/mb899/mv88e8053.c b/src/mainboard/ibase/mb899/mv88e8053.c deleted file mode 100644 index 7db7fd8..0000000 --- a/src/mainboard/ibase/mb899/mv88e8053.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This code should work for all ICH* southbridges with a NIC. */ - -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> - -static void nic_init(struct device *dev) -{ - printk(BIOS_DEBUG, "Initializing 88E8053 Gigabit Ethernet\n"); - // Nothing to do yet, but this has to be here to keep - // coreboot from trying to execute an option ROM. -} - -static struct device_operations nic_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = nic_init, - .scan_bus = 0, -}; - -static const struct pci_driver rtl8169_nic __pci_driver = { - .ops = &nic_ops, - .vendor = 0x11ab, - .device = 0x4362, -}; - - diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 02522f1..28300c6 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -34,7 +34,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_512 select CHANNEL_XOR_RANDOMIZATION - select RTL8168_ROM_DISABLE config MAINBOARD_DIR string diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index 8fce5eb..4526927 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_1024 select CHANNEL_XOR_RANDOMIZATION select OVERRIDE_CLOCK_DISABLE - select RTL8168_ROM_DISABLE config MAINBOARD_DIR string diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index ffc593e..bd009f7 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_1024 select CHANNEL_XOR_RANDOMIZATION - select RTL8168_ROM_DISABLE config MAINBOARD_DIR string diff --git a/src/mainboard/roda/rk9/Kconfig b/src/mainboard/roda/rk9/Kconfig index 67fc88a..aaa7864 100644 --- a/src/mainboard/roda/rk9/Kconfig +++ b/src/mainboard/roda/rk9/Kconfig @@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82801IX select SUPERIO_SMSC_LPC47N227 select BOARD_ROMSIZE_KB_4096 - select RTL8168_ROM_DISABLE select DRIVERS_GENERIC_IOAPIC select HAVE_MP_TABLE select CARDBUS_PLUGIN_SUPPORT

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coreboot-gerrit May 2014