coreboot-gerrit May 2014

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Patch set updated for coreboot: 24ef03f superio/winbond/w83697hf: Depreciate romstage component
by Edward O'Callaghan 21 May '14

21 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5727 -gerrit commit 24ef03fd7d0d2833dd4233e10c98e68baea9c306 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed May 14 01:00:43 2014 +1000 superio/winbond/w83697hf: Depreciate romstage component Depreciate the model specific early_serial.c romstage component for this Super I/O in favor of the recent generic winbond romstage framework. Change-Id: I529c9cd1d8d63db3035b4828b3c3fc43911f49ce Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/k8v-x/romstage.c | 5 +++-- src/mainboard/bcom/winnetp680/romstage.c | 6 ++++-- src/mainboard/via/epia-m700/romstage.c | 5 +++-- src/superio/winbond/w83697hf/Makefile.inc | 2 +- src/superio/winbond/w83697hf/early_serial.c | 4 +++- src/superio/winbond/w83697hf/w83697hf.h | 12 +++++++++--- 6 files changed, 23 insertions(+), 11 deletions(-) diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 275a97e..4d6bd60 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -38,7 +38,8 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" -#include "superio/winbond/w83697hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83697hf/w83697hf.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "cpu/x86/bist.h" @@ -108,7 +109,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) int needs_reset = 0; struct sys_info *sysinfo = &sysinfo_car; - w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index a57f9f7..a252e00 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -33,7 +33,9 @@ #include <lib.h> #include <spd.h> #include "southbridge/via/vt8237r/early_smbus.c" -#include "superio/winbond/w83697hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83697hf/w83697hf.h> + #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) static inline int spd_read_byte(unsigned device, unsigned address) @@ -85,7 +87,7 @@ void main(unsigned long bist) pci_write_config8(ctrl.d0f0, 0x4f, 0x01); w83697hf_set_clksel_48(SERIAL_DEV); - w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index fda1bb0..ef0cef3 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -42,7 +42,8 @@ #include "northbridge/via/vx800/raminit.h" #include "northbridge/via/vx800/raminit.c" #include "wakeup.h" -#include "superio/winbond/w83697hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83697hf/w83697hf.h> #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) @@ -385,7 +386,7 @@ void main(unsigned long bist) pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01); /* EmbedComInit(); */ w83697hf_set_clksel_48(DUMMY_DEV); - w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* enable_vx800_serial(); */ /* diff --git a/src/superio/winbond/w83697hf/Makefile.inc b/src/superio/winbond/w83697hf/Makefile.inc index cf03273..73e5b46 100644 --- a/src/superio/winbond/w83697hf/Makefile.inc +++ b/src/superio/winbond/w83697hf/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_WINBOND_W83697HF) += early_serial.c ramstage-$(CONFIG_SUPERIO_WINBOND_W83697HF) += superio.c - diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index e435645..6c00b27 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -19,6 +19,7 @@ */ #include <arch/io.h> +#include <device/pnp_def.h> #include "w83697hf.h" static void pnp_enter_ext_func_mode(device_t dev) @@ -45,7 +46,8 @@ void w83697hf_set_clksel_48(device_t dev) pnp_exit_ext_func_mode(dev); } -static void w83697hf_enable_serial(device_t dev, u16 iobase) +/* Depreciated, use winbond_enable_serial() */ +void w83697hf_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h index 7e353e2..f711786 100644 --- a/src/superio/winbond/w83697hf/w83697hf.h +++ b/src/superio/winbond/w83697hf/w83697hf.h @@ -18,8 +18,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_WINBOND_W83697HF_W83697HF_H -#define SUPERIO_WINBOND_W83697HF_W83697HF_H +#ifndef SUPERIO_WINBOND_W83697HF_H +#define SUPERIO_WINBOND_W83697HF_H + +#include <arch/io.h> #define W83697HF_FDC 0 /* Floppy */ #define W83697HF_PP 1 /* Parallel port */ @@ -33,4 +35,8 @@ #define W83697HF_HWM 11 /* Hardware monitor */ void w83697hf_set_clksel_48(device_t); -#endif + +/* Depreciated, use winbond_enable_serial() */ +void w83697hf_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_WINBOND_W83697HF_H */

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Patch set updated for coreboot: 419fbc2 superio/winbond/w83697hf: Depreciate romstage component
by Edward O'Callaghan 21 May '14

21 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5727 -gerrit commit 419fbc2b155c62f4fc634c0a2c82c0eb62074b69 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed May 14 01:00:43 2014 +1000 superio/winbond/w83697hf: Depreciate romstage component Depreciate the model specific early_serial.c romstage component for this Super I/O in favor of the recent generic winbond romstage framework. Change-Id: I529c9cd1d8d63db3035b4828b3c3fc43911f49ce Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/k8v-x/romstage.c | 12 +++--------- src/mainboard/bcom/winnetp680/romstage.c | 6 ++++-- src/mainboard/via/epia-m700/romstage.c | 5 +++-- src/superio/winbond/w83697hf/Makefile.inc | 2 +- src/superio/winbond/w83697hf/early_serial.c | 4 +++- src/superio/winbond/w83697hf/w83697hf.h | 12 +++++++++--- 6 files changed, 23 insertions(+), 18 deletions(-) diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 4fe1016..bdf8c7b 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -38,7 +38,8 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" -#include "superio/winbond/w83697hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83697hf/w83697hf.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "cpu/x86/bist.h" @@ -124,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; sio_init(); - w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); @@ -137,13 +138,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enumerate_ht_chain(); } - // FIXME why is this executed again? ---> - sio_init(); - w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - enable_rom_decode(); - // <--- FIXME why is this executed again? - print_info("now booting... real_main\n"); if (bist == 0) diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index a57f9f7..a252e00 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -33,7 +33,9 @@ #include <lib.h> #include <spd.h> #include "southbridge/via/vt8237r/early_smbus.c" -#include "superio/winbond/w83697hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83697hf/w83697hf.h> + #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) static inline int spd_read_byte(unsigned device, unsigned address) @@ -85,7 +87,7 @@ void main(unsigned long bist) pci_write_config8(ctrl.d0f0, 0x4f, 0x01); w83697hf_set_clksel_48(SERIAL_DEV); - w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index fda1bb0..ef0cef3 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -42,7 +42,8 @@ #include "northbridge/via/vx800/raminit.h" #include "northbridge/via/vx800/raminit.c" #include "wakeup.h" -#include "superio/winbond/w83697hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83697hf/w83697hf.h> #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) @@ -385,7 +386,7 @@ void main(unsigned long bist) pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01); /* EmbedComInit(); */ w83697hf_set_clksel_48(DUMMY_DEV); - w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* enable_vx800_serial(); */ /* diff --git a/src/superio/winbond/w83697hf/Makefile.inc b/src/superio/winbond/w83697hf/Makefile.inc index cf03273..73e5b46 100644 --- a/src/superio/winbond/w83697hf/Makefile.inc +++ b/src/superio/winbond/w83697hf/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_WINBOND_W83697HF) += early_serial.c ramstage-$(CONFIG_SUPERIO_WINBOND_W83697HF) += superio.c - diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index e435645..6c00b27 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -19,6 +19,7 @@ */ #include <arch/io.h> +#include <device/pnp_def.h> #include "w83697hf.h" static void pnp_enter_ext_func_mode(device_t dev) @@ -45,7 +46,8 @@ void w83697hf_set_clksel_48(device_t dev) pnp_exit_ext_func_mode(dev); } -static void w83697hf_enable_serial(device_t dev, u16 iobase) +/* Depreciated, use winbond_enable_serial() */ +void w83697hf_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h index 7e353e2..f711786 100644 --- a/src/superio/winbond/w83697hf/w83697hf.h +++ b/src/superio/winbond/w83697hf/w83697hf.h @@ -18,8 +18,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_WINBOND_W83697HF_W83697HF_H -#define SUPERIO_WINBOND_W83697HF_W83697HF_H +#ifndef SUPERIO_WINBOND_W83697HF_H +#define SUPERIO_WINBOND_W83697HF_H + +#include <arch/io.h> #define W83697HF_FDC 0 /* Floppy */ #define W83697HF_PP 1 /* Parallel port */ @@ -33,4 +35,8 @@ #define W83697HF_HWM 11 /* Hardware monitor */ void w83697hf_set_clksel_48(device_t); -#endif + +/* Depreciated, use winbond_enable_serial() */ +void w83697hf_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_WINBOND_W83697HF_H */

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Patch set updated for coreboot: 698751d superio/winbond/w83697hf: Depreciate romstage component
by Edward O'Callaghan 21 May '14

21 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5727 -gerrit commit 698751d6fa23c42c7d24c16c11d55300b57ff0db Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed May 14 01:00:43 2014 +1000 superio/winbond/w83697hf: Depreciate romstage component Depreciate the model specific early_serial.c romstage component for this Super I/O in favor of the recent generic winbond romstage framework. Change-Id: I529c9cd1d8d63db3035b4828b3c3fc43911f49ce Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/k8v-x/romstage.c | 12 +++--------- src/mainboard/bcom/winnetp680/romstage.c | 6 ++++-- src/mainboard/via/epia-m700/romstage.c | 5 +++-- src/superio/winbond/w83697hf/Makefile.inc | 2 +- src/superio/winbond/w83697hf/early_serial.c | 3 ++- src/superio/winbond/w83697hf/w83697hf.h | 12 +++++++++--- 6 files changed, 22 insertions(+), 18 deletions(-) diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 4fe1016..bdf8c7b 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -38,7 +38,8 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" -#include "superio/winbond/w83697hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83697hf/w83697hf.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "cpu/x86/bist.h" @@ -124,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; sio_init(); - w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); @@ -137,13 +138,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enumerate_ht_chain(); } - // FIXME why is this executed again? ---> - sio_init(); - w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - enable_rom_decode(); - // <--- FIXME why is this executed again? - print_info("now booting... real_main\n"); if (bist == 0) diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index a57f9f7..a252e00 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -33,7 +33,9 @@ #include <lib.h> #include <spd.h> #include "southbridge/via/vt8237r/early_smbus.c" -#include "superio/winbond/w83697hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83697hf/w83697hf.h> + #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) static inline int spd_read_byte(unsigned device, unsigned address) @@ -85,7 +87,7 @@ void main(unsigned long bist) pci_write_config8(ctrl.d0f0, 0x4f, 0x01); w83697hf_set_clksel_48(SERIAL_DEV); - w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index fda1bb0..ef0cef3 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -42,7 +42,8 @@ #include "northbridge/via/vx800/raminit.h" #include "northbridge/via/vx800/raminit.c" #include "wakeup.h" -#include "superio/winbond/w83697hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83697hf/w83697hf.h> #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) @@ -385,7 +386,7 @@ void main(unsigned long bist) pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01); /* EmbedComInit(); */ w83697hf_set_clksel_48(DUMMY_DEV); - w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* enable_vx800_serial(); */ /* diff --git a/src/superio/winbond/w83697hf/Makefile.inc b/src/superio/winbond/w83697hf/Makefile.inc index cf03273..73e5b46 100644 --- a/src/superio/winbond/w83697hf/Makefile.inc +++ b/src/superio/winbond/w83697hf/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_WINBOND_W83697HF) += early_serial.c ramstage-$(CONFIG_SUPERIO_WINBOND_W83697HF) += superio.c - diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index e435645..8efe303 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -45,7 +45,8 @@ void w83697hf_set_clksel_48(device_t dev) pnp_exit_ext_func_mode(dev); } -static void w83697hf_enable_serial(device_t dev, u16 iobase) +/* Depreciated, use winbond_enable_serial() */ +void w83697hf_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h index 7e353e2..f711786 100644 --- a/src/superio/winbond/w83697hf/w83697hf.h +++ b/src/superio/winbond/w83697hf/w83697hf.h @@ -18,8 +18,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_WINBOND_W83697HF_W83697HF_H -#define SUPERIO_WINBOND_W83697HF_W83697HF_H +#ifndef SUPERIO_WINBOND_W83697HF_H +#define SUPERIO_WINBOND_W83697HF_H + +#include <arch/io.h> #define W83697HF_FDC 0 /* Floppy */ #define W83697HF_PP 1 /* Parallel port */ @@ -33,4 +35,8 @@ #define W83697HF_HWM 11 /* Hardware monitor */ void w83697hf_set_clksel_48(device_t); -#endif + +/* Depreciated, use winbond_enable_serial() */ +void w83697hf_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_WINBOND_W83697HF_H */

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Patch set updated for coreboot: 2a197bb superio/winbond/w83627uhg: Depreciate romstage component
by Edward O'Callaghan 21 May '14

21 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5725 -gerrit commit 2a197bbc765761e9d806fd9d5dedad5337bd0d9a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue May 13 23:52:30 2014 +1000 superio/winbond/w83627uhg: Depreciate romstage component Depreciate the model specific early_serial.c romstage component for this Super I/O in favor of the recent generic winbond romstage framework. Convert dependent board to generic winbond serial init. Note the clock function is actually invalid since it never enters into PNP config mode to twiddle the register. Further, 48MHz is the default (page 9 of data-sheet) and so romstage.c need not do anything to the clock rate hence why it presumably works with this invalid function. Change-Id: I4706a1446c1b391b8390ac0361700ce6f15b9206 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asrock/imb-a180/romstage.c | 8 ++-- src/superio/winbond/w83627uhg/Makefile.inc | 1 - src/superio/winbond/w83627uhg/early_serial.c | 57 ---------------------------- src/superio/winbond/w83627uhg/w83627uhg.h | 2 +- 4 files changed, 5 insertions(+), 63 deletions(-) diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 5b64cf9..8ce496b 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -35,7 +35,8 @@ #include "southbridge/amd/agesa/hudson/hudson.h" #include "cpu/amd/agesa/s3_resume.h" #include "cbmem.h" -#include "superio/winbond/w83627uhg/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627uhg/w83627uhg.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1) @@ -80,9 +81,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x30); post_code(0x31); - /* Set w83627uhg to 48MHz and enable w83627uhg */ - w83627uhg_set_input_clk_sel(SERIAL_DEV, 0); - w83627uhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } diff --git a/src/superio/winbond/w83627uhg/Makefile.inc b/src/superio/winbond/w83627uhg/Makefile.inc index f3d04b9..7bb23c0 100644 --- a/src/superio/winbond/w83627uhg/Makefile.inc +++ b/src/superio/winbond/w83627uhg/Makefile.inc @@ -19,4 +19,3 @@ ## ramstage-$(CONFIG_SUPERIO_WINBOND_W83627UHG) += superio.c - diff --git a/src/superio/winbond/w83627uhg/early_serial.c b/src/superio/winbond/w83627uhg/early_serial.c deleted file mode 100644 index bfd08a3..0000000 --- a/src/superio/winbond/w83627uhg/early_serial.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Dynon Avionics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include "w83627uhg.h" - -static void pnp_enter_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_ext_func_mode(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -/** Set the input clock to 24 or 48 MHz. */ -static void w83627uhg_set_input_clk_sel(device_t dev, u8 speed_24mhz) -{ - u8 value; - - value = pnp_read_config(dev, 0x24); - value &= ~(1 << 6); - if (!speed_24mhz) - value |= (1 << 6); - pnp_write_config(dev, 0x24, value); -} - -static void w83627uhg_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/winbond/w83627uhg/w83627uhg.h b/src/superio/winbond/w83627uhg/w83627uhg.h index f5442bc..1925a57 100644 --- a/src/superio/winbond/w83627uhg/w83627uhg.h +++ b/src/superio/winbond/w83627uhg/w83627uhg.h @@ -37,4 +37,4 @@ #define W83627UHG_SP5 14 /* Com5 */ #define W83627UHG_SP6 15 /* Com6 */ -#endif +#endif /* SUPERIO_WINBOND_W83627UHG_W83627UHG_H */

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Patch merged into coreboot/master: 2c9e370 mainboard/ibase/mb899: Sanitize headers
by gerrit＠coreboot.org 20 May '14

20 May '14

the following patch was just integrated into master: commit 2c9e3706469e65629d6e74b5a43df9277f176933 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed May 21 06:51:15 2014 +1000 mainboard/ibase/mb899: Sanitize headers These are not local headers. Change-Id: Ie0b0a682565a08dbfa089986dc7860fdb0846949 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5796 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> See http://review.coreboot.org/5796 for details. -gerrit

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Patch merged into coreboot/master: 0deb355 vendorcode/amd/agesa: unsigned enum is strictly positive
by gerrit＠coreboot.org 20 May '14

20 May '14

the following patch was just integrated into master: commit 0deb355d0e7f042cbcf6d74937b39729c7eaac0f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 15 21:07:16 2014 +1000 vendorcode/amd/agesa: unsigned enum is strictly positive The typedef'ed BIT_FIELD_NAME enum is type unsigned. The parameter 'FieldName' is decleared with type BIT_FIELD_NAME and thus the redudant comparison of unsigned enum expression >= 0 is always true. BIT_FIELD_NAME is declared in vendorcode/amd/agesa/f14/Proc/Mem/mm.h Change-Id: Id2f03596c44b68e861e939f3528256d4b08c45ce Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5757 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/5757 for details. -gerrit

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Patch set updated for coreboot: a662019 vendorcode/amd/agesa: unsigned enum is strictly positive
by Edward O'Callaghan 20 May '14

20 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5757 -gerrit commit a662019dd54a9dc124d24a1c0e3bdbeb460060e4 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 15 21:07:16 2014 +1000 vendorcode/amd/agesa: unsigned enum is strictly positive The typedef'ed BIT_FIELD_NAME enum is type unsigned. The parameter 'FieldName' is decleared with type BIT_FIELD_NAME and thus the redudant comparison of unsigned enum expression >= 0 is always true. BIT_FIELD_NAME is declared in vendorcode/amd/agesa/f14/Proc/Mem/mm.h Change-Id: Id2f03596c44b68e861e939f3528256d4b08c45ce Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c index f85e56d..e92dec0 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c @@ -17,7 +17,7 @@ * * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -25,10 +25,10 @@ * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -39,7 +39,7 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * *************************************************************************** * */ @@ -187,7 +187,7 @@ MemNCmnGetSetFieldON ( UINT8 Instance; Value = 0; - if ((FieldName < BFEndOfList) && (FieldName >= 0)) { + if (FieldName < BFEndOfList) { Address = NBPtr->NBRegTable[FieldName]; if (Address) { Lowbit = TSEFO_END (Address);

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Patch merged into coreboot/master: 8a661ed amd/cimx/sb?00/SATA.c: Integer overflow in loop condition
by gerrit＠coreboot.org 20 May '14

20 May '14

the following patch was just integrated into master: commit 8a661ed788ff1373015a5c6b705e2e32b63ebe4a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed May 21 09:42:56 2014 +1000 amd/cimx/sb?00/SATA.c: Integer overflow in loop condition The conditional comparison in the for-loop construct with the constant 300000 has an index incrementor of type 'UINT16' (aka 'unsigned short') which is always true. Change-Id: I932c168742163be4038728fb40833231a447fa78 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5799 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/5799 for details. -gerrit

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New patch to review for coreboot: 9151a86 amd/cimx/sb?00/SATA.c: Integer overflow in loop condition
by Edward O'Callaghan 20 May '14

20 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5799 -gerrit commit 9151a86bb2b29b34ed0f6572ebc86305126e3b22 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed May 21 09:42:56 2014 +1000 amd/cimx/sb?00/SATA.c: Integer overflow in loop condition The conditional comparison in the for-loop construct with the constant 300000 has an index incrementor of type 'UINT16' (aka 'unsigned short') which is always true. Change-Id: I932c168742163be4038728fb40833231a447fa78 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/cimx/sb700/SATA.c | 2 +- src/vendorcode/amd/cimx/sb800/SATA.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/amd/cimx/sb700/SATA.c b/src/vendorcode/amd/cimx/sb700/SATA.c index 09d4923..d503239 100644 --- a/src/vendorcode/amd/cimx/sb700/SATA.c +++ b/src/vendorcode/amd/cimx/sb700/SATA.c @@ -238,7 +238,7 @@ void sataInitAfterPciEnum(AMDSBCFG* pConfig){ void sataDriveDetection(AMDSBCFG* pConfig, UINT32 ddBar5){ UINT32 ddVar0; UINT8 dbPortNum, dbVar0; - UINT16 dwIoBase, dwVar0; + UINT32 dwIoBase, dwVar0; TRACE((DMSG_SB_TRACE, "CIMx - Entering sata drive detection procedure\n\n")); TRACE((DMSG_SB_TRACE, "SATA BAR5 is %X \n", ddBar5)); diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c index a301208..73f2968 100644 --- a/src/vendorcode/amd/cimx/sb800/SATA.c +++ b/src/vendorcode/amd/cimx/sb800/SATA.c @@ -568,7 +568,7 @@ sataDriveDetection ( UINT8 dbPortNum; UINT8 dbVar0; UINT16 dwIoBase; - UINT16 dwVar0; + UINT32 dwVar0; if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) ) { for ( dbPortNum = 0; dbPortNum < 4; dbPortNum++ ) { ReadMEM (*pBar5 + SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0);

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Patch merged into coreboot/master: 03b00e9 baytrail: Fix some minor errors in FSP
by gerrit＠coreboot.org 20 May '14

20 May '14

the following patch was just integrated into master: commit 03b00e9675d08d01ff831f20e8e48d19e93494af Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue May 20 15:52:08 2014 -0700 baytrail: Fix some minor errors in FSP - Duplicate declaration of GetFspReservedMemoryFromGuid - Corrupt line that was only compiled for a southbridge that no board in coreboot currently uses. (thanks for Mike Hibbett <mhibbett(a)ircona.com> for pointing this out) Change-Id: I847e807272acbaa93c87a89c0d2f94829c9121e6 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/5798 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> See http://review.coreboot.org/5798 for details. -gerrit

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