coreboot-gerrit April 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 28c6437 console: Add console for GDB
by Kyösti Mälkki 11 Apr '14

11 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5343 -gerrit commit 28c6437002013edda9a2f13f74e006a172954711 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Apr 4 15:05:28 2014 +0300 console: Add console for GDB Change-Id: I90e05e8132889e788b92e055ee191f35add43bbc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/c_start.S | 1 + src/arch/x86/lib/exception.c | 13 +++++++++++-- src/console/console.c | 24 ++++++++++++++++++++++++ src/include/console/streams.h | 6 ++++++ src/include/console/uart.h | 8 ++++++++ src/include/console/usb.h | 15 +++++++++++++-- 6 files changed, 63 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S index faea22d..675a09c 100644 --- a/src/arch/x86/lib/c_start.S +++ b/src/arch/x86/lib/c_start.S @@ -86,6 +86,7 @@ _start: post_code(POST_PRE_HARDWAREMAIN) /* post fe */ #if CONFIG_GDB_WAIT + call gdb_hw_init call gdb_stub_breakpoint #endif call main diff --git a/src/arch/x86/lib/exception.c b/src/arch/x86/lib/exception.c index 9756949..f64b2e7 100644 --- a/src/arch/x86/lib/exception.c +++ b/src/arch/x86/lib/exception.c @@ -1,4 +1,5 @@ #include <console/console.h> +#include <console/streams.h> #include <string.h> #if CONFIG_GDB_STUB @@ -217,12 +218,17 @@ static char out_buffer[BUFMAX]; static inline void stub_putc(int ch) { - console_tx_byte(ch); + gdb_tx_byte(ch); +} + +static inline void stub_flush(void) +{ + gdb_tx_flush(); } static inline int stub_getc(void) { - return console_rx_byte(); + return gdb_rx_byte(); } static int hex(char ch) @@ -322,9 +328,11 @@ static int get_packet(char *buffer) if (checksum != xmitcsum) { stub_putc('-'); /* failed checksum */ + stub_flush(); } else { stub_putc('+'); /* successful transfer */ + stub_flush(); } } } while(checksum != xmitcsum); @@ -353,6 +361,7 @@ static void put_packet(char *buffer) stub_putc('#'); stub_putc(hexchars[checksum >> 4]); stub_putc(hexchars[checksum % 16]); + stub_flush(); } while ((stub_getc() & 0x7f) != '+'); diff --git a/src/console/console.c b/src/console/console.c index cd72596..396ca07 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -54,6 +54,30 @@ void console_tx_flush(void) __usb_tx_flush(); } + +#if CONFIG_GDB_STUB && !defined(__SMM__) +void gdb_hw_init(void) +{ + __gdb_hw_init(); +} + +void gdb_tx_byte(unsigned char byte) +{ + __gdb_tx_byte(byte); +} + +void gdb_tx_flush(void) +{ + __gdb_tx_flush(); +} + +unsigned char gdb_rx_byte(void) +{ + return __gdb_rx_byte(); +} +#endif + + void console_tx_nibble(unsigned nibble) { unsigned char digit; diff --git a/src/include/console/streams.h b/src/include/console/streams.h index 9d4d3fc..fb168da 100644 --- a/src/include/console/streams.h +++ b/src/include/console/streams.h @@ -22,6 +22,12 @@ void console_hw_init(void); void console_tx_byte(unsigned char byte); void console_tx_flush(void); +/* For remote GDB debugging. */ +void gdb_hw_init(void); +void gdb_tx_byte(unsigned char byte); +void gdb_tx_flush(void); +unsigned char gdb_rx_byte(void); + /* Helpers for ROMCC console. */ void console_tx_nibble(unsigned nibble); void console_tx_hex8(unsigned char value); diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 21aacd0..14a9ba9 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -69,4 +69,12 @@ static inline void __uart_tx_byte(u8 data) {} static inline void __uart_tx_flush(void) {} #endif +#if 0 && CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) +#define CONFIG_UART_FOR_GDB 0 +static inline void __gdb_hw_init(void) { uart_init(CONFIG_UART_FOR_GDB); } +static inline void __gdb_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_GDB, data); } +static inline void __gdb_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_GDB); } +static inline u8 __gdb_rx_byte(void) { return uart_rx_byte(CONFIG_UART_FOR_GDB); } +#endif + #endif /* CONSOLE_UART_H */ diff --git a/src/include/console/usb.h b/src/include/console/usb.h index e64e43e..42887a8 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -34,14 +34,25 @@ int usb_can_rx_byte(int idx); #define __CONSOLE_USB_ENABLE__ CONFIG_CONSOLE_USB && \ ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE) +#define USB_PIPE_FOR_CONSOLE 0 +#define USB_PIPE_FOR_GDB 0 + #if __CONSOLE_USB_ENABLE__ static inline void __usbdebug_init(void) { usbdebug_init(); } -static inline void __usb_tx_byte(u8 data) { usb_tx_byte(0, data); } -static inline void __usb_tx_flush(void) { usb_tx_flush(0); } +static inline void __usb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_CONSOLE, data); } +static inline void __usb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_CONSOLE); } #else static inline void __usbdebug_init(void) {} static inline void __usb_tx_byte(u8 data) {} static inline void __usb_tx_flush(void) {} #endif +#if 0 && CONFIG_GDB_STUB_USB && \ + ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE) +static inline void __gdb_hw_init(void) { usbdebug_init(); } +static inline void __gdb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_GDB, data); } +static inline void __gdb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_GDB); } +static inline u8 __gdb_rx_byte(void) { return usb_rx_byte(USB_PIPE_FOR_GDB); } +#endif + #endif /* _CONSOLE_USB_H_ */

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Patch set updated for coreboot: 849f11c console: Simplify the enable rules
by Kyösti Mälkki 11 Apr '14

11 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5341 -gerrit commit 849f11cd0d87ff479996c94e3c395b0432a47269 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 26 15:19:04 2014 +0200 console: Simplify the enable rules Consoles on CBMEM and USB have somewhat complex rules and dependencies when they can be active. Use simple variables to test which stage of boot is being built for each console. Change-Id: I2489e7731d07ca7d5dd2ea8b6501c73f05d6edd8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/console.c | 62 ++++++++++--------------------------- src/include/console/cbmem_console.h | 23 +++++++++++--- src/include/console/ne2k.h | 15 +++++++++ src/include/console/qemu_debugcon.h | 11 +++++++ src/include/console/spkmodem.h | 11 +++++++ src/include/console/uart.h | 14 +++++++++ src/include/console/usb.h | 16 ++++++++++ 7 files changed, 102 insertions(+), 50 deletions(-) diff --git a/src/console/console.c b/src/console/console.c index f66cd3f..cd72596 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -27,59 +27,31 @@ void console_hw_init(void) { -#if CONFIG_CONSOLE_SERIAL - uart_init(); -#endif -#if CONFIG_CONSOLE_NE2K - ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif -#if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__) && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) - cbmemc_init(); -#endif -#if CONFIG_SPKMODEM - spkmodem_init(); -#endif -#if CONFIG_CONSOLE_USB && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) - usbdebug_init(); -#endif -#if CONFIG_CONSOLE_QEMU_DEBUGCON - qemu_debugcon_init(); -#endif + __cbmemc_init(); + __spkmodem_init(); + __qemu_debugcon_init(); + + __uart_init(); + __ne2k_init(); + __usbdebug_init(); } void console_tx_byte(unsigned char byte) { -#if CONFIG_CONSOLE_SERIAL - uart_tx_byte(byte); -#endif -#if CONFIG_CONSOLE_USB && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) - usb_tx_byte(0, byte); -#endif -#if CONFIG_CONSOLE_NE2K - ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); -#endif -#if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__) && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) - cbmemc_tx_byte(byte); -#endif -#if CONFIG_SPKMODEM - spkmodem_tx_byte(byte); -#endif -#if CONFIG_CONSOLE_QEMU_DEBUGCON - qemu_debugcon_tx_byte(byte); -#endif + __cbmemc_tx_byte(byte); + __spkmodem_tx_byte(byte); + __qemu_debugcon_tx_byte(byte); + + __uart_tx_byte(byte); + __ne2k_tx_byte(byte); + __usb_tx_byte(byte); } void console_tx_flush(void) { -#if CONFIG_CONSOLE_SERIAL - uart_tx_flush(); -#endif -#if CONFIG_CONSOLE_NE2K - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif -#if CONFIG_CONSOLE_USB && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) - usb_tx_flush(0); -#endif + __uart_tx_flush(); + __ne2k_tx_flush(); + __usb_tx_flush(); } void console_tx_nibble(unsigned nibble) diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index 4f4a54f..a7f48c9 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -19,14 +19,27 @@ #ifndef _CONSOLE_CBMEM_CONSOLE_H_ #define _CONSOLE_CBMEM_CONSOLE_H_ -#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__) +#include <arch/rules.h> +#include <stdint.h> + void cbmemc_init(void); -void cbmemc_reinit(void); void cbmemc_tx_byte(unsigned char data); + +#if CONFIG_CONSOLE_CBMEM +void cbmemc_reinit(void); +#else +static inline void cbmemc_reinit(void) {} +#endif + +#define __CBMEM_CONSOLE_ENABLE__ CONFIG_CONSOLE_CBMEM && \ + ((ENV_ROMSTAGE && CONFIG_EARLY_CBMEM_INIT) || ENV_RAMSTAGE) + +#if __CBMEM_CONSOLE_ENABLE__ +static inline void __cbmemc_init(void) { cbmemc_init(); } +static inline void __cbmemc_tx_byte(u8 data) { cbmemc_tx_byte(data); } #else -#define cbmemc_init() -#define cbmemc_reinit() -#define cbmemc_tx_byte(x) +static inline void __cbmemc_init(void) {} +static inline void __cbmemc_tx_byte(u8 data) {} #endif #endif diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h index cb3c1ec..508b5e5 100644 --- a/src/include/console/ne2k.h +++ b/src/include/console/ne2k.h @@ -19,6 +19,10 @@ #ifndef _NE2K_H__ #define _NE2K_H__ + +#include <arch/rules.h> +#include <stdint.h> + void ne2k_append_data(unsigned char *d, int len, unsigned int base); int ne2k_init(unsigned int eth_nic_base); void ne2k_transmit(unsigned int eth_nic_base); @@ -26,4 +30,15 @@ void ne2k_transmit(unsigned int eth_nic_base); #ifndef __ROMCC__ #define ne2k_append_data_byte(d, base) ne2k_append_data(&d, 1, base) #endif + +#if CONFIG_CONSOLE_NE2K && (ENV_ROMSTAGE || ENV_RAMSTAGE) +static inline void __ne2k_init(void) { ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); } +static inline void __ne2k_tx_byte(u8 data) { ne2k_append_data_byte(data, CONFIG_CONSOLE_NE2K_IO_PORT); } +static inline void __ne2k_tx_flush(void) { ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); } +#else +static inline void __ne2k_init(void) {} +static inline void __ne2k_tx_byte(u8 data) {} +static inline void __ne2k_tx_flush(void) {} +#endif + #endif /* _NE2K_H */ diff --git a/src/include/console/qemu_debugcon.h b/src/include/console/qemu_debugcon.h index 63b1455..8988e9e 100644 --- a/src/include/console/qemu_debugcon.h +++ b/src/include/console/qemu_debugcon.h @@ -1,7 +1,18 @@ #ifndef _QEMU_DEBUGCON_H_ #define _QEMU_DEBUGCON_H_ +#include <arch/rules.h> +#include <stdint.h> + void qemu_debugcon_init(void); void qemu_debugcon_tx_byte(unsigned char data); +#if CONFIG_CONSOLE_QEMU_DEBUGCON && (ENV_ROMSTAGE || ENV_RAMSTAGE) +static inline void __qemu_debugcon_init(void) { qemu_debugcon_init(); } +static inline void __qemu_debugcon_tx_byte(u8 data) { qemu_debugcon_tx_byte(data); } +#else +static inline void __qemu_debugcon_init(void) {} +static inline void __qemu_debugcon_tx_byte(u8 data) {} +#endif + #endif diff --git a/src/include/console/spkmodem.h b/src/include/console/spkmodem.h index 450dbe8..dbc1843 100644 --- a/src/include/console/spkmodem.h +++ b/src/include/console/spkmodem.h @@ -1,7 +1,18 @@ #ifndef SPKMODEM_H #define SPKMODEM_H 1 +#include <arch/rules.h> +#include <stdint.h> + void spkmodem_init(void); void spkmodem_tx_byte(unsigned char c); +#if CONFIG_SPKMODEM && (ENV_ROMSTAGE || ENV_RAMSTAGE) +static inline void __spkmodem_init(void) { spkmodem_init(); } +static inline void __spkmodem_tx_byte(u8 data) { spkmodem_tx_byte(data); } +#else +static inline void __spkmodem_init(void) {} +static inline void __spkmodem_tx_byte(u8 data) {} +#endif + #endif diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 4551408..2ea1931 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -20,6 +20,7 @@ #ifndef CONSOLE_UART_H #define CONSOLE_UART_H +#include <arch/rules.h> #include <stdint.h> /* Return the clock frequency UART uses as reference clock for @@ -55,4 +56,17 @@ static inline void *uart_platform_baseptr(int idx) void oxford_remap(unsigned int new_base); +#define __CONSOLE_SERIAL_ENABLE__ CONFIG_CONSOLE_SERIAL && \ + (ENV_ROMSTAGE || ENV_RAMSTAGE || (ENV_SMM && CONFIG_DEBUG_SMI)) + +#if __CONSOLE_SERIAL_ENABLE__ +static inline void __uart_init(void) { uart_init(); } +static inline void __uart_tx_byte(u8 data) { uart_tx_byte(data); } +static inline void __uart_tx_flush(void) { uart_tx_flush(); } +#else +static inline void __uart_init(void) {} +static inline void __uart_tx_byte(u8 data) {} +static inline void __uart_tx_flush(void) {} +#endif + #endif /* CONSOLE_UART_H */ diff --git a/src/include/console/usb.h b/src/include/console/usb.h index 9591135..e64e43e 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -21,6 +21,9 @@ #ifndef _CONSOLE_USB_H_ #define _CONSOLE_USB_H_ +#include <arch/rules.h> +#include <stdint.h> + int usbdebug_init(void); void usb_tx_byte(int idx, unsigned char data); @@ -28,4 +31,17 @@ void usb_tx_flush(int idx); unsigned char usb_rx_byte(int idx); int usb_can_rx_byte(int idx); +#define __CONSOLE_USB_ENABLE__ CONFIG_CONSOLE_USB && \ + ((ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE) || ENV_RAMSTAGE) + +#if __CONSOLE_USB_ENABLE__ +static inline void __usbdebug_init(void) { usbdebug_init(); } +static inline void __usb_tx_byte(u8 data) { usb_tx_byte(0, data); } +static inline void __usb_tx_flush(void) { usb_tx_flush(0); } +#else +static inline void __usbdebug_init(void) {} +static inline void __usb_tx_byte(u8 data) {} +static inline void __usb_tx_flush(void) {} +#endif + #endif /* _CONSOLE_USB_H_ */

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Patch set updated for coreboot: f9a2374 allwinner/a10: Hide SoC specific UART functions
by Kyösti Mälkki 11 Apr '14

11 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5469 -gerrit commit f9a23747a0beb9fdc873dd44f18037d324f970aa Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Apr 4 20:32:59 2014 +0300 allwinner/a10: Hide SoC specific UART functions If platform has a component coreboot has to communicate with using one of the UARTs, that device would not be part of the SoC and must not use functions specific to a10 UART. Also, a10 UART suppor should be changed to generic uart8250mem support for ARM. Change-Id: Ifacfc94dfde9979eae0b0cfb723a6eaa1fbcd659 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/allwinner/a10/uart.c | 40 ++++++++++++++++++++++++++---------- src/cpu/allwinner/a10/uart.h | 7 ------- src/cpu/allwinner/a10/uart_console.c | 28 +------------------------ 3 files changed, 30 insertions(+), 45 deletions(-) diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c index 1885ace..feccc82 100644 --- a/src/cpu/allwinner/a10/uart.c +++ b/src/cpu/allwinner/a10/uart.c @@ -13,12 +13,11 @@ /** * \brief Configure line control settings for UART */ -void a10_uart_configure(void *uart_base, u32 baud_rate, u8 data_bits, +static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bits, enum uart_parity parity, u8 stop_bits) { u32 reg32; u16 div; - struct a10_uart *uart = uart_base; div = (u16) uart_baudrate_divisor(baud_rate, uart_platform_refclk(), 16); @@ -44,10 +43,8 @@ void a10_uart_configure(void *uart_base, u32 baud_rate, u8 data_bits, write32(reg32, &uart->lcr); } -void a10_uart_enable_fifos(void *uart_base) +static void a10_uart_enable_fifos(struct a10_uart *uart) { - struct a10_uart *uart = uart_base; - write32(UART_FCR_FIFO_EN, &uart->fcr); } @@ -70,10 +67,8 @@ static int rx_fifo_empty(struct a10_uart *uart) * * Blocks until at least a byte is available. */ -u8 a10_uart_rx_blocking(void *uart_base) +static u8 a10_uart_rx_blocking(struct a10_uart *uart) { - struct a10_uart *uart = uart_base; - while (rx_fifo_empty(uart)) ; return read32(&uart->rbr); @@ -84,11 +79,34 @@ u8 a10_uart_rx_blocking(void *uart_base) * * Blocks until there is space in the FIFO. */ -void a10_uart_tx_blocking(void *uart_base, u8 data) +static void a10_uart_tx_blocking(struct a10_uart *uart, u8 data) { - struct a10_uart *uart = uart_base; - while (tx_fifo_full(uart)) ; return write32(data, &uart->thr); } + + +void uart_init(int idx) +{ + struct a10_uart *uart_base = uart_platform_baseptr(idx); + + /* Use default 8N1 encoding */ + a10_uart_configure(uart_base, default_baudrate(), + 8, UART_PARITY_NONE, 1); + a10_uart_enable_fifos(uart_base); +} + +unsigned char uart_rx_byte(int idx) +{ + return a10_uart_rx_blocking(uart_platform_baseptr(idx)); +} + +void uart_tx_byte(int idx, unsigned char data) +{ + a10_uart_tx_blocking(uart_platform_baseptr(idx), data); +} + +void uart_tx_flush(int idx) +{ +} diff --git a/src/cpu/allwinner/a10/uart.h b/src/cpu/allwinner/a10/uart.h index 86ab487..aa94362 100644 --- a/src/cpu/allwinner/a10/uart.h +++ b/src/cpu/allwinner/a10/uart.h @@ -13,7 +13,6 @@ #ifndef CPU_ALLWINNER_A10_UART_H #define CPU_ALLWINNER_A10_UART_H -#include "memmap.h" #include <types.h> struct a10_uart { @@ -68,10 +67,4 @@ enum uart_parity { UART_PARITY_ODD, }; -void a10_uart_configure(void *uart_base, u32 baud_rate, u8 data_bits, - enum uart_parity parity, u8 stop_bits); -void a10_uart_enable_fifos(void *uart_base); -u8 a10_uart_rx_blocking(void *uart_base); -void a10_uart_tx_blocking(void *uart_base, u8 data); - #endif /* CPU_ALLWINNER_A10_UART_H */ diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c index bb5f41c..b787961 100644 --- a/src/cpu/allwinner/a10/uart_console.c +++ b/src/cpu/allwinner/a10/uart_console.c @@ -6,13 +6,11 @@ * Subject to the GNU GPL v2, or (at your option) any later version. */ -#include <config.h> #include <types.h> #include <console/uart.h> -#include <arch/io.h> #include <boot/coreboot_tables.h> -#include <cpu/allwinner/a10/uart.h> +#include "memmap.h" unsigned int uart_platform_base(int idx) { @@ -29,30 +27,6 @@ unsigned int uart_platform_refclk(void) return 24000000; } -void uart_init(int idx) -{ - void *uart_base = uart_platform_baseptr(idx); - - /* Use default 8N1 encoding */ - a10_uart_configure(uart_base, default_baudrate(), - 8, UART_PARITY_NONE, 1); - a10_uart_enable_fifos(uart_base); -} - -unsigned char uart_rx_byte(int idx) -{ - return a10_uart_rx_blocking(uart_platform_baseptr(idx)); -} - -void uart_tx_byte(int idx, unsigned char data) -{ - a10_uart_tx_blocking(uart_platform_baseptr(idx), data); -} - -void uart_tx_flush(int idx) -{ -} - #ifndef __PRE_RAM__ void uart_fill_lb(void *data) {

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Patch set updated for coreboot: 3a5296d jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA
by Edward O'Callaghan 11 Apr '14

11 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5484 -gerrit commit 3a5296d31c9730b2b1112cfabb6eb52e41adc4e7 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Apr 11 12:56:13 2014 +1000 jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA Replace usage of AGESA poor reinvention of memset/memcpy functions with the usual standard ones. Change-Id: Ibfe9ee253d57140b06a4fca6b47b2051308ad012 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- .../jetway/nf81-t56n-lf/PlatformGnbPcie.c | 26 +++----- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 76 ++++++++-------------- 2 files changed, 36 insertions(+), 66 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c index f60bc8f..46daf1c 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c @@ -21,6 +21,8 @@ #include "PlatformGnbPcieComplex.h" #include "BiosCallOuts.h" +#include <assert.h> +#include <string.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -167,25 +169,15 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; - LibAmdMemFill(BrazosPcieComplexListPtr, - 0, - sizeof(Brazos), - &InitEarly->StdHeader); + ASSERT(&(InitEarly->StdHeader) != NULL); - LibAmdMemFill(BrazosPciePortPtr, - 0, - sizeof(PortList), - &InitEarly->StdHeader); - - LibAmdMemFill(BrazosPcieDdiPtr, - 0, - sizeof(DdiList), - &InitEarly->StdHeader); - - LibAmdMemCopy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); - LibAmdMemCopy(BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); - LibAmdMemCopy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); + memset(BrazosPcieComplexListPtr, 0, sizeof(Brazos)); + memset(BrazosPciePortPtr, 0, sizeof(PortList)); + memset(BrazosPcieDdiPtr, 0, sizeof(DdiList)); + memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); + memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); + memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->PciePortList = \ (PCIe_PORT_DESCRIPTOR *) BrazosPciePortPtr; diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c index 4a5d9c1..2754170 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c @@ -25,6 +25,7 @@ #include <arch/acpi.h> #include <arch/io.h> +#include <assert.h> #include <cbmem.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> @@ -142,15 +143,11 @@ agesawrapper_amdinitreset ( AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESET_PARAMS AmdResetParams; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + ASSERT(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); + ASSERT(&(AmdResetParams.StdHeader) != NULL); + memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; AmdParamStruct.AllocationMethod = ByHost; @@ -176,12 +173,10 @@ agesawrapper_amdinitearly ( { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + ASSERT(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -229,10 +224,8 @@ agesawrapper_amdinitpost ( AMD_INTERFACE_PARAMS AmdParamStruct; BIOS_HEAP_MANAGER *BiosManagerPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + ASSERT(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -270,10 +263,8 @@ agesawrapper_amdinitenv ( PCI_ADDR PciAddress; UINT32 PciValue; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + ASSERT(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AllocationMethod = PostMemDram; @@ -397,10 +388,8 @@ agesawrapper_amdinitmid ( /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio (); - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + ASSERT(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AllocationMethod = PostMemDram; @@ -427,10 +416,8 @@ agesawrapper_amdinitlate ( AMD_INTERFACE_PARAMS AmdParamStruct; AMD_LATE_PARAMS * AmdLateParamsPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + ASSERT(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; @@ -482,10 +469,8 @@ agesawrapper_amdinitresume ( AMD_RESUME_PARAMS *AmdResumeParamsPtr; S3_DATA_TYPE S3DataType; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + ASSERT(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -524,10 +509,9 @@ agesawrapper_amds3laterestore ( AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; S3_DATA_TYPE S3DataType; - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); + ASSERT(&(AmdS3LateParams.StdHeader) != NULL); + memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.AllocationMethod = ByHost; AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; @@ -565,10 +549,8 @@ agesawrapper_amdS3Save ( AMD_INTERFACE_PARAMS AmdInterfaceParams; S3_DATA_TYPE S3DataType; - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); + ASSERT(&(AmdInterfaceParams.StdHeader) != NULL); + memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; @@ -623,10 +605,8 @@ agesawrapper_amdlaterunaptask ( AGESA_STATUS Status; AP_EXE_PARAMS ApExeParams; - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); + ASSERT(&(ApExeParams.StdHeader) != NULL); + memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS)); ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; @@ -652,10 +632,8 @@ agesawrapper_amdreadeventlog ( AGESA_STATUS Status; EVENT_PARAMS AmdEventParams; - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); + ASSERT(&(AmdEventParams.StdHeader) != NULL); + memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS)); AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.CalloutPtr = NULL;

1 0

Patch set updated for coreboot: 9930e39 jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA
by Edward O'Callaghan 11 Apr '14

11 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5484 -gerrit commit 9930e39c6169cca85b7aee0df79c726998699279 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Apr 11 12:56:13 2014 +1000 jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA NOTFORMERGE. Replace usage of AGESA poor reinvention of memset/memcpy functions with the usual standard ones. Change-Id: Ibfe9ee253d57140b06a4fca6b47b2051308ad012 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- .../jetway/nf81-t56n-lf/PlatformGnbPcie.c | 26 +++----- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 76 ++++++++-------------- 2 files changed, 36 insertions(+), 66 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c index f60bc8f..ab7d078 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c @@ -21,6 +21,8 @@ #include "PlatformGnbPcieComplex.h" #include "BiosCallOuts.h" +#include <assert.h> +#include <string.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -167,25 +169,15 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; - LibAmdMemFill(BrazosPcieComplexListPtr, - 0, - sizeof(Brazos), - &InitEarly->StdHeader); + ASSERT(&(InitEarly->StdHeader) != NULL); - LibAmdMemFill(BrazosPciePortPtr, - 0, - sizeof(PortList), - &InitEarly->StdHeader); - - LibAmdMemFill(BrazosPcieDdiPtr, - 0, - sizeof(DdiList), - &InitEarly->StdHeader); - - LibAmdMemCopy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); - LibAmdMemCopy(BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); - LibAmdMemCopy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); + memset(&BrazosPcieComplexListPtr, 0, sizeof(Brazos)); + memset(&BrazosPciePortPtr, 0, sizeof(PortList)); + memset(&BrazosPcieDdiPtr, 0, sizeof(DdiList)); + memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); + memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); + memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->PciePortList = \ (PCIe_PORT_DESCRIPTOR *) BrazosPciePortPtr; diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c index 4a5d9c1..2754170 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c @@ -25,6 +25,7 @@ #include <arch/acpi.h> #include <arch/io.h> +#include <assert.h> #include <cbmem.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> @@ -142,15 +143,11 @@ agesawrapper_amdinitreset ( AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESET_PARAMS AmdResetParams; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + ASSERT(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); + ASSERT(&(AmdResetParams.StdHeader) != NULL); + memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; AmdParamStruct.AllocationMethod = ByHost; @@ -176,12 +173,10 @@ agesawrapper_amdinitearly ( { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + ASSERT(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -229,10 +224,8 @@ agesawrapper_amdinitpost ( AMD_INTERFACE_PARAMS AmdParamStruct; BIOS_HEAP_MANAGER *BiosManagerPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + ASSERT(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -270,10 +263,8 @@ agesawrapper_amdinitenv ( PCI_ADDR PciAddress; UINT32 PciValue; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + ASSERT(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AllocationMethod = PostMemDram; @@ -397,10 +388,8 @@ agesawrapper_amdinitmid ( /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio (); - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + ASSERT(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AllocationMethod = PostMemDram; @@ -427,10 +416,8 @@ agesawrapper_amdinitlate ( AMD_INTERFACE_PARAMS AmdParamStruct; AMD_LATE_PARAMS * AmdLateParamsPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + ASSERT(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; @@ -482,10 +469,8 @@ agesawrapper_amdinitresume ( AMD_RESUME_PARAMS *AmdResumeParamsPtr; S3_DATA_TYPE S3DataType; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + ASSERT(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -524,10 +509,9 @@ agesawrapper_amds3laterestore ( AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; S3_DATA_TYPE S3DataType; - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); + ASSERT(&(AmdS3LateParams.StdHeader) != NULL); + memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.AllocationMethod = ByHost; AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; @@ -565,10 +549,8 @@ agesawrapper_amdS3Save ( AMD_INTERFACE_PARAMS AmdInterfaceParams; S3_DATA_TYPE S3DataType; - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); + ASSERT(&(AmdInterfaceParams.StdHeader) != NULL); + memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; @@ -623,10 +605,8 @@ agesawrapper_amdlaterunaptask ( AGESA_STATUS Status; AP_EXE_PARAMS ApExeParams; - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); + ASSERT(&(ApExeParams.StdHeader) != NULL); + memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS)); ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; @@ -652,10 +632,8 @@ agesawrapper_amdreadeventlog ( AGESA_STATUS Status; EVENT_PARAMS AmdEventParams; - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); + ASSERT(&(AmdEventParams.StdHeader) != NULL); + memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS)); AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.CalloutPtr = NULL;

1 0

Patch merged into coreboot/master: eb4920d intel/*bd82x6x/acpi/pch.asl: Correct name of field unit to GP03
by gerrit＠coreboot.org 11 Apr '14

11 Apr '14

the following patch was just integrated into master: commit eb4920df327fd7d3ac9e9f853768b15e9a02a9b1 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Apr 10 19:50:58 2014 +0200 intel/*bd82x6x/acpi/pch.asl: Correct name of field unit to GP03 GP0e does not fit into the naming scheme of the field units surrounding this field unit definition. Also the keys for e and 3 are close to each other supporting the theory that this is indeed a typo. Change-Id: I43cf288fe1e0240b33971073c1aa8a1db5762e31 Reported-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5483 Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5483 for details. -gerrit

1 0

Patch set updated for coreboot: 077599a jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA
by Edward O'Callaghan 11 Apr '14

11 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5484 -gerrit commit 077599a37214f06b28e6c57c4ae8069acc56f614 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Apr 11 12:56:13 2014 +1000 jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA NOTFORMERGE. Replace usage of AGESA poor reinvention of memset/memcpy functions with the usual standard ones. Change-Id: Ibfe9ee253d57140b06a4fca6b47b2051308ad012 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- .../jetway/nf81-t56n-lf/PlatformGnbPcie.c | 26 +++----- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 76 ++++++++-------------- 2 files changed, 36 insertions(+), 66 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c index f60bc8f..f44bc49 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c @@ -21,6 +21,8 @@ #include "PlatformGnbPcieComplex.h" #include "BiosCallOuts.h" +#include <assert.h> +#include <string.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -167,25 +169,15 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; - LibAmdMemFill(BrazosPcieComplexListPtr, - 0, - sizeof(Brazos), - &InitEarly->StdHeader); + ASSERT(&(InitEarly->StdHeader) != NULL); - LibAmdMemFill(BrazosPciePortPtr, - 0, - sizeof(PortList), - &InitEarly->StdHeader); - - LibAmdMemFill(BrazosPcieDdiPtr, - 0, - sizeof(DdiList), - &InitEarly->StdHeader); - - LibAmdMemCopy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); - LibAmdMemCopy(BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); - LibAmdMemCopy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); + memset(&BrazosPcieComplexListPtr, 0, sizeof(Brazos)); + memset(&BrazosPciePortPtr, 0, sizeof(PortList)); + memset(&BrazosPcieDdiPtr, 0, sizeof(DdiList)); + memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); + memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); + memcpy(BrazosPcieDdiPtr, &DdiList, sizeof(DdiList)); ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->PciePortList = \ (PCIe_PORT_DESCRIPTOR *) BrazosPciePortPtr; diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c index 4a5d9c1..2754170 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c @@ -25,6 +25,7 @@ #include <arch/acpi.h> #include <arch/io.h> +#include <assert.h> #include <cbmem.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> @@ -142,15 +143,11 @@ agesawrapper_amdinitreset ( AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESET_PARAMS AmdResetParams; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + ASSERT(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); + ASSERT(&(AmdResetParams.StdHeader) != NULL); + memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; AmdParamStruct.AllocationMethod = ByHost; @@ -176,12 +173,10 @@ agesawrapper_amdinitearly ( { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + ASSERT(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -229,10 +224,8 @@ agesawrapper_amdinitpost ( AMD_INTERFACE_PARAMS AmdParamStruct; BIOS_HEAP_MANAGER *BiosManagerPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + ASSERT(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -270,10 +263,8 @@ agesawrapper_amdinitenv ( PCI_ADDR PciAddress; UINT32 PciValue; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + ASSERT(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AllocationMethod = PostMemDram; @@ -397,10 +388,8 @@ agesawrapper_amdinitmid ( /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio (); - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + ASSERT(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AllocationMethod = PostMemDram; @@ -427,10 +416,8 @@ agesawrapper_amdinitlate ( AMD_INTERFACE_PARAMS AmdParamStruct; AMD_LATE_PARAMS * AmdLateParamsPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + ASSERT(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; @@ -482,10 +469,8 @@ agesawrapper_amdinitresume ( AMD_RESUME_PARAMS *AmdResumeParamsPtr; S3_DATA_TYPE S3DataType; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + ASSERT(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -524,10 +509,9 @@ agesawrapper_amds3laterestore ( AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; S3_DATA_TYPE S3DataType; - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); + ASSERT(&(AmdS3LateParams.StdHeader) != NULL); + memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.AllocationMethod = ByHost; AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; @@ -565,10 +549,8 @@ agesawrapper_amdS3Save ( AMD_INTERFACE_PARAMS AmdInterfaceParams; S3_DATA_TYPE S3DataType; - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); + ASSERT(&(AmdInterfaceParams.StdHeader) != NULL); + memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; @@ -623,10 +605,8 @@ agesawrapper_amdlaterunaptask ( AGESA_STATUS Status; AP_EXE_PARAMS ApExeParams; - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); + ASSERT(&(ApExeParams.StdHeader) != NULL); + memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS)); ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; @@ -652,10 +632,8 @@ agesawrapper_amdreadeventlog ( AGESA_STATUS Status; EVENT_PARAMS AmdEventParams; - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); + ASSERT(&(AmdEventParams.StdHeader) != NULL); + memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS)); AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.CalloutPtr = NULL;

1 0

Patch set updated for coreboot: 29a37a1 jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA
by Edward O'Callaghan 11 Apr '14

11 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5484 -gerrit commit 29a37a1e080030a9df2433ca7845b931de7295fc Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Apr 11 12:56:13 2014 +1000 jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA NOTFORMERGE. Replace usage of AGESA poor reinvention of memset/memcpy functions with the usual standard ones. Change-Id: Ibfe9ee253d57140b06a4fca6b47b2051308ad012 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- .../jetway/nf81-t56n-lf/PlatformGnbPcie.c | 26 +++----- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 74 ++++++++-------------- 2 files changed, 35 insertions(+), 65 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c index f60bc8f..0a893d5 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c @@ -21,6 +21,8 @@ #include "PlatformGnbPcieComplex.h" #include "BiosCallOuts.h" +#include <assert.h> +#include <string.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -167,25 +169,15 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; - LibAmdMemFill(BrazosPcieComplexListPtr, - 0, - sizeof(Brazos), - &InitEarly->StdHeader); + assert(&(InitEarly->StdHeader) != NULL); - LibAmdMemFill(BrazosPciePortPtr, - 0, - sizeof(PortList), - &InitEarly->StdHeader); - - LibAmdMemFill(BrazosPcieDdiPtr, - 0, - sizeof(DdiList), - &InitEarly->StdHeader); - - LibAmdMemCopy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); - LibAmdMemCopy(BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); - LibAmdMemCopy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); + memset(&BrazosPcieComplexListPtr, 0, sizeof(Brazos)); + memset(&BrazosPciePortPtr, 0, sizeof(PortList)); + memset(&BrazosPcieDdiPtr, 0, sizeof(DdiList)); + memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); + memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); + memcpy(BrazosPcieDdiPtr, &DdiList, sizeof(DdiList)); ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->PciePortList = \ (PCIe_PORT_DESCRIPTOR *) BrazosPciePortPtr; diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c index 4a5d9c1..47cabf9 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c @@ -25,6 +25,7 @@ #include <arch/acpi.h> #include <arch/io.h> +#include <assert.h> #include <cbmem.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> @@ -142,15 +143,11 @@ agesawrapper_amdinitreset ( AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESET_PARAMS AmdResetParams; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); + assert(&(AmdResetParams.StdHeader) != NULL); + memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; AmdParamStruct.AllocationMethod = ByHost; @@ -178,10 +175,8 @@ agesawrapper_amdinitearly ( AMD_INTERFACE_PARAMS AmdParamStruct; AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -229,10 +224,8 @@ agesawrapper_amdinitpost ( AMD_INTERFACE_PARAMS AmdParamStruct; BIOS_HEAP_MANAGER *BiosManagerPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -270,10 +263,8 @@ agesawrapper_amdinitenv ( PCI_ADDR PciAddress; UINT32 PciValue; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AllocationMethod = PostMemDram; @@ -397,10 +388,8 @@ agesawrapper_amdinitmid ( /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio (); - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AllocationMethod = PostMemDram; @@ -427,10 +416,8 @@ agesawrapper_amdinitlate ( AMD_INTERFACE_PARAMS AmdParamStruct; AMD_LATE_PARAMS * AmdLateParamsPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; @@ -482,10 +469,8 @@ agesawrapper_amdinitresume ( AMD_RESUME_PARAMS *AmdResumeParamsPtr; S3_DATA_TYPE S3DataType; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -524,10 +509,9 @@ agesawrapper_amds3laterestore ( AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; S3_DATA_TYPE S3DataType; - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); + assert(&(AmdS3LateParams.StdHeader) != NULL); + memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.AllocationMethod = ByHost; AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; @@ -565,10 +549,8 @@ agesawrapper_amdS3Save ( AMD_INTERFACE_PARAMS AmdInterfaceParams; S3_DATA_TYPE S3DataType; - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; @@ -623,10 +605,8 @@ agesawrapper_amdlaterunaptask ( AGESA_STATUS Status; AP_EXE_PARAMS ApExeParams; - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); + assert(&(ApExeParams.StdHeader) != NULL); + memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS)); ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; @@ -652,10 +632,8 @@ agesawrapper_amdreadeventlog ( AGESA_STATUS Status; EVENT_PARAMS AmdEventParams; - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); + assert(&(AmdEventParams.StdHeader) != NULL); + memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS)); AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.CalloutPtr = NULL;

1 0

Patch set updated for coreboot: e222c1a jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA
by Edward O'Callaghan 11 Apr '14

11 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5484 -gerrit commit e222c1af88fa85ab279a068fc3421a7b343d6ef8 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Apr 11 12:56:13 2014 +1000 jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA NOTFORMERGE. Replace usage of AGESA poor reinvention of memset/memcpy functions with the usual standard ones. Change-Id: Ibfe9ee253d57140b06a4fca6b47b2051308ad012 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- .../jetway/nf81-t56n-lf/PlatformGnbPcie.c | 25 +++----- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 73 ++++++++-------------- 2 files changed, 33 insertions(+), 65 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c index f60bc8f..bd6a9ee 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c @@ -21,6 +21,7 @@ #include "PlatformGnbPcieComplex.h" #include "BiosCallOuts.h" +#include <string.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE @@ -167,25 +168,15 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; - LibAmdMemFill(BrazosPcieComplexListPtr, - 0, - sizeof(Brazos), - &InitEarly->StdHeader); + assert(&(InitEarly->StdHeader) != NULL); - LibAmdMemFill(BrazosPciePortPtr, - 0, - sizeof(PortList), - &InitEarly->StdHeader); - - LibAmdMemFill(BrazosPcieDdiPtr, - 0, - sizeof(DdiList), - &InitEarly->StdHeader); - - LibAmdMemCopy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); - LibAmdMemCopy(BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); - LibAmdMemCopy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); + memset(&BrazosPcieComplexListPtr, 0, sizeof(Brazos)); + memset(&BrazosPciePortPtr, 0, sizeof(PortList)); + memset(&BrazosPcieDdiPtr, 0, sizeof(DdiList)); + memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); + memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); + memcpy(BrazosPcieDdiPtr, &DdiList, sizeof(DdiList)); ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->PciePortList = \ (PCIe_PORT_DESCRIPTOR *) BrazosPciePortPtr; diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c index 4a5d9c1..3a7460b 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c @@ -142,15 +142,11 @@ agesawrapper_amdinitreset ( AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESET_PARAMS AmdResetParams; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); + assert(&(AmdResetParams.StdHeader) != NULL); + memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; AmdParamStruct.AllocationMethod = ByHost; @@ -178,10 +174,8 @@ agesawrapper_amdinitearly ( AMD_INTERFACE_PARAMS AmdParamStruct; AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -229,10 +223,8 @@ agesawrapper_amdinitpost ( AMD_INTERFACE_PARAMS AmdParamStruct; BIOS_HEAP_MANAGER *BiosManagerPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -270,10 +262,8 @@ agesawrapper_amdinitenv ( PCI_ADDR PciAddress; UINT32 PciValue; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AllocationMethod = PostMemDram; @@ -397,10 +387,8 @@ agesawrapper_amdinitmid ( /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio (); - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AllocationMethod = PostMemDram; @@ -427,10 +415,8 @@ agesawrapper_amdinitlate ( AMD_INTERFACE_PARAMS AmdParamStruct; AMD_LATE_PARAMS * AmdLateParamsPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; @@ -482,10 +468,8 @@ agesawrapper_amdinitresume ( AMD_RESUME_PARAMS *AmdResumeParamsPtr; S3_DATA_TYPE S3DataType; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -524,10 +508,9 @@ agesawrapper_amds3laterestore ( AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; S3_DATA_TYPE S3DataType; - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); + assert(&(AmdS3LateParams.StdHeader) != NULL); + memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.AllocationMethod = ByHost; AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; @@ -565,10 +548,8 @@ agesawrapper_amdS3Save ( AMD_INTERFACE_PARAMS AmdInterfaceParams; S3_DATA_TYPE S3DataType; - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; @@ -623,10 +604,8 @@ agesawrapper_amdlaterunaptask ( AGESA_STATUS Status; AP_EXE_PARAMS ApExeParams; - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); + assert(&(ApExeParams.StdHeader) != NULL); + memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS)); ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; @@ -652,10 +631,8 @@ agesawrapper_amdreadeventlog ( AGESA_STATUS Status; EVENT_PARAMS AmdEventParams; - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); + assert(&(AmdEventParams.StdHeader) != NULL); + memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS)); AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.CalloutPtr = NULL;

1 0

New patch to review for coreboot: f9405ba jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA
by Edward O'Callaghan 11 Apr '14

11 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5484 -gerrit commit f9405ba6afb3087989dc7e36e91e32e5558cbe3b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Apr 11 12:56:13 2014 +1000 jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA NOTFORMERGE. Replace usage of AGESA poor reinvention of memset/memcpy functions with the usual standard ones. Change-Id: Ibfe9ee253d57140b06a4fca6b47b2051308ad012 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- .../jetway/nf81-t56n-lf/PlatformGnbPcie.c | 24 +++---- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 73 ++++++++-------------- 2 files changed, 32 insertions(+), 65 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c index f60bc8f..aa5ee9c 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c @@ -167,25 +167,15 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = { AllocHeapParams.BufferPtr += sizeof(PortList); BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; - LibAmdMemFill(BrazosPcieComplexListPtr, - 0, - sizeof(Brazos), - &InitEarly->StdHeader); + assert(&(InitEarly.StdHeader) != NULL); - LibAmdMemFill(BrazosPciePortPtr, - 0, - sizeof(PortList), - &InitEarly->StdHeader); - - LibAmdMemFill(BrazosPcieDdiPtr, - 0, - sizeof(DdiList), - &InitEarly->StdHeader); - - LibAmdMemCopy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos), &InitEarly->StdHeader); - LibAmdMemCopy(BrazosPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader); - LibAmdMemCopy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader); + memset(&BrazosPcieComplexListPtr, 0, sizeof(Brazos)); + memset(&BrazosPciePortPtr, 0, sizeof(PortList)); + memset(&BrazosPcieDdiPtr, 0, sizeof(DdiList)); + memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); + memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); + memcpy(BrazosPcieDdiPtr, &DdiList, sizeof(DdiList)); ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->PciePortList = \ (PCIe_PORT_DESCRIPTOR *) BrazosPciePortPtr; diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c index 4a5d9c1..3a7460b 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c @@ -142,15 +142,11 @@ agesawrapper_amdinitreset ( AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESET_PARAMS AmdResetParams; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); + assert(&(AmdResetParams.StdHeader) != NULL); + memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; AmdParamStruct.AllocationMethod = ByHost; @@ -178,10 +174,8 @@ agesawrapper_amdinitearly ( AMD_INTERFACE_PARAMS AmdParamStruct; AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -229,10 +223,8 @@ agesawrapper_amdinitpost ( AMD_INTERFACE_PARAMS AmdParamStruct; BIOS_HEAP_MANAGER *BiosManagerPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -270,10 +262,8 @@ agesawrapper_amdinitenv ( PCI_ADDR PciAddress; UINT32 PciValue; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; AmdParamStruct.AllocationMethod = PostMemDram; @@ -397,10 +387,8 @@ agesawrapper_amdinitmid ( /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio (); - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; AmdParamStruct.AllocationMethod = PostMemDram; @@ -427,10 +415,8 @@ agesawrapper_amdinitlate ( AMD_INTERFACE_PARAMS AmdParamStruct; AMD_LATE_PARAMS * AmdLateParamsPtr; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; AmdParamStruct.AllocationMethod = PostMemDram; @@ -482,10 +468,8 @@ agesawrapper_amdinitresume ( AMD_RESUME_PARAMS *AmdResumeParamsPtr; S3_DATA_TYPE S3DataType; - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; AmdParamStruct.AllocationMethod = PreMemHeap; @@ -524,10 +508,9 @@ agesawrapper_amds3laterestore ( AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; S3_DATA_TYPE S3DataType; - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); + assert(&(AmdS3LateParams.StdHeader) != NULL); + memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.AllocationMethod = ByHost; AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; @@ -565,10 +548,8 @@ agesawrapper_amdS3Save ( AMD_INTERFACE_PARAMS AmdInterfaceParams; S3_DATA_TYPE S3DataType; - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); + assert(&(AmdParamStruct.StdHeader) != NULL); + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdInterfaceParams.StdHeader.ImageBasePtr = 0; AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; @@ -623,10 +604,8 @@ agesawrapper_amdlaterunaptask ( AGESA_STATUS Status; AP_EXE_PARAMS ApExeParams; - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); + assert(&(ApExeParams.StdHeader) != NULL); + memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS)); ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; @@ -652,10 +631,8 @@ agesawrapper_amdreadeventlog ( AGESA_STATUS Status; EVENT_PARAMS AmdEventParams; - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); + assert(&(AmdEventParams.StdHeader) != NULL); + memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS)); AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.CalloutPtr = NULL;

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coreboot-gerrit April 2014