coreboot-gerrit April 2014

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New patch to review for coreboot: ed361dc jetway/nf81-t56n-lf: Avoid shouting type declarations
by Edward O'Callaghan 11 Apr '14

11 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5486 -gerrit commit ed361dc7698bb3378fffb9e4191d733db61e8eff Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Apr 12 04:12:14 2014 +1000 jetway/nf81-t56n-lf: Avoid shouting type declarations Try to use void and uint32_t in place of VOID and UINT32 respectively. Remove some useless type casts. Change-Id: I4bff96a222507fc35333488331c3f35ef1158132 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 58 ++++---- src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h | 40 +++--- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 174 +++++++++-------------- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h | 34 ++--- 4 files changed, 134 insertions(+), 172 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index e86b813..9255ab3 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -76,7 +76,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = }, }; -AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS GetBiosCallout (uint32_t Func, uint32_t Data, void *ConfigPtr) { UINTN i; AGESA_STATUS CalloutStatus; @@ -98,16 +98,16 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return CalloutStatus; } -AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS BiosAllocateBuffer (uint32_t Func, uint32_t Data, void *ConfigPtr) { - UINT32 AvailableHeapSize; + uint32_t AvailableHeapSize; UINT8 *BiosHeapBaseAddr; - UINT32 CurrNodeOffset; - UINT32 PrevNodeOffset; - UINT32 FreedNodeOffset; - UINT32 BestFitNodeOffset; - UINT32 BestFitPrevNodeOffset; - UINT32 NextFreeOffset; + uint32_t CurrNodeOffset; + uint32_t PrevNodeOffset; + uint32_t FreedNodeOffset; + uint32_t BestFitNodeOffset; + uint32_t BestFitPrevNodeOffset; + uint32_t NextFreeOffset; BIOS_BUFFER_NODE *CurrNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; BIOS_BUFFER_NODE *BestFitNodePtr; @@ -229,15 +229,15 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return AGESA_SUCCESS; } -AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS BiosDeallocateBuffer (uint32_t Func, uint32_t Data, void *ConfigPtr) { UINT8 *BiosHeapBaseAddr; - UINT32 AllocNodeOffset; - UINT32 PrevNodeOffset; - UINT32 NextNodeOffset; - UINT32 FreedNodeOffset; - UINT32 EndNodeOffset; + uint32_t AllocNodeOffset; + uint32_t PrevNodeOffset; + uint32_t NextNodeOffset; + uint32_t FreedNodeOffset; + uint32_t EndNodeOffset; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_BUFFER_NODE *PrevNodePtr; BIOS_BUFFER_NODE *FreedNodePtr; @@ -348,9 +348,9 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return AGESA_SUCCESS; } -AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS BiosLocateBuffer (uint32_t Func, uint32_t Data, void *ConfigPtr) { - UINT32 AllocNodeOffset; + uint32_t AllocNodeOffset; UINT8 *BiosHeapBaseAddr; BIOS_BUFFER_NODE *AllocNodePtr; BIOS_HEAP_MANAGER *BiosHeapBasePtr; @@ -382,7 +382,7 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } -AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS BiosRunFuncOnAp (uint32_t Func, uint32_t Data, void *ConfigPtr) { AGESA_STATUS Status; @@ -390,7 +390,7 @@ AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return Status; } -AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS BiosReset (uint32_t Func, uint32_t Data, void *ConfigPtr) { AGESA_STATUS Status; UINT8 Value; @@ -426,7 +426,7 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return Status; } -AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS BiosReadSpd (uint32_t Func, uint32_t Data, void *ConfigPtr) { AGESA_STATUS Status; #ifdef __PRE_RAM__ @@ -438,19 +438,19 @@ AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return Status; } -AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS BiosDefaultRet (uint32_t Func, uint32_t Data, void *ConfigPtr) { return AGESA_UNSUPPORTED; } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS BiosHookBeforeDQSTraining (uint32_t Func, uint32_t Data, void *ConfigPtr) { return AGESA_SUCCESS; } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS BiosHookBeforeDramInit (uint32_t Func, uint32_t Data, void *ConfigPtr) { /* Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. * Make sure the right speed settings are selected. @@ -460,26 +460,26 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS BiosHookBeforeDramInitRecovery (uint32_t Func, uint32_t Data, void *ConfigPtr) { return AGESA_SUCCESS; } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS BiosHookBeforeExitSelfRefresh (uint32_t Func, uint32_t Data, void *ConfigPtr) { return AGESA_SUCCESS; } /* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +AGESA_STATUS BiosGnbPcieSlotReset (uint32_t Func, uint32_t Data, void *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; PCIe_SLOT_RESET_INFO *ResetInfo; - UINT32 GpioMmioAddr; - UINT32 AcpiMmioAddr; + uint32_t GpioMmioAddr; + uint32_t AcpiMmioAddr; UINT8 Data8; UINT16 Data16; @@ -492,7 +492,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) WriteIo8(0xCD6, 0x26); Data8 = ReadIo8(0xCD7); Data16|=Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; + AcpiMmioAddr = (uint32_t)Data16 << 16; Status = AGESA_UNSUPPORTED; GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; switch (ResetInfo->ResetId) diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h index 40dc809..a2924fc 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h @@ -28,47 +28,47 @@ #define BSP_STACK_BASE_ADDR 0x30000 typedef struct _BIOS_HEAP_MANAGER { - //UINT32 AvailableSize; - UINT32 StartOfAllocatedNodes; - UINT32 StartOfFreedNodes; + //uint32_t AvailableSize; + uint32_t StartOfAllocatedNodes; + uint32_t StartOfFreedNodes; } BIOS_HEAP_MANAGER; typedef struct _BIOS_BUFFER_NODE { - UINT32 BufferHandle; - UINT32 BufferSize; - UINT32 NextNodeOffset; + uint32_t BufferHandle; + uint32_t BufferSize; + uint32_t NextNodeOffset; } BIOS_BUFFER_NODE; /* * Callouts */ -AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS GetBiosCallout (uint32_t Func, uint32_t Data, void *ConfigPtr); /* Required Callouts * AGESA Advanced Callouts - CPU */ -AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosAllocateBuffer (uint32_t Func, uint32_t Data, void *ConfigPtr); +AGESA_STATUS BiosDeallocateBuffer (uint32_t Func, uint32_t Data, void *ConfigPtr); +AGESA_STATUS BiosLocateBuffer (uint32_t Func, uint32_t Data, void *ConfigPtr); +AGESA_STATUS BiosRunFuncOnAp (uint32_t Func, uint32_t Data, void *ConfigPtr); +AGESA_STATUS BiosReset (uint32_t Func, uint32_t Data, void *ConfigPtr); +AGESA_STATUS BiosGetIdsInitData (uint32_t Func, uint32_t Data, void *ConfigPtr); /* AGESA Advanced Callouts - Memory */ -AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); +AGESA_STATUS BiosReadSpd (uint32_t Func,uint32_t Data,void *ConfigPtr); /* BIOS default RET */ -AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosDefaultRet (uint32_t Func, uint32_t Data, void *ConfigPtr); /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosHookBeforeDQSTraining (uint32_t Func, uint32_t Data, void *ConfigPtr); /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosHookBeforeDramInit (uint32_t Func, uint32_t Data, void *ConfigPtr); /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosHookBeforeDramInitRecovery (uint32_t Func, uint32_t Data, void *ConfigPtr); /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosHookBeforeExitSelfRefresh (uint32_t Func, uint32_t Data, void *ConfigPtr); /* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosGnbPcieSlotReset (uint32_t Func, uint32_t Data, void *ConfigPtr); #endif /* _BIOS_CALLOUT_H_ */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c index 2754170..ecf0d97 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c @@ -40,16 +40,16 @@ #define MMCONF_ENABLE 1 /* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; +void *DmiTable = NULL; +void *AcpiPstate = NULL; +void *AcpiSrat = NULL; +void *AcpiSlit = NULL; -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; +void *AcpiWheaMce = NULL; +void *AcpiWheaCmc = NULL; +void *AcpiAlib = NULL; -uint32_t agesawrapper_amdinitcpuio(void) +AGESA_STATUS agesawrapper_amdinitcpuio(void) { pci_devfn_t dev; msr_t msr; @@ -84,14 +84,10 @@ uint32_t agesawrapper_amdinitcpuio(void) return AGESA_SUCCESS; } -UINT32 -agesawrapper_amdinitmmio ( - VOID - ) +AGESA_STATUS agesawrapper_amdinitmmio(void) { - AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; + uint32_t PciData; PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; @@ -100,9 +96,9 @@ agesawrapper_amdinitmmio ( UINT8 Index; /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ + * Set the MMIO Configuration Base Address and Bus Range onto MMIO + * configuration base Address MSR register. + */ for (Index = 0; Index < 8; Index++) { BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; @@ -130,14 +126,10 @@ agesawrapper_amdinitmmio ( PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - Status = AGESA_SUCCESS; - return (UINT32)Status; + return AGESA_SUCCESS; } -UINT32 -agesawrapper_amdinitreset ( - VOID - ) +AGESA_STATUS agesawrapper_amdinitreset(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -163,13 +155,11 @@ agesawrapper_amdinitreset ( status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + + return status; } -UINT32 -agesawrapper_amdinitearly ( - VOID - ) +AGESA_STATUS agesawrapper_amdinitearly(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -193,19 +183,19 @@ agesawrapper_amdinitearly ( if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + return status; } -UINT32 GetHeapBase( +uint32_t GetHeapBase( AMD_CONFIG_PARAMS *StdHeader ) { - UINT32 heap; + uint32_t heap; #if CONFIG_HAVE_ACPI_RESUME /* Both romstage and ramstage has this S3 detect. */ if (acpi_get_sleep_type() == 3) - heap = (UINT32)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* himem_heap_base + high_stack_size */ + heap = (uint32_t)cbmem_find(CBMEM_ID_RESUME_SCRATCH) + (CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE); /* himem_heap_base + high_stack_size */ else #endif heap = BIOS_HEAP_START_ADDRESS; /* low mem */ @@ -213,14 +203,11 @@ UINT32 GetHeapBase( return heap; } -UINT32 -agesawrapper_amdinitpost ( - VOID - ) +AGESA_STATUS agesawrapper_amdinitpost(void) { AGESA_STATUS status; UINT16 i; - UINT32 *HeadPtr; + uint32_t *HeadPtr; AMD_INTERFACE_PARAMS AmdParamStruct; BIOS_HEAP_MANAGER *BiosManagerPtr; @@ -242,7 +229,7 @@ agesawrapper_amdinitpost ( /* Initialize heap space */ BiosManagerPtr = (BIOS_HEAP_MANAGER *)GetHeapBase(&AmdParamStruct.StdHeader); - HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); + HeadPtr = (uint32_t *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER)); for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) { *HeadPtr = 0x00000000; HeadPtr++; @@ -250,18 +237,15 @@ agesawrapper_amdinitpost ( BiosManagerPtr->StartOfAllocatedNodes = 0; BiosManagerPtr->StartOfFreedNodes = 0; - return (UINT32)status; + return status; } -UINT32 -agesawrapper_amdinitenv ( - VOID - ) +AGESA_STATUS agesawrapper_amdinitenv(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; PCI_ADDR PciAddress; - UINT32 PciValue; + uint32_t PciValue; ASSERT(&(AmdParamStruct.StdHeader) != NULL); memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); @@ -349,13 +333,10 @@ agesawrapper_amdinitenv ( LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader); AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + return status; } -VOID * -agesawrapper_getlateinitptr ( - int pick - ) +void * agesawrapper_getlateinitptr(int pick) { switch (pick) { case PICK_DMI: @@ -377,10 +358,7 @@ agesawrapper_getlateinitptr ( } } -UINT32 -agesawrapper_amdinitmid ( - VOID - ) +AGESA_STATUS agesawrapper_amdinitmid(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -404,15 +382,12 @@ agesawrapper_amdinitmid ( if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + return status; } -UINT32 -agesawrapper_amdinitlate ( - VOID - ) +AGESA_STATUS agesawrapper_amdinitlate(void) { - AGESA_STATUS Status; + AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_LATE_PARAMS * AmdLateParamsPtr; @@ -431,10 +406,10 @@ agesawrapper_amdinitlate ( printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); - Status = AmdInitLate (AmdLateParamsPtr); - if (Status != AGESA_SUCCESS) { + status = AmdInitLate (AmdLateParamsPtr); + if (status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); + ASSERT(status == AGESA_SUCCESS); } DmiTable = AmdLateParamsPtr->DmiTable; @@ -455,14 +430,11 @@ agesawrapper_amdinitlate ( * AmdReleaseStruct (&AmdLateParams); */ - return (UINT32)Status; + return status; } #if CONFIG_HAVE_ACPI_RESUME -UINT32 -agesawrapper_amdinitresume ( - VOID - ) +AGESA_STATUS agesawrapper_amdinitresume(void) { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; @@ -495,15 +467,12 @@ agesawrapper_amdinitresume ( if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); - return (UINT32)status; + return status; } -UINT32 -agesawrapper_amds3laterestore ( - VOID - ) +AGESA_STATUS agesawrapper_amds3laterestore(void) { - AGESA_STATUS Status; + AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdInterfaceParams; AMD_S3LATE_PARAMS AmdS3LateParams; AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; @@ -529,22 +498,19 @@ agesawrapper_amds3laterestore ( (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - Status = AmdS3LateRestore (AmdS3LateParamsPtr); - if (Status != AGESA_SUCCESS) { + status = AmdS3LateRestore (AmdS3LateParamsPtr); + if (status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); + ASSERT(status == AGESA_SUCCESS); } - return (UINT32)Status; + return status; } #ifndef __PRE_RAM__ -UINT32 -agesawrapper_amdS3Save ( - VOID - ) +AGESA_STATUS agesawrapper_amdS3Save(void) { - AGESA_STATUS Status; + AGESA_STATUS status; AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; AMD_INTERFACE_PARAMS AmdInterfaceParams; S3_DATA_TYPE S3DataType; @@ -564,15 +530,15 @@ agesawrapper_amdS3Save ( AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - Status = AmdS3Save (AmdS3SaveParamsPtr); - if (Status != AGESA_SUCCESS) { + status = AmdS3Save (AmdS3SaveParamsPtr); + if (status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); + ASSERT(status == AGESA_SUCCESS); } S3DataType = S3DataTypeNonVolatile; - Status = OemAgesaSaveS3Info ( + status = OemAgesaSaveS3Info ( S3DataType, AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, AmdS3SaveParamsPtr->S3DataBlock.NvStorage); @@ -580,7 +546,7 @@ agesawrapper_amdS3Save ( if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { S3DataType = S3DataTypeVolatile; - Status = OemAgesaSaveS3Info ( + status = OemAgesaSaveS3Info ( S3DataType, AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage @@ -590,19 +556,18 @@ agesawrapper_amdS3Save ( OemAgesaSaveMtrr(); AmdReleaseStruct (&AmdInterfaceParams); - return (UINT32)Status; + return status; } #endif /* #ifndef __PRE_RAM__ */ #endif /* CONFIG_HAVE_ACPI_RESUME */ -UINT32 -agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, - VOID *ConfigPtr +AGESA_STATUS agesawrapper_amdlaterunaptask ( + uint32_t Func, + uint32_t Data, + void *ConfigPtr ) { - AGESA_STATUS Status; + AGESA_STATUS status; AP_EXE_PARAMS ApExeParams; ASSERT(&(ApExeParams.StdHeader) != NULL); @@ -615,21 +580,18 @@ agesawrapper_amdlaterunaptask ( ApExeParams.FunctionNumber = Func; ApExeParams.RelatedDataBlock = ConfigPtr; - Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { + status = AmdLateRunApTask (&ApExeParams); + if (status != AGESA_SUCCESS) { agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); + ASSERT(status == AGESA_SUCCESS); } - return (UINT32)Status; + return status; } -UINT32 -agesawrapper_amdreadeventlog ( - VOID - ) +AGESA_STATUS agesawrapper_amdreadeventlog(void) { - AGESA_STATUS Status; + AGESA_STATUS status; EVENT_PARAMS AmdEventParams; ASSERT(&(AmdEventParams.StdHeader) != NULL); @@ -639,13 +601,13 @@ agesawrapper_amdreadeventlog ( AmdEventParams.StdHeader.CalloutPtr = NULL; AmdEventParams.StdHeader.Func = 0; AmdEventParams.StdHeader.ImageBasePtr = 0; - Status = AmdReadEventLog (&AmdEventParams); + status = AmdReadEventLog (&AmdEventParams); while (AmdEventParams.EventClass != 0) { printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); + status = AmdReadEventLog (&AmdEventParams); } - return (UINT32)Status; + return status; } diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h index ee31fcf..f10117f 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h @@ -42,27 +42,27 @@ enum { }; typedef struct { - UINT32 CalloutName; - AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr); + uint32_t CalloutName; + AGESA_STATUS (*CalloutPtr) (uint32_t Func, uint32_t Data, void* ConfigPtr); } BIOS_CALLOUT_STRUCT; -UINT32 agesawrapper_amdinitreset (void); -UINT32 agesawrapper_amdinitearly (void); -UINT32 agesawrapper_amdinitenv (void); -UINT32 agesawrapper_amdinitlate (void); -UINT32 agesawrapper_amdinitpost (void); -UINT32 agesawrapper_amdinitmid (void); +AGESA_STATUS agesawrapper_amdinitreset(void); +AGESA_STATUS agesawrapper_amdinitearly(void); +AGESA_STATUS agesawrapper_amdinitenv(void); +AGESA_STATUS agesawrapper_amdinitlate(void); +AGESA_STATUS agesawrapper_amdinitpost(void); +AGESA_STATUS agesawrapper_amdinitmid(void); -UINT32 agesawrapper_amdreadeventlog (void); +AGESA_STATUS agesawrapper_amdreadeventlog(void); -uint32_t agesawrapper_amdinitcpuio (void); -UINT32 agesawrapper_amdinitmmio (void); -UINT32 agesawrapper_amdinitresume (void); -UINT32 agesawrapper_amdS3Save (void); -UINT32 agesawrapper_amds3laterestore (void); -UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -void *agesawrapper_getlateinitptr (int pick); +AGESA_STATUS agesawrapper_amdinitcpuio(void); +AGESA_STATUS agesawrapper_amdinitmmio(void); +AGESA_STATUS agesawrapper_amdinitresume(void); +AGESA_STATUS agesawrapper_amdS3Save(void); +AGESA_STATUS agesawrapper_amds3laterestore(void); +AGESA_STATUS agesawrapper_amdlaterunaptask(uint32_t, uint32_t, void *); +void * agesawrapper_getlateinitptr(int); -UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); +uint32_t GetHeapBase(AMD_CONFIG_PARAMS *StdHeader); #endif /* _AGESAWRAPPER_H_ */

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Patch merged into coreboot/master: 4e6881f Add the Rangeley FSP include & srx directories
by gerrit＠coreboot.org 11 Apr '14

11 Apr '14

the following patch was just integrated into master: commit 4e6881f0ba917054405535ac922b9020a0eee4cd Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Apr 4 14:07:54 2014 -0600 Add the Rangeley FSP include & srx directories These are the .h and .c files from Intel that support interaction with the FSP. These have been modified from the FSP distribution only to strip trailing whitespace. Intel® Firmware Support Package for Intel® Atom™ Processor C2000 Product Family (Formerly Rangeley) "Intel® Firmware Support Package (Intel® FSP) provides key programming information for initializing Intel® silicon and can be easily integrated into a boot loader of the developer’s choice. It is easy to adopt, scalable to design, reduces time-to-market, and is economical to build." http://www.intel.com/fsp Change-Id: I9ed94cb92909c3681cc88bf10b85a9ba25e8fc55 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/5457 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/5457 for details. -gerrit

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Patch merged into coreboot/master: 954f388 Add the Bay Trail FSP include & srx directories
by gerrit＠coreboot.org 11 Apr '14

11 Apr '14

the following patch was just integrated into master: commit 954f3882f1ea8512de9a5a6a38569c36bffae405 Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Apr 4 13:23:41 2014 -0600 Add the Bay Trail FSP include & srx directories These are the .h and .c files from Intel that support interaction with the FSP. These have been modified from the FSP distribution only to strip trailing whitespace. Intel® Atom™ processor E3800 product family (formerly Bay Trail) "Intel® Firmware Support Package (Intel® FSP) provides key programming information for initializing Intel® silicon and can be easily integrated into a boot loader of the developer’s choice. It is easy to adopt, scalable to design, reduces time-to-market, and is economical to build." http://www.intel.com/fsp Change-Id: I0fa64dbaf640493cdb5e670e8d213a49d9e7dcfb Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/5456 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/5456 for details. -gerrit

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Patch merged into coreboot/master: debd765 Add the ivybridge i89xx FSP include & srx directories
by gerrit＠coreboot.org 11 Apr '14

11 Apr '14

the following patch was just integrated into master: commit debd7657548ed7cdc67dcabe3f6e69b33093a43a Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Apr 4 13:53:07 2014 -0600 Add the ivybridge i89xx FSP include & srx directories These are the .h and .c files from Intel that support interaction with the FSP. These have been modified from the FSP distribution only to strip trailing whitespace. Intel® Firmware Support Package for Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for Communications Infrastructure with Intel® Communications Chipset 89xx Series Platform Controller Hub (formerly Crystal Forest Refresh: Ivy Bridge Gladden and Cave Creek "Intel® Firmware Support Package (Intel® FSP) provides key programming information for initializing Intel® silicon and can be easily integrated into a boot loader of the developer’s choice. It is easy to adopt, scalable to design, reduces time-to-market, and is economical to build." http://www.intel.com/fsp Change-Id: Ib76e89b2d2f6407cf55a5a664da989c7a7e0eb23 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/5455 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/5455 for details. -gerrit

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Patch merged into coreboot/master: 18a40e0 Update vendorcode/intel/makefile for coming FSPs
by gerrit＠coreboot.org 11 Apr '14

11 Apr '14

the following patch was just integrated into master: commit 18a40e05334b650d8104787416afd8ba87f03987 Author: Martin Roth <gaumless(a)gmail.com> Date: Fri Apr 4 11:59:48 2014 -0600 Update vendorcode/intel/makefile for coming FSPs Other FSPs have more than just the initial fsphob.c source file. Add any .c files in the srx directory to the ramstage build. Change-Id: I5118bdcca44935b579809c4fc9566ab7914a6e4b Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/5454 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)google.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/5454 for details. -gerrit

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Patch set updated for coreboot: 8219ea9 console: Use romstage code for ramstage and SMM
by Kyösti Mälkki 11 Apr '14

11 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5338 -gerrit commit 8219ea9a16b4ed535375768578999f1227fcbe30 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 27 19:30:18 2014 +0200 console: Use romstage code for ramstage and SMM Console is arch-agnostic and there is no need for separate implementations for romstage and ramstage. For SMM there is console only if DEBUG_SMI is selected. Change-Id: I7028eeeff8bfbb9c8552972436b29a7508834d87 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/Makefile.inc | 2 -- src/arch/armv7/early_console.c | 40 -------------------------- src/arch/x86/lib/Makefile.inc | 1 - src/arch/x86/lib/romcc_console.c | 26 +++-------------- src/arch/x86/lib/romstage_console.c | 57 ------------------------------------- src/console/Makefile.inc | 3 +- src/console/console.c | 39 +++++++++++++++++++++---- src/console/init.c | 3 +- src/console/printk.c | 1 + src/cpu/x86/smm/Makefile.inc | 2 -- src/cpu/x86/smm/smiutil.c | 47 ------------------------------ src/include/console/console.h | 6 ++-- src/include/console/streams.h | 25 ++++++++++++++++ 13 files changed, 70 insertions(+), 182 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index dfd5164..f0adc0a 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -163,12 +163,10 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDD ramstage-y += exception.c ramstage-y += exception_asm.S -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += early_console.c bootblock-y += cache.c romstage-y += cache.c romstage-y += div0.c -romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c ramstage-y += div0.c #ramstage-y += interrupts.c diff --git a/src/arch/armv7/early_console.c b/src/arch/armv7/early_console.c deleted file mode 100644 index 599cbc7..0000000 --- a/src/arch/armv7/early_console.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/cbmem_console.h> -#include <console/uart.h> - -/* FIXME: need to make console driver more generic */ -void console_tx_byte(unsigned char byte) -{ -#if CONFIG_CONSOLE_SERIAL - uart_tx_byte(byte); -#endif -#if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__) - cbmemc_tx_byte(byte); -#endif -} - -void console_tx_flush(void) -{ -#if CONFIG_CONSOLE_SERIAL - uart_tx_flush(); -#endif -} diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index c173011..8b7418b 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -12,7 +12,6 @@ ramstage-y += rom_media.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S -romstage-$(CONFIG_EARLY_CONSOLE) += romstage_console.c romstage-y += cbfs_and_run.c romstage-y += memset.c romstage-y += memcpy.c diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 0557a52..454e0bc 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -17,8 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/uart.h> -#include <console/ne2k.h> +#include <console/streams.h> /* While in romstage, console loglevel is built-time constant. */ #define console_log_level(msg_level) (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= msg_level) @@ -31,25 +30,9 @@ #include "drivers/net/ne2k.c" #endif -static void __console_tx_byte(unsigned char byte) -{ -#if CONFIG_CONSOLE_SERIAL - uart_tx_byte(byte); -#endif -#if CONFIG_CONSOLE_NE2K - ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); -#endif -} - -static void __console_tx_flush(void) -{ -#if CONFIG_CONSOLE_SERIAL - uart_tx_flush(); -#endif -#if CONFIG_CONSOLE_NE2K - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif -} +#include <console/console.c> +#define __console_tx_byte console_tx_byte +#define __console_tx_flush console_tx_flush static void __console_tx_nibble(unsigned nibble) { @@ -118,7 +101,6 @@ static void __console_tx_string(int loglevel, const char *str) } /* if included by romcc, include the sources, too. romcc can't use prototypes */ -#include <console/console.c> #include <console/init.c> #include <console/post.c> #include <console/die.c> diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c deleted file mode 100644 index 58742a2..0000000 --- a/src/arch/x86/lib/romstage_console.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/cbmem_console.h> -#include <console/uart.h> -#include <console/usb.h> -#include <console/ne2k.h> -#include <console/spkmodem.h> - -void console_tx_byte(unsigned char byte) -{ -#if CONFIG_CONSOLE_SERIAL - uart_tx_byte(byte); -#endif -#if CONFIG_CONSOLE_USB && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) - usb_tx_byte(0, byte); -#endif -#if CONFIG_CONSOLE_NE2K - ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); -#endif -#if CONFIG_CONSOLE_CBMEM && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) - cbmemc_tx_byte(byte); -#endif -#if CONFIG_SPKMODEM - spkmodem_tx_byte(byte); -#endif -} - -void console_tx_flush(void) -{ -#if CONFIG_CONSOLE_SERIAL - uart_tx_flush(); -#endif -#if CONFIG_CONSOLE_NE2K - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif -#if CONFIG_CONSOLE_USB && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) - usb_tx_flush(0); -#endif -} diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index d59e44e..e3b3780 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -3,7 +3,7 @@ ramstage-y += init.c console.c ramstage-y += post.c ramstage-y += die.c -smm-$(CONFIG_DEBUG_SMI) += vtxprintf.c printk.c +smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c romstage-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c printk.c @@ -15,6 +15,7 @@ bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c printk.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += init.c console.c bootblock-y += die.c +$(obj)/console/init.smm.o : $(obj)/build.h $(obj)/console/init.ramstage.o : $(obj)/build.h $(obj)/console/init.romstage.o : $(obj)/build.h $(obj)/console/init.bootblock.o : $(obj)/build.h diff --git a/src/console/console.c b/src/console/console.c index 2f4eb5c..e0e505c 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -17,12 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> +#include <console/streams.h> #include <console/cbmem_console.h> #include <console/uart.h> #include <console/usb.h> #include <console/ne2k.h> #include <console/spkmodem.h> +#include <console/qemu_debugcon.h> void console_hw_init(void) { @@ -32,23 +33,51 @@ void console_hw_init(void) #if CONFIG_CONSOLE_NE2K ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); #endif -#if CONFIG_CONSOLE_CBMEM && CONFIG_EARLY_CBMEM_INIT && !defined(__BOOT_BLOCK__) +#if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__) && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) cbmemc_init(); #endif #if CONFIG_SPKMODEM spkmodem_init(); #endif -#if CONFIG_CONSOLE_USB && CONFIG_USBDEBUG_IN_ROMSTAGE && !defined(__BOOT_BLOCK__) +#if CONFIG_CONSOLE_USB && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) usbdebug_init(); #endif +#if CONFIG_CONSOLE_QEMU_DEBUGCON + qemu_debugcon_init(); +#endif } -#ifndef __PRE_RAM__ void console_tx_byte(unsigned char byte) { +#if CONFIG_CONSOLE_SERIAL + uart_tx_byte(byte); +#endif +#if CONFIG_CONSOLE_USB && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) + usb_tx_byte(0, byte); +#endif +#if CONFIG_CONSOLE_NE2K + ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); +#endif +#if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__) && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) + cbmemc_tx_byte(byte); +#endif +#if CONFIG_SPKMODEM + spkmodem_tx_byte(byte); +#endif +#if CONFIG_CONSOLE_QEMU_DEBUGCON + qemu_debugcon_tx_byte(byte); +#endif } void console_tx_flush(void) { -} +#if CONFIG_CONSOLE_SERIAL + uart_tx_flush(); #endif +#if CONFIG_CONSOLE_NE2K + ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); +#endif +#if CONFIG_CONSOLE_USB && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) + usb_tx_flush(0); +#endif +} diff --git a/src/console/init.c b/src/console/init.c index d7c8cc3..8bdb2cc 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -22,6 +22,7 @@ #include <build.h> #include <console/console.h> #include <console/uart.h> +#include <console/streams.h> #include <option.h> #if CONFIG_EARLY_PCI_BRIDGE @@ -46,7 +47,7 @@ void console_init(void) console_loglevel=CONFIG_DEFAULT_CONSOLE_LOGLEVEL; #endif -#if CONFIG_EARLY_PCI_BRIDGE +#if CONFIG_EARLY_PCI_BRIDGE && !defined(__SMM__) pci_early_bridge_init(); #endif diff --git a/src/console/printk.c b/src/console/printk.c index 2fa160b..40ea404 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -10,6 +10,7 @@ #include <smp/spinlock.h> #include <console/vtxprintf.h> #include <console/console.h> +#include <console/streams.h> #include <trace.h> DECLARE_SPIN_LOCK(console_lock) diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index bb9c11d..9720630 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -22,7 +22,6 @@ ramstage-$(CONFIG_BACKUP_DEFAULT_SMM_REGION) += backup_default_smm.c ifeq ($(CONFIG_SMM_MODULES),y) smmstub-y += smm_stub.S -smm-y += smiutil.c smm-y += smm_module_handler.c ramstage-y += smm_module_loader.c @@ -79,7 +78,6 @@ SMM_LDSCRIPT := smm.ld endif smm-y += smihandler.c -smm-y += smiutil.c $(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(LIBGCC_FILE_NAME) $(CC) $(LDFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(smm-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c deleted file mode 100644 index 644cab7..0000000 --- a/src/cpu/x86/smm/smiutil.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/uart.h> - -#if CONFIG_DEBUG_SMI -void console_tx_flush(void) -{ -} - -void console_tx_byte(unsigned char byte) -{ -#if CONFIG_CONSOLE_SERIAL - uart_tx_byte(byte); -#endif -} -#endif - -void console_init(void) -{ -#if CONFIG_DEBUG_SMI - console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; -#if CONFIG_CONSOLE_SERIAL - uart_init(); -#endif -#endif -} - diff --git a/src/include/console/console.h b/src/include/console/console.h index 0ebd1b7..54e4545 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -26,10 +26,6 @@ #ifndef __ROMCC__ int console_log_level(int msg_level); -void console_init(void); -void console_hw_init(void); -void console_tx_byte(unsigned char byte); -void console_tx_flush(void); void post_code(u8 value); #if CONFIG_CMOS_POST_EXTRA void post_log_extra(u32 value); @@ -52,9 +48,11 @@ void __attribute__ ((noreturn)) die(const char *msg); /* Do nothing. */ static inline void printk(int LEVEL, const char *fmt, ...) {} static inline void do_putchar(unsigned char byte) {} +static inline void console_init(void) {} #else +void console_init(void); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); void do_putchar(unsigned char byte); diff --git a/src/include/console/streams.h b/src/include/console/streams.h new file mode 100644 index 0000000..288fade --- /dev/null +++ b/src/include/console/streams.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _CONSOLE_STREAMS_H_ +#define _CONSOLE_STREAMS_H_ + +void console_hw_init(void); +void console_tx_byte(unsigned char byte); +void console_tx_flush(void); + +#endif /* _CONSOLE_STREAMS_H_ */

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Patch set updated for coreboot: 559185a console: Split ROMCC helpers
by Kyösti Mälkki 11 Apr '14

11 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5339 -gerrit commit 559185a0bababa9136ad3c0a3c9863b9bda30d61 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 3 10:40:38 2014 +0200 console: Split ROMCC helpers These are potentially useful with GDB or SerialICE too. Also it reduces the amount of actual code we put in romcc_console. Change-Id: Id8c56e979660ad9f4eef39c648f68c7ec60edfba Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 76 +------------------ src/console/console.c | 46 ++++++++++++ src/include/console/console.h | 108 ++------------------------- src/include/console/early_print.h | 149 ++++++++++++++++++++++++++++++++++++++ src/include/console/streams.h | 7 ++ 5 files changed, 209 insertions(+), 177 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 454e0bc..0fa633a 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -17,11 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/streams.h> - -/* While in romstage, console loglevel is built-time constant. */ -#define console_log_level(msg_level) (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= msg_level) +#include <console/early_print.h> +/* Include the sources. */ #if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO #include "drivers/uart/util.c" #include "drivers/uart/uart8250io.c" @@ -31,76 +29,6 @@ #endif #include <console/console.c> -#define __console_tx_byte console_tx_byte -#define __console_tx_flush console_tx_flush - -static void __console_tx_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - __console_tx_byte(digit); -} - -static void __console_tx_char(int loglevel, unsigned char byte) -{ - if (console_log_level(loglevel)) { - __console_tx_byte(byte); - __console_tx_flush(); - } -} - -static void __console_tx_hex8(int loglevel, unsigned char value) -{ - if (console_log_level(loglevel)) { - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - __console_tx_flush(); - } -} - -static void __console_tx_hex16(int loglevel, unsigned short value) -{ - if (console_log_level(loglevel)) { - __console_tx_nibble((value >> 12U) & 0x0fU); - __console_tx_nibble((value >> 8U) & 0x0fU); - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - __console_tx_flush(); - } -} - -static void __console_tx_hex32(int loglevel, unsigned int value) -{ - if (console_log_level(loglevel)) { - __console_tx_nibble((value >> 28U) & 0x0fU); - __console_tx_nibble((value >> 24U) & 0x0fU); - __console_tx_nibble((value >> 20U) & 0x0fU); - __console_tx_nibble((value >> 16U) & 0x0fU); - __console_tx_nibble((value >> 12U) & 0x0fU); - __console_tx_nibble((value >> 8U) & 0x0fU); - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - __console_tx_flush(); - } -} - -static void __console_tx_string(int loglevel, const char *str) -{ - if (console_log_level(loglevel)) { - unsigned char ch; - while((ch = *str++) != '\0') { - if (ch == '\n') - __console_tx_byte('\r'); - __console_tx_byte(ch); - } - __console_tx_flush(); - } -} - -/* if included by romcc, include the sources, too. romcc can't use prototypes */ #include <console/init.c> #include <console/post.c> #include <console/die.c> diff --git a/src/console/console.c b/src/console/console.c index e0e505c..f66cd3f 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -81,3 +81,49 @@ void console_tx_flush(void) usb_tx_flush(0); #endif } + +void console_tx_nibble(unsigned nibble) +{ + unsigned char digit; + digit = nibble + '0'; + if (digit > '9') { + digit += 39; + } + console_tx_byte(digit); +} + +void console_tx_hex8(unsigned char value) +{ + console_tx_nibble((value >> 4U) & 0x0fU); + console_tx_nibble(value & 0x0fU); +} + +void console_tx_hex16(unsigned short value) +{ + console_tx_nibble((value >> 12U) & 0x0fU); + console_tx_nibble((value >> 8U) & 0x0fU); + console_tx_nibble((value >> 4U) & 0x0fU); + console_tx_nibble(value & 0x0fU); +} + +void console_tx_hex32(unsigned int value) +{ + console_tx_nibble((value >> 28U) & 0x0fU); + console_tx_nibble((value >> 24U) & 0x0fU); + console_tx_nibble((value >> 20U) & 0x0fU); + console_tx_nibble((value >> 16U) & 0x0fU); + console_tx_nibble((value >> 12U) & 0x0fU); + console_tx_nibble((value >> 8U) & 0x0fU); + console_tx_nibble((value >> 4U) & 0x0fU); + console_tx_nibble(value & 0x0fU); +} + +void console_tx_string(const char *str) +{ + unsigned char ch; + while((ch = *str++) != '\0') { + if (ch == '\n') + console_tx_byte('\r'); + console_tx_byte(ch); + } +} diff --git a/src/include/console/console.h b/src/include/console/console.h index 54e4545..a15f608 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -21,7 +21,6 @@ #define CONSOLE_CONSOLE_H_ #include <stdint.h> -#include <console/loglevel.h> #include <console/post_codes.h> #ifndef __ROMCC__ @@ -73,109 +72,12 @@ static inline void do_vtxprintf(const char *fmt, va_list args) {}; #endif #endif -#define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR)) -#define print_alert(STR) printk(BIOS_ALERT, "%s", (STR)) -#define print_crit(STR) printk(BIOS_CRIT, "%s", (STR)) -#define print_err(STR) printk(BIOS_ERR, "%s", (STR)) -#define print_warning(STR) printk(BIOS_WARNING,"%s", (STR)) -#define print_notice(STR) printk(BIOS_NOTICE, "%s", (STR)) -#define print_info(STR) printk(BIOS_INFO, "%s", (STR)) -#define print_debug(STR) printk(BIOS_DEBUG, "%s", (STR)) -#define print_spew(STR) printk(BIOS_SPEW, "%s", (STR)) - -#define print_emerg_char(CH) printk(BIOS_EMERG, "%c", (CH)) -#define print_alert_char(CH) printk(BIOS_ALERT, "%c", (CH)) -#define print_crit_char(CH) printk(BIOS_CRIT, "%c", (CH)) -#define print_err_char(CH) printk(BIOS_ERR, "%c", (CH)) -#define print_warning_char(CH) printk(BIOS_WARNING,"%c", (CH)) -#define print_notice_char(CH) printk(BIOS_NOTICE, "%c", (CH)) -#define print_info_char(CH) printk(BIOS_INFO, "%c", (CH)) -#define print_debug_char(CH) printk(BIOS_DEBUG, "%c", (CH)) -#define print_spew_char(CH) printk(BIOS_SPEW, "%c", (CH)) - -#define print_emerg_hex8(HEX) printk(BIOS_EMERG, "%02x", (HEX)) -#define print_alert_hex8(HEX) printk(BIOS_ALERT, "%02x", (HEX)) -#define print_crit_hex8(HEX) printk(BIOS_CRIT, "%02x", (HEX)) -#define print_err_hex8(HEX) printk(BIOS_ERR, "%02x", (HEX)) -#define print_warning_hex8(HEX) printk(BIOS_WARNING,"%02x", (HEX)) -#define print_notice_hex8(HEX) printk(BIOS_NOTICE, "%02x", (HEX)) -#define print_info_hex8(HEX) printk(BIOS_INFO, "%02x", (HEX)) -#define print_debug_hex8(HEX) printk(BIOS_DEBUG, "%02x", (HEX)) -#define print_spew_hex8(HEX) printk(BIOS_SPEW, "%02x", (HEX)) - -#define print_emerg_hex16(HEX) printk(BIOS_EMERG, "%04x", (HEX)) -#define print_alert_hex16(HEX) printk(BIOS_ALERT, "%04x", (HEX)) -#define print_crit_hex16(HEX) printk(BIOS_CRIT, "%04x", (HEX)) -#define print_err_hex16(HEX) printk(BIOS_ERR, "%04x", (HEX)) -#define print_warning_hex16(HEX) printk(BIOS_WARNING,"%04x", (HEX)) -#define print_notice_hex16(HEX) printk(BIOS_NOTICE, "%04x", (HEX)) -#define print_info_hex16(HEX) printk(BIOS_INFO, "%04x", (HEX)) -#define print_debug_hex16(HEX) printk(BIOS_DEBUG, "%04x", (HEX)) -#define print_spew_hex16(HEX) printk(BIOS_SPEW, "%04x", (HEX)) - -#define print_emerg_hex32(HEX) printk(BIOS_EMERG, "%08x", (HEX)) -#define print_alert_hex32(HEX) printk(BIOS_ALERT, "%08x", (HEX)) -#define print_crit_hex32(HEX) printk(BIOS_CRIT, "%08x", (HEX)) -#define print_err_hex32(HEX) printk(BIOS_ERR, "%08x", (HEX)) -#define print_warning_hex32(HEX) printk(BIOS_WARNING,"%08x", (HEX)) -#define print_notice_hex32(HEX) printk(BIOS_NOTICE, "%08x", (HEX)) -#define print_info_hex32(HEX) printk(BIOS_INFO, "%08x", (HEX)) -#define print_debug_hex32(HEX) printk(BIOS_DEBUG, "%08x", (HEX)) -#define print_spew_hex32(HEX) printk(BIOS_SPEW, "%08x", (HEX)) - -#else - -/* __ROMCC__ */ - -#define print_emerg(STR) __console_tx_string(BIOS_EMERG, STR) -#define print_alert(STR) __console_tx_string(BIOS_ALERT, STR) -#define print_crit(STR) __console_tx_string(BIOS_CRIT, STR) -#define print_err(STR) __console_tx_string(BIOS_ERR, STR) -#define print_warning(STR) __console_tx_string(BIOS_WARNING, STR) -#define print_notice(STR) __console_tx_string(BIOS_NOTICE, STR) -#define print_info(STR) __console_tx_string(BIOS_INFO, STR) -#define print_debug(STR) __console_tx_string(BIOS_DEBUG, STR) -#define print_spew(STR) __console_tx_string(BIOS_SPEW, STR) - -#define print_emerg_char(CH) __console_tx_char(BIOS_EMERG, CH) -#define print_alert_char(CH) __console_tx_char(BIOS_ALERT, CH) -#define print_crit_char(CH) __console_tx_char(BIOS_CRIT, CH) -#define print_err_char(CH) __console_tx_char(BIOS_ERR, CH) -#define print_warning_char(CH) __console_tx_char(BIOS_WARNING, CH) -#define print_notice_char(CH) __console_tx_char(BIOS_NOTICE, CH) -#define print_info_char(CH) __console_tx_char(BIOS_INFO, CH) -#define print_debug_char(CH) __console_tx_char(BIOS_DEBUG, CH) -#define print_spew_char(CH) __console_tx_char(BIOS_SPEW, CH) - -#define print_emerg_hex8(HEX) __console_tx_hex8(BIOS_EMERG, HEX) -#define print_alert_hex8(HEX) __console_tx_hex8(BIOS_ALERT, HEX) -#define print_crit_hex8(HEX) __console_tx_hex8(BIOS_CRIT, HEX) -#define print_err_hex8(HEX) __console_tx_hex8(BIOS_ERR, HEX) -#define print_warning_hex8(HEX) __console_tx_hex8(BIOS_WARNING, HEX) -#define print_notice_hex8(HEX) __console_tx_hex8(BIOS_NOTICE, HEX) -#define print_info_hex8(HEX) __console_tx_hex8(BIOS_INFO, HEX) -#define print_debug_hex8(HEX) __console_tx_hex8(BIOS_DEBUG, HEX) -#define print_spew_hex8(HEX) __console_tx_hex8(BIOS_SPEW, HEX) - -#define print_emerg_hex16(HEX) __console_tx_hex16(BIOS_EMERG, HEX) -#define print_alert_hex16(HEX) __console_tx_hex16(BIOS_ALERT, HEX) -#define print_crit_hex16(HEX) __console_tx_hex16(BIOS_CRIT, HEX) -#define print_err_hex16(HEX) __console_tx_hex16(BIOS_ERR, HEX) -#define print_warning_hex16(HEX) __console_tx_hex16(BIOS_WARNING, HEX) -#define print_notice_hex16(HEX) __console_tx_hex16(BIOS_NOTICE, HEX) -#define print_info_hex16(HEX) __console_tx_hex16(BIOS_INFO, HEX) -#define print_debug_hex16(HEX) __console_tx_hex16(BIOS_DEBUG, HEX) -#define print_spew_hex16(HEX) __console_tx_hex16(BIOS_SPEW, HEX) +/* A lot of code still uses print_debug() et al. while use of printk() + * would be preferred. + */ +#include <console/early_print.h> -#define print_emerg_hex32(HEX) __console_tx_hex32(BIOS_EMERG, HEX) -#define print_alert_hex32(HEX) __console_tx_hex32(BIOS_ALERT, HEX) -#define print_crit_hex32(HEX) __console_tx_hex32(BIOS_CRIT, HEX) -#define print_err_hex32(HEX) __console_tx_hex32(BIOS_ERR, HEX) -#define print_warning_hex32(HEX) __console_tx_hex32(BIOS_WARNING, HEX) -#define print_notice_hex32(HEX) __console_tx_hex32(BIOS_NOTICE, HEX) -#define print_info_hex32(HEX) __console_tx_hex32(BIOS_INFO, HEX) -#define print_debug_hex32(HEX) __console_tx_hex32(BIOS_DEBUG, HEX) -#define print_spew_hex32(HEX) __console_tx_hex32(BIOS_SPEW, HEX) +#else /* __ROMCC__ */ #include "arch/x86/lib/romcc_console.c" diff --git a/src/include/console/early_print.h b/src/include/console/early_print.h new file mode 100644 index 0000000..8bc1489 --- /dev/null +++ b/src/include/console/early_print.h @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __CONSOLE_EARLY_PRINT_H_ +#define __CONSOLE_EARLY_PRINT_H_ + +#include <console/console.h> +#include <console/streams.h> +#include <console/loglevel.h> + +#if defined(__ROMCC__) +/* While in romstage, console loglevel is built-time constant. + * With ROMCC we inline this test with help from preprocessor. + */ +#define console_log_level(msg_level) (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= msg_level) + +#define CALL_CONSOLE_TX(loglevel, tx_func, x) \ + do { \ + if (console_log_level(loglevel)) { \ + tx_func(x); \ + console_tx_flush(); \ + } \ + } while (0) + +#define __console_tx_char(level, x) CALL_CONSOLE_TX(level, console_tx_byte, x) +#define __console_tx_hex8(level, x) CALL_CONSOLE_TX(level, console_tx_hex8, x) +#define __console_tx_hex16(level, x) CALL_CONSOLE_TX(level, console_tx_hex16, x) +#define __console_tx_hex32(level, x) CALL_CONSOLE_TX(level, console_tx_hex32, x) +#define __console_tx_string(level, x) CALL_CONSOLE_TX(level, console_tx_string, x) + +#define print_emerg(STR) __console_tx_string(BIOS_EMERG, STR) +#define print_alert(STR) __console_tx_string(BIOS_ALERT, STR) +#define print_crit(STR) __console_tx_string(BIOS_CRIT, STR) +#define print_err(STR) __console_tx_string(BIOS_ERR, STR) +#define print_warning(STR) __console_tx_string(BIOS_WARNING, STR) +#define print_notice(STR) __console_tx_string(BIOS_NOTICE, STR) +#define print_info(STR) __console_tx_string(BIOS_INFO, STR) +#define print_debug(STR) __console_tx_string(BIOS_DEBUG, STR) +#define print_spew(STR) __console_tx_string(BIOS_SPEW, STR) + +#define print_emerg_char(CH) __console_tx_char(BIOS_EMERG, CH) +#define print_alert_char(CH) __console_tx_char(BIOS_ALERT, CH) +#define print_crit_char(CH) __console_tx_char(BIOS_CRIT, CH) +#define print_err_char(CH) __console_tx_char(BIOS_ERR, CH) +#define print_warning_char(CH) __console_tx_char(BIOS_WARNING, CH) +#define print_notice_char(CH) __console_tx_char(BIOS_NOTICE, CH) +#define print_info_char(CH) __console_tx_char(BIOS_INFO, CH) +#define print_debug_char(CH) __console_tx_char(BIOS_DEBUG, CH) +#define print_spew_char(CH) __console_tx_char(BIOS_SPEW, CH) + +#define print_emerg_hex8(HEX) __console_tx_hex8(BIOS_EMERG, HEX) +#define print_alert_hex8(HEX) __console_tx_hex8(BIOS_ALERT, HEX) +#define print_crit_hex8(HEX) __console_tx_hex8(BIOS_CRIT, HEX) +#define print_err_hex8(HEX) __console_tx_hex8(BIOS_ERR, HEX) +#define print_warning_hex8(HEX) __console_tx_hex8(BIOS_WARNING, HEX) +#define print_notice_hex8(HEX) __console_tx_hex8(BIOS_NOTICE, HEX) +#define print_info_hex8(HEX) __console_tx_hex8(BIOS_INFO, HEX) +#define print_debug_hex8(HEX) __console_tx_hex8(BIOS_DEBUG, HEX) +#define print_spew_hex8(HEX) __console_tx_hex8(BIOS_SPEW, HEX) + +#define print_emerg_hex16(HEX) __console_tx_hex16(BIOS_EMERG, HEX) +#define print_alert_hex16(HEX) __console_tx_hex16(BIOS_ALERT, HEX) +#define print_crit_hex16(HEX) __console_tx_hex16(BIOS_CRIT, HEX) +#define print_err_hex16(HEX) __console_tx_hex16(BIOS_ERR, HEX) +#define print_warning_hex16(HEX) __console_tx_hex16(BIOS_WARNING, HEX) +#define print_notice_hex16(HEX) __console_tx_hex16(BIOS_NOTICE, HEX) +#define print_info_hex16(HEX) __console_tx_hex16(BIOS_INFO, HEX) +#define print_debug_hex16(HEX) __console_tx_hex16(BIOS_DEBUG, HEX) +#define print_spew_hex16(HEX) __console_tx_hex16(BIOS_SPEW, HEX) + +#define print_emerg_hex32(HEX) __console_tx_hex32(BIOS_EMERG, HEX) +#define print_alert_hex32(HEX) __console_tx_hex32(BIOS_ALERT, HEX) +#define print_crit_hex32(HEX) __console_tx_hex32(BIOS_CRIT, HEX) +#define print_err_hex32(HEX) __console_tx_hex32(BIOS_ERR, HEX) +#define print_warning_hex32(HEX) __console_tx_hex32(BIOS_WARNING, HEX) +#define print_notice_hex32(HEX) __console_tx_hex32(BIOS_NOTICE, HEX) +#define print_info_hex32(HEX) __console_tx_hex32(BIOS_INFO, HEX) +#define print_debug_hex32(HEX) __console_tx_hex32(BIOS_DEBUG, HEX) +#define print_spew_hex32(HEX) __console_tx_hex32(BIOS_SPEW, HEX) + +#else + +#define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR)) +#define print_alert(STR) printk(BIOS_ALERT, "%s", (STR)) +#define print_crit(STR) printk(BIOS_CRIT, "%s", (STR)) +#define print_err(STR) printk(BIOS_ERR, "%s", (STR)) +#define print_warning(STR) printk(BIOS_WARNING,"%s", (STR)) +#define print_notice(STR) printk(BIOS_NOTICE, "%s", (STR)) +#define print_info(STR) printk(BIOS_INFO, "%s", (STR)) +#define print_debug(STR) printk(BIOS_DEBUG, "%s", (STR)) +#define print_spew(STR) printk(BIOS_SPEW, "%s", (STR)) + +#define print_emerg_char(CH) printk(BIOS_EMERG, "%c", (CH)) +#define print_alert_char(CH) printk(BIOS_ALERT, "%c", (CH)) +#define print_crit_char(CH) printk(BIOS_CRIT, "%c", (CH)) +#define print_err_char(CH) printk(BIOS_ERR, "%c", (CH)) +#define print_warning_char(CH) printk(BIOS_WARNING,"%c", (CH)) +#define print_notice_char(CH) printk(BIOS_NOTICE, "%c", (CH)) +#define print_info_char(CH) printk(BIOS_INFO, "%c", (CH)) +#define print_debug_char(CH) printk(BIOS_DEBUG, "%c", (CH)) +#define print_spew_char(CH) printk(BIOS_SPEW, "%c", (CH)) + +#define print_emerg_hex8(HEX) printk(BIOS_EMERG, "%02x", (HEX)) +#define print_alert_hex8(HEX) printk(BIOS_ALERT, "%02x", (HEX)) +#define print_crit_hex8(HEX) printk(BIOS_CRIT, "%02x", (HEX)) +#define print_err_hex8(HEX) printk(BIOS_ERR, "%02x", (HEX)) +#define print_warning_hex8(HEX) printk(BIOS_WARNING,"%02x", (HEX)) +#define print_notice_hex8(HEX) printk(BIOS_NOTICE, "%02x", (HEX)) +#define print_info_hex8(HEX) printk(BIOS_INFO, "%02x", (HEX)) +#define print_debug_hex8(HEX) printk(BIOS_DEBUG, "%02x", (HEX)) +#define print_spew_hex8(HEX) printk(BIOS_SPEW, "%02x", (HEX)) + +#define print_emerg_hex16(HEX) printk(BIOS_EMERG, "%04x", (HEX)) +#define print_alert_hex16(HEX) printk(BIOS_ALERT, "%04x", (HEX)) +#define print_crit_hex16(HEX) printk(BIOS_CRIT, "%04x", (HEX)) +#define print_err_hex16(HEX) printk(BIOS_ERR, "%04x", (HEX)) +#define print_warning_hex16(HEX) printk(BIOS_WARNING,"%04x", (HEX)) +#define print_notice_hex16(HEX) printk(BIOS_NOTICE, "%04x", (HEX)) +#define print_info_hex16(HEX) printk(BIOS_INFO, "%04x", (HEX)) +#define print_debug_hex16(HEX) printk(BIOS_DEBUG, "%04x", (HEX)) +#define print_spew_hex16(HEX) printk(BIOS_SPEW, "%04x", (HEX)) + +#define print_emerg_hex32(HEX) printk(BIOS_EMERG, "%08x", (HEX)) +#define print_alert_hex32(HEX) printk(BIOS_ALERT, "%08x", (HEX)) +#define print_crit_hex32(HEX) printk(BIOS_CRIT, "%08x", (HEX)) +#define print_err_hex32(HEX) printk(BIOS_ERR, "%08x", (HEX)) +#define print_warning_hex32(HEX) printk(BIOS_WARNING,"%08x", (HEX)) +#define print_notice_hex32(HEX) printk(BIOS_NOTICE, "%08x", (HEX)) +#define print_info_hex32(HEX) printk(BIOS_INFO, "%08x", (HEX)) +#define print_debug_hex32(HEX) printk(BIOS_DEBUG, "%08x", (HEX)) +#define print_spew_hex32(HEX) printk(BIOS_SPEW, "%08x", (HEX)) + +#endif + +#endif /* __CONSOLE_EARLY_PRINT_H_ */ diff --git a/src/include/console/streams.h b/src/include/console/streams.h index 288fade..9d4d3fc 100644 --- a/src/include/console/streams.h +++ b/src/include/console/streams.h @@ -22,4 +22,11 @@ void console_hw_init(void); void console_tx_byte(unsigned char byte); void console_tx_flush(void); +/* Helpers for ROMCC console. */ +void console_tx_nibble(unsigned nibble); +void console_tx_hex8(unsigned char value); +void console_tx_hex16(unsigned short value); +void console_tx_hex32(unsigned int value); +void console_tx_string(const char *str); + #endif /* _CONSOLE_STREAMS_H_ */

1 0

Patch set updated for coreboot: f98bda4 console: Drop driver list in ramstage
by Kyösti Mälkki 11 Apr '14

11 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5337 -gerrit commit f98bda4c8cfa0ea256bc3ad0bff1db2a1ee20588 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 3 17:04:22 2014 +0200 console: Drop driver list in ramstage This framework was only available in ramstage. So we had to define console output functions separately for bootblock, romstage and SMM. Follow-up patches will re-enable all the consoles removed here, in a more flexible fashion, and with less lines-of-code and copy-paste. Also the driver list is not in a well-defined order and some of the loops could exit without visiting all drivers. NOTE: This build has no console in ramstage. Change-Id: Iaddc495aaca37e2a6c2c3f802a0dba27bf227a3e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/coreboot_ram.ld | 4 --- src/arch/x86/coreboot_ram.ld | 4 --- src/console/Makefile.inc | 8 ----- src/console/cbmem_console.c | 36 -------------------- src/console/console.c | 65 +++++-------------------------------- src/console/ne2k_console.c | 37 --------------------- src/console/qemu_debugcon_console.c | 37 --------------------- src/console/spkmodem_console.c | 46 -------------------------- src/console/uart_console.c | 59 --------------------------------- src/console/usbdebug_console.c | 56 -------------------------------- src/drivers/uart/uart8250io.c | 5 --- src/drivers/uart/uart8250mem.c | 8 ----- src/include/console/console.h | 18 ---------- src/include/console/uart.h | 1 - src/lib/rmodule.ld | 4 --- 15 files changed, 9 insertions(+), 379 deletions(-) diff --git a/src/arch/armv7/coreboot_ram.ld b/src/arch/armv7/coreboot_ram.ld index 38eaca3..452d2d7 100644 --- a/src/arch/armv7/coreboot_ram.ld +++ b/src/arch/armv7/coreboot_ram.ld @@ -56,10 +56,6 @@ SECTIONS .rodata : { _rodata = .; . = ALIGN(4); - console_drivers = .; - *(.rodata.console_drivers) - econsole_drivers = . ; - . = ALIGN(4); pci_drivers = . ; *(.rodata.pci_driver) epci_drivers = . ; diff --git a/src/arch/x86/coreboot_ram.ld b/src/arch/x86/coreboot_ram.ld index ea32837..1d1143c 100644 --- a/src/arch/x86/coreboot_ram.ld +++ b/src/arch/x86/coreboot_ram.ld @@ -54,10 +54,6 @@ SECTIONS /* If any changes are made to the driver start/symbols or the * section names the equivalent changes need to made to * rmodule.ld. */ - console_drivers = .; - *(.rodata.console_drivers) - econsole_drivers = . ; - . = ALIGN(4); pci_drivers = . ; *(.rodata.pci_driver) epci_drivers = . ; diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index ef917da..d59e44e 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -15,14 +15,6 @@ bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c printk.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += init.c console.c bootblock-y += die.c -ramstage-$(CONFIG_CONSOLE_SERIAL) += uart_console.c -ramstage-$(CONFIG_SPKMODEM) += spkmodem_console.c -ramstage-$(CONFIG_CONSOLE_USB) += usbdebug_console.c -ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c -ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c -ramstage-$(CONFIG_CONSOLE_QEMU_DEBUGCON) += qemu_debugcon_console.c - - $(obj)/console/init.ramstage.o : $(obj)/build.h $(obj)/console/init.romstage.o : $(obj)/build.h $(obj)/console/init.bootblock.o : $(obj)/build.h diff --git a/src/console/cbmem_console.c b/src/console/cbmem_console.c deleted file mode 100644 index 870ce2f..0000000 --- a/src/console/cbmem_console.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA - */ - -#include <console/console.h> -#include <console/cbmem_console.h> - -static void cbmemc_init_(void) -{ - cbmemc_init(); -} - -static void cbmemc_tx_byte_(unsigned char data) -{ - cbmemc_tx_byte(data); -} - -static const struct console_driver cbmem_console __console = { - .init = cbmemc_init_, - .tx_byte = cbmemc_tx_byte_, -}; diff --git a/src/console/console.c b/src/console/console.c index d5aadf6..2f4eb5c 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -24,62 +24,6 @@ #include <console/ne2k.h> #include <console/spkmodem.h> -#ifndef __PRE_RAM__ - -/* initialize the console */ -void console_hw_init(void) -{ - struct console_driver *driver; - - for(driver = console_drivers; driver < econsole_drivers; driver++) { - if (!driver->init) - continue; - driver->init(); - } -} - -void console_tx_flush(void) -{ - struct console_driver *driver; - for(driver = console_drivers; driver < econsole_drivers; driver++) { - if (!driver->tx_flush) - continue; - driver->tx_flush(); - } -} - -void console_tx_byte(unsigned char byte) -{ - struct console_driver *driver; - for(driver = console_drivers; driver < econsole_drivers; driver++) { - driver->tx_byte(byte); - } -} - -unsigned char console_rx_byte(void) -{ - struct console_driver *driver; - for(driver = console_drivers; driver < econsole_drivers; driver++) { - if (driver->tst_byte) - break; - } - if (driver == econsole_drivers) - return 0; - while (!driver->tst_byte()); - return driver->rx_byte(); -} - -int console_tst_byte(void) -{ - struct console_driver *driver; - for(driver = console_drivers; driver < econsole_drivers; driver++) - if (driver->tst_byte) - return driver->tst_byte(); - return 0; -} - -#else // __PRE_RAM__ ^^^ NOT defined vvv defined - void console_hw_init(void) { #if CONFIG_CONSOLE_SERIAL @@ -98,4 +42,13 @@ void console_hw_init(void) usbdebug_init(); #endif } + +#ifndef __PRE_RAM__ +void console_tx_byte(unsigned char byte) +{ +} + +void console_tx_flush(void) +{ +} #endif diff --git a/src/console/ne2k_console.c b/src/console/ne2k_console.c deleted file mode 100644 index ffbf0c6..0000000 --- a/src/console/ne2k_console.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2010 Rudolf Marek <r.marek(a)assembler.cz> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/ne2k.h> - -static void ne2k_tx_byte(unsigned char data) -{ - ne2k_append_data(&data, 1, CONFIG_CONSOLE_NE2K_IO_PORT); -} - -static void ne2k_tx_flush(void) -{ - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -} - -static const struct console_driver ne2k_console __console = { - .tx_byte = ne2k_tx_byte, - .tx_flush = ne2k_tx_flush, -}; diff --git a/src/console/qemu_debugcon_console.c b/src/console/qemu_debugcon_console.c deleted file mode 100644 index d7a53a2..0000000 --- a/src/console/qemu_debugcon_console.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Red Hat Inc. - * Written by Gerd Hoffmann <kraxel(a)redhat.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/qemu_debugcon.h> - -static void debugcon_init(void) -{ - qemu_debugcon_init(); -} - -static void debugcon_tx_byte(unsigned char data) -{ - qemu_debugcon_tx_byte(data); -} - -static const struct console_driver debugcon_console __console = { - .init = debugcon_init, - .tx_byte = debugcon_tx_byte, -}; diff --git a/src/console/spkmodem_console.c b/src/console/spkmodem_console.c deleted file mode 100644 index 814a1ac..0000000 --- a/src/console/spkmodem_console.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/spkmodem.h> - -static void spkmodem_tx_flush(void) -{ -} - -static unsigned char spkmodem_rx_byte(void) -{ - return 0; -} - -static int spkmodem_tst_byte(void) -{ - return 0; -} - - -static const struct console_driver spkmodem_console __console = { - .init = spkmodem_init, - .tx_byte = spkmodem_tx_byte, - .tx_flush = spkmodem_tx_flush, - .rx_byte = spkmodem_rx_byte, - .tst_byte = spkmodem_tst_byte, -}; - diff --git a/src/console/uart_console.c b/src/console/uart_console.c deleted file mode 100644 index f5535d7..0000000 --- a/src/console/uart_console.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/uart.h> - -static void uartmem_init(void) -{ - uart_init(); -} - -static void uartmem_tx_byte(unsigned char data) -{ - uart_tx_byte(data); -} - -static void uartmem_tx_flush(void) -{ - uart_tx_flush(); -} - -static unsigned char uartmem_rx_byte(void) -{ - return uart_rx_byte(); -} - -/* This only relevant with x86 with GDB_STUB enabled.*/ -static int uartmem_tst_byte(void) -{ -#if CONFIG_DRIVERS_UART_8250IO || CONFIG_DRIVERS_UART_8250MEM - return uart_can_rx_byte(); -#else - return 0; -#endif -} - -static const struct console_driver uart_console __console = { - .init = uartmem_init, - .tx_byte = uartmem_tx_byte, - .tx_flush = uartmem_tx_flush, - .rx_byte = uartmem_rx_byte, - .tst_byte = uartmem_tst_byte, -}; diff --git a/src/console/usbdebug_console.c b/src/console/usbdebug_console.c deleted file mode 100644 index 8331473..0000000 --- a/src/console/usbdebug_console.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA - */ - -#include <string.h> -#include <console/console.h> -#include <console/usb.h> - -static void dbgp_init(void) -{ - usbdebug_init(); -} - -static void dbgp_tx_byte(unsigned char data) -{ - usb_tx_byte(0, data); -} - -static unsigned char dbgp_rx_byte(void) -{ - return usb_rx_byte(0); -} - -static void dbgp_tx_flush(void) -{ - usb_tx_flush(0); -} - -static int dbgp_tst_byte(void) -{ - return usb_can_rx_byte(0); -} - -static const struct console_driver usbdebug_direct_console __console = { - .init = dbgp_init, - .tx_byte = dbgp_tx_byte, - .tx_flush = dbgp_tx_flush, - .rx_byte = dbgp_rx_byte, - .tst_byte = dbgp_tst_byte, -}; diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 1eebb18..e1fb39b 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -129,11 +129,6 @@ unsigned char uart_rx_byte(void) return uart8250_rx_byte(bases[0]); } -int uart_can_rx_byte(void) -{ - return uart8250_can_rx_byte(bases[0]); -} - void uart_tx_flush(void) { uart8250_tx_flush(bases[0]); diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 74929f5..5a186f0 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -116,14 +116,6 @@ unsigned char uart_rx_byte(void) return uart8250_mem_rx_byte(base); } -int uart_can_rx_byte(void) -{ - u32 base = uart_platform_base(0); - if (!base) - return 0; - return uart8250_mem_can_rx_byte(base); -} - void uart_tx_flush(void) { u32 base = uart_platform_base(0); diff --git a/src/include/console/console.h b/src/include/console/console.h index c184f83..0ebd1b7 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -24,24 +24,6 @@ #include <console/loglevel.h> #include <console/post_codes.h> -#ifndef __PRE_RAM__ -unsigned char console_rx_byte(void); -int console_tst_byte(void); -struct console_driver { - void (*init)(void); - void (*tx_byte)(unsigned char byte); - void (*tx_flush)(void); - unsigned char (*rx_byte)(void); - int (*tst_byte)(void); -}; - -#define __console __attribute__((used, __section__ (".rodata.console_drivers"))) - -/* Defined by the linker... */ -extern struct console_driver console_drivers[]; -extern struct console_driver econsole_drivers[]; -#endif - #ifndef __ROMCC__ int console_log_level(int msg_level); void console_init(void); diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 68abf6f..4551408 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -43,7 +43,6 @@ void uart_init(void); void uart_tx_byte(unsigned char data); void uart_tx_flush(void); unsigned char uart_rx_byte(void); -int uart_can_rx_byte(void); unsigned int uart_platform_base(int idx); diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index 9222f3b..63b99b3 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -35,10 +35,6 @@ SECTIONS /* The driver sections are to allow linking coreboot's * ramstage with the rmodule linker. Any changes made in * coreboot_ram.ld should be made here as well. */ - console_drivers = .; - *(.rodata.console_drivers) - econsole_drivers = . ; - . = ALIGN(4); pci_drivers = . ; *(.rodata.pci_driver) epci_drivers = . ;

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Patch set updated for coreboot: 5881936 build rules: Identify build stage with simple variables
by Kyösti Mälkki 11 Apr '14

11 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5410 -gerrit commit 5881936a6ace2d13e2eaca415bffc32e6f0db54a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 26 15:19:04 2014 +0200 build rules: Identify build stage with simple variables Provide simple environment variables telling which stage of boot is being built. Change-Id: I8cbb5cf91f53e01c06e7d672b5be3f5c235f911d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/include/arch/rules.h | 23 +++++++++++++++++++++++ src/arch/x86/Makefile.inc | 4 ++-- src/arch/x86/include/arch/rules.h | 29 +++++++++++++++++++++++++++++ 3 files changed, 54 insertions(+), 2 deletions(-) diff --git a/src/arch/armv7/include/arch/rules.h b/src/arch/armv7/include/arch/rules.h index a790365..de68f04 100644 --- a/src/arch/armv7/include/arch/rules.h +++ b/src/arch/armv7/include/arch/rules.h @@ -19,6 +19,29 @@ #ifndef _ARCH_RULES_H #define _ARCH_RULES_H +/* Useful helpers to tell whether the code is executing in bootblock, + * romstage, ramstage or SMM. + */ + +#if defined(__BOOT_BLOCK__) +#define ENV_BOOTBLOCK 1 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 0 + +#elif defined(__PRE_RAM__) +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 1 +#define ENV_RAMSTAGE 0 + +#else +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 1 +#endif + +/* SMM not implemented on ARM. */ +#define ENV_SMM 0 + /* For romstage and ramstage always build with simple device model, ie. * PCI, PNP and CPU functions operate without use of devicetree. * diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 56f0c5c..f986c3b 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -368,9 +368,9 @@ endif bootblock_inc += $(objgenerated)/bootblock.inc bootblock_inc += $(src)/arch/x86/lib/walkcbfs.S -bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ +bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOT_BLOCK__ ifeq ($(CONFIG_SSE),y) -bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ +bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOT_BLOCK__ endif $(objgenerated)/bootblock.ld: $$(bootblock_lds) $(obj)/ldoptions diff --git a/src/arch/x86/include/arch/rules.h b/src/arch/x86/include/arch/rules.h index 4b84677..1ed1f1f 100644 --- a/src/arch/x86/include/arch/rules.h +++ b/src/arch/x86/include/arch/rules.h @@ -19,6 +19,35 @@ #ifndef _ARCH_RULES_H #define _ARCH_RULES_H +/* Useful helpers to tell whether the code is executing in bootblock, + * romstage, ramstage or SMM. + */ + +#if defined(__BOOT_BLOCK__) +#define ENV_BOOTBLOCK 1 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 0 +#define ENV_SMM 0 + +#elif defined(__PRE_RAM__) +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 1 +#define ENV_RAMSTAGE 0 +#define ENV_SMM 0 + +#elif defined(__SMM__) +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 0 +#define ENV_SMM 1 +#else + +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 1 +#define ENV_SMM 0 +#endif + /* For romstage and ramstage always build with simple device model, ie. * PCI, PNP and CPU functions operate without use of devicetree. *

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Patch set updated for coreboot: 7ae6735 uart: Support multiple ports
by Kyösti Mälkki 11 Apr '14

11 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5342 -gerrit commit 7ae673555070027a2a45babcdef684d85992aa05 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Mar 14 22:28:29 2014 +0200 uart: Support multiple ports The port for console remains to be a compile time constant. The Kconfig option is changed to select an UART port with index to avoid putting map of UART base addresses in Kconfigs. With this change it is possible to have other than debug console on different UART port. Change-Id: Ie1845a946f8d3b2604ef5404edb31b2e811f3ccd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/Kconfig | 38 +++++------------- src/cpu/allwinner/a10/Kconfig | 49 ++---------------------- src/cpu/allwinner/a10/uart_console.c | 48 +++++++---------------- src/cpu/samsung/exynos5250/Kconfig | 39 ++----------------- src/cpu/samsung/exynos5250/uart.c | 23 ++++++----- src/cpu/samsung/exynos5420/Kconfig | 39 ++----------------- src/cpu/samsung/exynos5420/uart.c | 21 +++++----- src/cpu/ti/am335x/uart.c | 24 +++++++----- src/drivers/uart/oxpcie_early.c | 2 +- src/drivers/uart/pl011.c | 17 +++------ src/drivers/uart/uart8250io.c | 18 ++++----- src/drivers/uart/uart8250mem.c | 16 ++++---- src/include/console/uart.h | 14 +++---- src/mainboard/emulation/qemu-armv7/Kconfig | 5 --- src/mainboard/emulation/qemu-armv7/Makefile.inc | 4 ++ src/mainboard/emulation/qemu-armv7/mmio.c | 21 ++++++++++ src/mainboard/ti/beaglebone/Kconfig | 51 ++----------------------- src/mainboard/ti/beaglebone/bootblock.c | 12 +++--- 18 files changed, 138 insertions(+), 303 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 65fc1aa..703e5c7 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -48,39 +48,21 @@ if CONSOLE_SERIAL comment "device-specific UART" depends on HAVE_UART_SPECIAL -choice - prompt "Serial port for 8250" - default CONSOLE_SERIAL_COM1 - depends on DRIVERS_UART_8250IO - -config CONSOLE_SERIAL_COM1 - bool "COM1/ttyS0, I/O port 0x3f8" - help - Serial console on COM1/ttyS0 at I/O port 0x3f8. -config CONSOLE_SERIAL_COM2 - bool "COM2/ttyS1, I/O port 0x2f8" - help - Serial console on COM2/ttyS1 at I/O port 0x2f8. -config CONSOLE_SERIAL_COM3 - bool "COM3/ttyS2, I/O port 0x3e8" - help - Serial console on COM3/ttyS2 at I/O port 0x3e8. -config CONSOLE_SERIAL_COM4 - bool "COM4/ttyS3, I/O port 0x2e8" - help - Serial console on COM4/ttyS3 at I/O port 0x2e8. - -endchoice +config UART_FOR_CONSOLE + prompt "Index for UART port to use for console" + default 0 +# FIXME: Early programming in romstage is incorrect as we should +# program different LDN to actually change the physical port. config TTYS0_BASE hex depends on DRIVERS_UART_8250IO - default 0x3f8 if CONSOLE_SERIAL_COM1 - default 0x2f8 if CONSOLE_SERIAL_COM2 - default 0x3e8 if CONSOLE_SERIAL_COM3 - default 0x2e8 if CONSOLE_SERIAL_COM4 + default 0x3f8 if UART_FOR_CONSOLE = 0 + default 0x2f8 if UART_FOR_CONSOLE = 1 + default 0x3e8 if UART_FOR_CONSOLE = 2 + default 0x2e8 if UART_FOR_CONSOLE = 3 help - Map the COM port names to the respective I/O port. + Map the COM port number to the respective I/O port. choice prompt "Baud rate" diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 8512c38..3d12acd 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -73,51 +73,8 @@ config SYS_SDRAM_BASE hex default 0x40000000 -choice CONSOLE_SERIAL_UART_CHOICES - prompt "Serial Console UART" - default CONSOLE_SERIAL_UART0 - depends on CONSOLE_SERIAL - -config CONSOLE_SERIAL_UART0 - bool "UART0" - help - Serial console on UART0 - -config CONSOLE_SERIAL_UART1 - bool "UART1" - help - Serial console on UART1 - -config CONSOLE_SERIAL_UART2 - bool "UART2" - help - Serial console on UART2 - -config CONSOLE_SERIAL_UART3 - bool "UART3" - help - Serial console on UART3 - -config CONSOLE_SERIAL_UART4 - bool "UART4" - help - Serial console on UART4 - -config CONSOLE_SERIAL_UART5 - bool "UART5" - help - Serial console on UART5 - -config CONSOLE_SERIAL_UART6 - bool "UART6" - help - Serial console on UART6 - -config CONSOLE_SERIAL_UART7 - bool "UART7" - help - Serial console on UART7 - -endchoice +config UART_FOR_CONSOLE + int + default 0 endif # if CPU_ALLWINNER_A10 diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c index d6b91e7..bb5f41c 100644 --- a/src/cpu/allwinner/a10/uart_console.c +++ b/src/cpu/allwinner/a10/uart_console.c @@ -14,28 +14,13 @@ #include <cpu/allwinner/a10/uart.h> -static void *get_console_uart_base_addr(void) +unsigned int uart_platform_base(int idx) { - /* This big block gets compiled to a constant, not a function call */ - if (CONFIG_CONSOLE_SERIAL_UART0) - return (void *)A1X_UART0_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART1) - return (void *)A1X_UART1_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART2) - return (void *)A1X_UART2_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART3) - return (void *)A1X_UART3_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART4) - return (void *)A1X_UART4_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART5) - return (void *)A1X_UART5_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART6) - return (void *)A1X_UART6_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART7) - return (void *)A1X_UART7_BASE; - - /* If selection is invalid, default to UART0 */ - return (void *)A1X_UART0_BASE; + /* UART blocks are mapped 0x400 bytes apart */ + if (idx < 8) + return A1X_UART0_BASE + 0x400 * idx; + else + return 0; } /* FIXME: We assume clock is 24MHz, which may not be the case. */ @@ -44,14 +29,9 @@ unsigned int uart_platform_refclk(void) return 24000000; } -unsigned int uart_platform_base(int idx) -{ - return (unsigned int)get_console_uart_base_addr(); -} - -void uart_init(void) +void uart_init(int idx) { - void *uart_base = get_console_uart_base_addr(); + void *uart_base = uart_platform_baseptr(idx); /* Use default 8N1 encoding */ a10_uart_configure(uart_base, default_baudrate(), @@ -59,17 +39,17 @@ void uart_init(void) a10_uart_enable_fifos(uart_base); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - return a10_uart_rx_blocking(get_console_uart_base_addr()); + return a10_uart_rx_blocking(uart_platform_baseptr(idx)); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - a10_uart_tx_blocking(get_console_uart_base_addr(), data); + a10_uart_tx_blocking(uart_platform_baseptr(idx), data); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { } @@ -78,7 +58,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 9320184..2fda9b3 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -88,41 +88,8 @@ config SYS_SDRAM_BASE hex default 0x40000000 -choice CONSOLE_SERIAL_UART_CHOICES - prompt "Serial Console UART" - default CONSOLE_SERIAL_UART3 - depends on CONSOLE_SERIAL - -config CONSOLE_SERIAL_UART0 - bool "UART0" - help - Serial console on UART0 - -config CONSOLE_SERIAL_UART1 - bool "UART1" - help - Serial console on UART1 - -config CONSOLE_SERIAL_UART2 - bool "UART2" - help - Serial console on UART2 - -config CONSOLE_SERIAL_UART3 - bool "UART3" - help - Serial console on UART3 - -endchoice - -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on CONSOLE_SERIAL - default 0x12c00000 if CONSOLE_SERIAL_UART0 - default 0x12c10000 if CONSOLE_SERIAL_UART1 - default 0x12c20000 if CONSOLE_SERIAL_UART2 - default 0x12c30000 if CONSOLE_SERIAL_UART3 - help - Map the UART names to the respective MMIO address. +config UART_FOR_CONSOLE + int + default 3 endif diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 1dabc09..a73a01a 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -157,30 +157,33 @@ static void exynos5_uart_tx_flush(struct s5p_uart *uart) unsigned int uart_platform_base(int idx) { - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + if (idx < 4) + return 0x12c00000 + idx * 0x10000; + else + return 0; } -void uart_init(void) +void uart_init(int idx) { - struct s5p_uart *uart = uart_platform_baseptr(0); + struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_init_dev(uart); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - struct s5p_uart *uart = uart_platform_baseptr(0); + struct s5p_uart *uart = uart_platform_baseptr(idx); return exynos5_uart_rx_byte(uart); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - struct s5p_uart *uart = uart_platform_baseptr(0); + struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_uart_tx_byte(uart, data); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { - struct s5p_uart *uart = uart_platform_baseptr(0); + struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_uart_tx_flush(uart); } @@ -189,7 +192,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index 5f78cc5..e46d889 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -90,41 +90,8 @@ config SYS_SDRAM_BASE hex default 0x20000000 -choice CONSOLE_SERIAL_UART_CHOICES - prompt "Serial Console UART" - default CONSOLE_SERIAL_UART3 - depends on CONSOLE_SERIAL - -config CONSOLE_SERIAL_UART0 - bool "UART0" - help - Serial console on UART0 - -config CONSOLE_SERIAL_UART1 - bool "UART1" - help - Serial console on UART1 - -config CONSOLE_SERIAL_UART2 - bool "UART2" - help - Serial console on UART2 - -config CONSOLE_SERIAL_UART3 - bool "UART3" - help - Serial console on UART3 - -endchoice - -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on CONSOLE_SERIAL - default 0x12c00000 if CONSOLE_SERIAL_UART0 - default 0x12c10000 if CONSOLE_SERIAL_UART1 - default 0x12c20000 if CONSOLE_SERIAL_UART2 - default 0x12c30000 if CONSOLE_SERIAL_UART3 - help - Map the UART names to the respective MMIO address. +config UART_FOR_CONSOLE + int + default 3 endif diff --git a/src/cpu/samsung/exynos5420/uart.c b/src/cpu/samsung/exynos5420/uart.c index 290eb35..8fd4dea 100644 --- a/src/cpu/samsung/exynos5420/uart.c +++ b/src/cpu/samsung/exynos5420/uart.c @@ -149,28 +149,31 @@ static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data) unsigned int uart_platform_base(int idx) { - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + if (idx < 4) + return 0x12c00000 + idx * 0x10000; + else + return 0; } -void uart_init(void) +void uart_init(int idx) { - struct s5p_uart *uart = uart_platform_baseptr(0); + struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_init_dev(uart); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - struct s5p_uart *uart = uart_platform_baseptr(0); + struct s5p_uart *uart = uart_platform_baseptr(idx); return exynos5_uart_rx_byte(uart); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - struct s5p_uart *uart = uart_platform_baseptr(0); + struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_uart_tx_byte(uart, data); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { /* Exynos5250 implements this too. */ } @@ -180,7 +183,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index 858926b..371e352 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -154,30 +154,36 @@ unsigned int uart_platform_refclk(void) unsigned int uart_platform_base(int idx) { - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + const unsigned int bases[] = { + 0x44e09000, 0x48022000, 0x48024000, + 0x481a6000, 0x481a8000, 0x481aa000 + }; + if (idx < sizeof(bases)/sizeof(bases[0])) + return bases[idx]; + return 0; } -void uart_init(void) +void uart_init(int idx) { - struct am335x_uart *uart = uart_platform_baseptr(0); + struct am335x_uart *uart = uart_platform_baseptr(idx); uint16_t div = (uint16_t) uart_baudrate_divisor( default_baudrate(), uart_platform_refclk(), 16); am335x_uart_init(uart, div); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - struct am335x_uart *uart = uart_platform_baseptr(0); + struct am335x_uart *uart = uart_platform_baseptr(idx); return am335x_uart_rx_byte(uart); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - struct am335x_uart *uart = uart_platform_baseptr(0); + struct am335x_uart *uart = uart_platform_baseptr(idx); am335x_uart_tx_byte(uart, data); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { } @@ -186,7 +192,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c index b81fa89..fd37806 100644 --- a/src/drivers/uart/oxpcie_early.c +++ b/src/drivers/uart/oxpcie_early.c @@ -97,7 +97,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 41e66fa..e2db877 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -21,26 +21,21 @@ static void pl011_uart_tx_byte(unsigned int *uart_base, unsigned char data) *uart_base = (unsigned int)data; } -unsigned int uart_platform_base(int idx) +void uart_init(int idx) { - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -void uart_init(void) +void uart_tx_byte(int idx, unsigned char data) { -} - -void uart_tx_byte(unsigned char data) -{ - unsigned int *uart_base = uart_platform_baseptr(0); + unsigned int *uart_base = uart_platform_baseptr(idx); pl011_uart_tx_byte(uart_base, data); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { return 0; } @@ -50,7 +45,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index e1fb39b..f008e1f 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -111,27 +111,27 @@ unsigned int uart_platform_base(int idx) return bases[idx]; } -void uart_init(void) +void uart_init(int idx) { unsigned int div; div = uart_baudrate_divisor(default_baudrate(), BAUDRATE_REFCLK, BAUDRATE_OVERSAMPLE); - uart8250_init(bases[0], div); + uart8250_init(uart_platform_base(idx), div); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - uart8250_tx_byte(bases[0], data); + uart8250_tx_byte(uart_platform_base(idx), data); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - return uart8250_rx_byte(bases[0]); + return uart8250_rx_byte(uart_platform_base(idx)); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { - uart8250_tx_flush(bases[0]); + uart8250_tx_flush(uart_platform_base(idx)); } #ifndef __PRE_RAM__ @@ -139,7 +139,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_IO_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 5a186f0..976bcb6 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -89,9 +89,9 @@ static void uart8250_mem_init(unsigned base_port, unsigned divisor) write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); } -void uart_init(void) +void uart_init(int idx) { - u32 base = uart_platform_base(0); + u32 base = uart_platform_base(idx); if (!base) return; @@ -100,25 +100,25 @@ void uart_init(void) uart8250_mem_init(base, div); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - u32 base = uart_platform_base(0); + u32 base = uart_platform_base(idx); if (!base) return; uart8250_mem_tx_byte(base, data); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - u32 base = uart_platform_base(0); + u32 base = uart_platform_base(idx); if (!base) return 0xff; return uart8250_mem_rx_byte(base); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { - u32 base = uart_platform_base(0); + u32 base = uart_platform_base(idx); if (!base) return; uart8250_mem_tx_flush(base); diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 2ea1931..21aacd0 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -40,10 +40,10 @@ unsigned int uart_baudrate_divisor(unsigned int baudrate, unsigned int refclk, unsigned int oversample); -void uart_init(void); -void uart_tx_byte(unsigned char data); -void uart_tx_flush(void); -unsigned char uart_rx_byte(void); +void uart_init(int idx); +void uart_tx_byte(int idx, unsigned char data); +void uart_tx_flush(int idx); +unsigned char uart_rx_byte(int idx); unsigned int uart_platform_base(int idx); @@ -60,9 +60,9 @@ void oxford_remap(unsigned int new_base); (ENV_ROMSTAGE || ENV_RAMSTAGE || (ENV_SMM && CONFIG_DEBUG_SMI)) #if __CONSOLE_SERIAL_ENABLE__ -static inline void __uart_init(void) { uart_init(); } -static inline void __uart_tx_byte(u8 data) { uart_tx_byte(data); } -static inline void __uart_tx_flush(void) { uart_tx_flush(); } +static inline void __uart_init(void) { uart_init(CONFIG_UART_FOR_CONSOLE); } +static inline void __uart_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data); } +static inline void __uart_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_CONSOLE); } #else static inline void __uart_init(void) {} static inline void __uart_tx_byte(u8 data) {} diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 040ed9c..6d04216 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -48,11 +48,6 @@ config DRAM_SIZE_MB int default 1024 -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on CONSOLE_SERIAL - default 0x10009000 - # Memory map for qemu vexpress-a9: # # 0x0000_0000: jump instruction (by qemu) diff --git a/src/mainboard/emulation/qemu-armv7/Makefile.inc b/src/mainboard/emulation/qemu-armv7/Makefile.inc index d15495f..e088da6 100644 --- a/src/mainboard/emulation/qemu-armv7/Makefile.inc +++ b/src/mainboard/emulation/qemu-armv7/Makefile.inc @@ -21,3 +21,7 @@ ramstage-y += media.c bootblock-y += timer.c romstage-y += timer.c ramstage-y += timer.c + +bootblock-y += mmio.c +romstage-y += mmio.c +ramstage-y += mmio.c diff --git a/src/mainboard/emulation/qemu-armv7/mmio.c b/src/mainboard/emulation/qemu-armv7/mmio.c new file mode 100644 index 0000000..02473e4 --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/mmio.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/uart.h> + +#define VEXPRESS_UART0_IO_ADDRESS (0x10009000) + +unsigned int uart_platform_base(int idx) +{ + return VEXPRESS_UART0_IO_ADDRESS; +} diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index c842a5d..a24fcde 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -61,54 +61,9 @@ config CBFS_HEADER_ROM_OFFSET hex default 0x10 -choice CONSOLE_SERIAL_UART_CHOICES - prompt "Serial Console UART" - default CONSOLE_SERIAL_UART0 - depends on CONSOLE_SERIAL - -config CONSOLE_SERIAL_UART0 - bool "UART0" - help - Serial console on UART0 - -config CONSOLE_SERIAL_UART1 - bool "UART1" - help - Serial console on UART1 - -config CONSOLE_SERIAL_UART2 - bool "UART2" - help - Serial console on UART2 - -config CONSOLE_SERIAL_UART3 - bool "UART3" - help - Serial console on UART3 - -config CONSOLE_SERIAL_UART4 - bool "UART4" - help - Serial console on UART4 - -config CONSOLE_SERIAL_UART5 - bool "UART5" - help - Serial console on UART5 - -endchoice - -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on CONSOLE_SERIAL - default 0x44e09000 if CONSOLE_SERIAL_UART0 - default 0x48022000 if CONSOLE_SERIAL_UART1 - default 0x48024000 if CONSOLE_SERIAL_UART2 - default 0x481a6000 if CONSOLE_SERIAL_UART3 - default 0x481a8000 if CONSOLE_SERIAL_UART4 - default 0x481aa000 if CONSOLE_SERIAL_UART5 - help - Map the UART names to the respective MMIO address. +config UART_FOR_CONSOLE + int + default 0 ################################################################# # stuff from smdk5250.h # diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c index 9e0a62e..6cc7a8c 100644 --- a/src/mainboard/ti/beaglebone/bootblock.c +++ b/src/mainboard/ti/beaglebone/bootblock.c @@ -42,22 +42,22 @@ void bootblock_mainboard_init(void) setbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0x5 << 21); /* Set up the UART we're going to use */ - if (CONFIG_CONSOLE_SERIAL_UART0) { + if (CONFIG_UART_FOR_CONSOLE == 0) { am335x_pinmux_uart0(); uart_clock_ctrl = (void *)(uintptr_t)(0x44e00400 + 0xb4); - } else if (CONFIG_CONSOLE_SERIAL_UART1) { + } else if (CONFIG_UART_FOR_CONSOLE == 1) { am335x_pinmux_uart1(); uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x6c); - } else if (CONFIG_CONSOLE_SERIAL_UART2) { + } else if (CONFIG_UART_FOR_CONSOLE == 2) { am335x_pinmux_uart2(); uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x70); - } else if (CONFIG_CONSOLE_SERIAL_UART3) { + } else if (CONFIG_UART_FOR_CONSOLE == 3) { am335x_pinmux_uart3(); uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x74); - } else if (CONFIG_CONSOLE_SERIAL_UART4) { + } else if (CONFIG_UART_FOR_CONSOLE == 4) { am335x_pinmux_uart4(); uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x78); - } else if (CONFIG_CONSOLE_SERIAL_UART5) { + } else if (CONFIG_UART_FOR_CONSOLE == 5) { am335x_pinmux_uart5(); uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x38); }

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coreboot-gerrit April 2014