coreboot-gerrit February 2014

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Patch set updated for coreboot: 9d35fb0 NOTFORMERGE: x60gfx: step 1
by Vladimir Serbinenko 23 Feb '14

23 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5287 -gerrit commit 9d35fb055c6e8391912f64d17e499521869ded2c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 23 14:17:03 2014 +0100 NOTFORMERGE: x60gfx: step 1 Change-Id: I91c5619d7c2a212a55e301733374de8b23f8aa1f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/gma/edid.c | 23 +++++++++++++---------- src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/lenovo/x60/i915.c | 18 +++++------------- src/northbridge/intel/i945/gma.c | 6 +++--- 4 files changed, 22 insertions(+), 26 deletions(-) diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 0066b6a..e9a4dd6 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -26,13 +26,16 @@ #include "i915_reg.h" #include "edid.h" +unsigned long io_i915_READ32(unsigned long addr); +void io_i915_WRITE32(unsigned long val, unsigned long addr); + static void wait_rdy(u32 mmio) { unsigned try = 100; while (try--) { - if (read32(mmio + PCH_GMBUS2) & (1 << 11)) + if (io_i915_READ32(PCH_GMBUS2) & (1 << 11)) return; udelay(10); } @@ -45,29 +48,29 @@ intel_gmbus_read_edid(u32 mmio, u8 bus, u8 slave, u8 *edid) wait_rdy(mmio); /* 100 KHz, hold 0ns, */ - write32(mmio + PCH_GMBUS0, bus); + io_i915_WRITE32(bus, PCH_GMBUS0); wait_rdy(mmio); /* Ensure index bits are disabled. */ - write32(mmio + PCH_GMBUS5, 0); - write32(mmio + PCH_GMBUS1, 0x46000000 | (slave << 1)); + io_i915_WRITE32(0, PCH_GMBUS5); + io_i915_WRITE32((0x46000000 | 0x10000 | (slave << 1)), PCH_GMBUS1); wait_rdy(mmio); /* Ensure index bits are disabled. */ - write32(mmio + PCH_GMBUS5, 0); - write32(mmio + PCH_GMBUS1, 0x4a800001 | (slave << 1)); + io_i915_WRITE32(0, PCH_GMBUS5); + io_i915_WRITE32((0x46800001 | (slave << 1)), PCH_GMBUS1); for (i = 0; i < 128 / 4; i++) { u32 reg32; wait_rdy(mmio); - reg32 = read32(mmio + PCH_GMBUS3); + reg32 = io_i915_READ32(PCH_GMBUS3); edid[4 * i] = reg32 & 0xff; edid[4 * i + 1] = (reg32 >> 8) & 0xff; edid[4 * i + 2] = (reg32 >> 16) & 0xff; edid[4 * i + 3] = (reg32 >> 24) & 0xff; } wait_rdy(mmio); - write32(mmio + PCH_GMBUS1, 0x4a800000 | (slave << 1)); + io_i915_WRITE32((0x4a800000 | (slave << 1)), PCH_GMBUS1); wait_rdy(mmio); - write32(mmio + PCH_GMBUS0, 0x48000000); - write32(mmio + PCH_GMBUS2, 0x00008000); + io_i915_WRITE32(0x48000000, PCH_GMBUS0); + io_i915_WRITE32(0x00008000, PCH_GMBUS2); printk (BIOS_INFO, "EDID:\n"); for (i = 0; i < 128; i++) { diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 7ed2665..977d9e5 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT select H8_DOCK_EARLY_INIT + select INTEL_EDID config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 4870fd8..d420cb8 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -43,6 +43,7 @@ #include <cpu/x86/msr.h> #include <edid.h> #include "i915io.h" +#include <drivers/intel/gma/edid.h> enum { vmsg = 1, vio = 2, vspin = 4, @@ -64,16 +65,6 @@ static unsigned int physbase; static u32 htotal, hblank, hsync, vtotal, vblank, vsync; -const u8 x60_edid_data[] = { - 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0xae, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x0f, 0x01, 0x03, 0x80, 0x19, 0x12, 0x78, 0xea, 0xed, 0x75, 0x91, 0x57, 0x4f, 0x8b, 0x26, - 0x21, 0x50, 0x54, 0x21, 0x08, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x28, 0x15, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, 0x18, 0x88, - 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0xed, 0x10, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, - 0x18, 0x88, 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x61, - 0x43, 0x32, 0x61, 0x43, 0x28, 0x0f, 0x01, 0x00, 0x4c, 0xa3, 0x58, 0x4a, 0x00, 0x00, 0x00, 0xfe, - 0x00, 0x4c, 0x54, 0x4e, 0x31, 0x32, 0x31, 0x58, 0x4a, 0x2d, 0x4c, 0x30, 0x37, 0x0a, 0x00, 0x00, -}; #define READ32(addr) io_i915_READ32(addr) #define WRITE32(val, addr) io_i915_WRITE32(val, addr) @@ -278,7 +269,8 @@ int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, int i915lightup(unsigned int pphysbase, unsigned int piobase, unsigned int pmmio, unsigned int pgfx) { - static struct edid edid; + struct edid edid; + u8 x60_edid_data[256]; int index; unsigned long temp; @@ -292,8 +284,8 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, (void *)graphics, mmio, addrport, physbase); globalstart = rdtscll(); - - decode_edid((unsigned char *)&x60_edid_data, + intel_gmbus_read_edid(pmmio, 3, 0x50, x60_edid_data); + decode_edid(x60_edid_data, sizeof(x60_edid_data), &edid); htotal = (edid.ha - 1) | ((edid.ha + edid.hbl - 1) << 16); diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 433152c..ad63c97 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -40,8 +40,8 @@ static void gma_func0_init(struct device *dev) /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); - + pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER + | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); #if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT /* PCI Init, will run VBIOS */ @@ -92,7 +92,7 @@ static void gma_func1_init(struct device *dev) /* IGD needs to be Bus Master, also enable IO accesss */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | - PCI_COMMAND_MASTER | PCI_COMMAND_IO); + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); if (get_option(&val, "tft_brightness") == CB_SUCCESS) pci_write_config8(dev, 0xf4, val);

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Patch set updated for coreboot: f9dcd62 NOTFORMERGE: x60gfx: step 1
by Vladimir Serbinenko 23 Feb '14

23 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5287 -gerrit commit f9dcd62ce07cd109150b95d90ac5f2e789501bb2 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 23 14:17:03 2014 +0100 NOTFORMERGE: x60gfx: step 1 Change-Id: I91c5619d7c2a212a55e301733374de8b23f8aa1f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/gma/edid.c | 4 ++-- src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/lenovo/x60/i915.c | 18 +++++------------- src/northbridge/intel/i945/gma.c | 6 +++--- 4 files changed, 11 insertions(+), 18 deletions(-) diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 0066b6a..bb6cba8 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -49,11 +49,11 @@ intel_gmbus_read_edid(u32 mmio, u8 bus, u8 slave, u8 *edid) wait_rdy(mmio); /* Ensure index bits are disabled. */ write32(mmio + PCH_GMBUS5, 0); - write32(mmio + PCH_GMBUS1, 0x46000000 | (slave << 1)); + write32(mmio + PCH_GMBUS1, 0x46000000 | 0x10000 | (slave << 1)); wait_rdy(mmio); /* Ensure index bits are disabled. */ write32(mmio + PCH_GMBUS5, 0); - write32(mmio + PCH_GMBUS1, 0x4a800001 | (slave << 1)); + write32(mmio + PCH_GMBUS1, 0x46800001 | (slave << 1)); for (i = 0; i < 128 / 4; i++) { u32 reg32; wait_rdy(mmio); diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 7ed2665..977d9e5 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT select H8_DOCK_EARLY_INIT + select INTEL_EDID config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 4870fd8..d420cb8 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -43,6 +43,7 @@ #include <cpu/x86/msr.h> #include <edid.h> #include "i915io.h" +#include <drivers/intel/gma/edid.h> enum { vmsg = 1, vio = 2, vspin = 4, @@ -64,16 +65,6 @@ static unsigned int physbase; static u32 htotal, hblank, hsync, vtotal, vblank, vsync; -const u8 x60_edid_data[] = { - 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0xae, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x0f, 0x01, 0x03, 0x80, 0x19, 0x12, 0x78, 0xea, 0xed, 0x75, 0x91, 0x57, 0x4f, 0x8b, 0x26, - 0x21, 0x50, 0x54, 0x21, 0x08, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x28, 0x15, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, 0x18, 0x88, - 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0xed, 0x10, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, - 0x18, 0x88, 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x61, - 0x43, 0x32, 0x61, 0x43, 0x28, 0x0f, 0x01, 0x00, 0x4c, 0xa3, 0x58, 0x4a, 0x00, 0x00, 0x00, 0xfe, - 0x00, 0x4c, 0x54, 0x4e, 0x31, 0x32, 0x31, 0x58, 0x4a, 0x2d, 0x4c, 0x30, 0x37, 0x0a, 0x00, 0x00, -}; #define READ32(addr) io_i915_READ32(addr) #define WRITE32(val, addr) io_i915_WRITE32(val, addr) @@ -278,7 +269,8 @@ int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, int i915lightup(unsigned int pphysbase, unsigned int piobase, unsigned int pmmio, unsigned int pgfx) { - static struct edid edid; + struct edid edid; + u8 x60_edid_data[256]; int index; unsigned long temp; @@ -292,8 +284,8 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, (void *)graphics, mmio, addrport, physbase); globalstart = rdtscll(); - - decode_edid((unsigned char *)&x60_edid_data, + intel_gmbus_read_edid(pmmio, 3, 0x50, x60_edid_data); + decode_edid(x60_edid_data, sizeof(x60_edid_data), &edid); htotal = (edid.ha - 1) | ((edid.ha + edid.hbl - 1) << 16); diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 433152c..ad63c97 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -40,8 +40,8 @@ static void gma_func0_init(struct device *dev) /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); - + pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER + | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); #if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT /* PCI Init, will run VBIOS */ @@ -92,7 +92,7 @@ static void gma_func1_init(struct device *dev) /* IGD needs to be Bus Master, also enable IO accesss */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | - PCI_COMMAND_MASTER | PCI_COMMAND_IO); + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); if (get_option(&val, "tft_brightness") == CB_SUCCESS) pci_write_config8(dev, 0xf4, val);

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Patch set updated for coreboot: 91dfb83 NOTFORMERGE: x60gfx: step 1
by Vladimir Serbinenko 23 Feb '14

23 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5287 -gerrit commit 91dfb8317bbb1454a461058b840595ef0deb6bcb Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 23 14:17:03 2014 +0100 NOTFORMERGE: x60gfx: step 1 Change-Id: I91c5619d7c2a212a55e301733374de8b23f8aa1f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/gma/edid.c | 4 ++-- src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/lenovo/x60/i915.c | 18 +++++------------- src/northbridge/intel/i945/gma.c | 2 +- 4 files changed, 9 insertions(+), 16 deletions(-) diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 0066b6a..bb6cba8 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -49,11 +49,11 @@ intel_gmbus_read_edid(u32 mmio, u8 bus, u8 slave, u8 *edid) wait_rdy(mmio); /* Ensure index bits are disabled. */ write32(mmio + PCH_GMBUS5, 0); - write32(mmio + PCH_GMBUS1, 0x46000000 | (slave << 1)); + write32(mmio + PCH_GMBUS1, 0x46000000 | 0x10000 | (slave << 1)); wait_rdy(mmio); /* Ensure index bits are disabled. */ write32(mmio + PCH_GMBUS5, 0); - write32(mmio + PCH_GMBUS1, 0x4a800001 | (slave << 1)); + write32(mmio + PCH_GMBUS1, 0x46800001 | (slave << 1)); for (i = 0; i < 128 / 4; i++) { u32 reg32; wait_rdy(mmio); diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 7ed2665..977d9e5 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT select H8_DOCK_EARLY_INIT + select INTEL_EDID config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 4870fd8..d420cb8 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -43,6 +43,7 @@ #include <cpu/x86/msr.h> #include <edid.h> #include "i915io.h" +#include <drivers/intel/gma/edid.h> enum { vmsg = 1, vio = 2, vspin = 4, @@ -64,16 +65,6 @@ static unsigned int physbase; static u32 htotal, hblank, hsync, vtotal, vblank, vsync; -const u8 x60_edid_data[] = { - 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0xae, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x0f, 0x01, 0x03, 0x80, 0x19, 0x12, 0x78, 0xea, 0xed, 0x75, 0x91, 0x57, 0x4f, 0x8b, 0x26, - 0x21, 0x50, 0x54, 0x21, 0x08, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x28, 0x15, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, 0x18, 0x88, - 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0xed, 0x10, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, - 0x18, 0x88, 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x61, - 0x43, 0x32, 0x61, 0x43, 0x28, 0x0f, 0x01, 0x00, 0x4c, 0xa3, 0x58, 0x4a, 0x00, 0x00, 0x00, 0xfe, - 0x00, 0x4c, 0x54, 0x4e, 0x31, 0x32, 0x31, 0x58, 0x4a, 0x2d, 0x4c, 0x30, 0x37, 0x0a, 0x00, 0x00, -}; #define READ32(addr) io_i915_READ32(addr) #define WRITE32(val, addr) io_i915_WRITE32(val, addr) @@ -278,7 +269,8 @@ int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, int i915lightup(unsigned int pphysbase, unsigned int piobase, unsigned int pmmio, unsigned int pgfx) { - static struct edid edid; + struct edid edid; + u8 x60_edid_data[256]; int index; unsigned long temp; @@ -292,8 +284,8 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, (void *)graphics, mmio, addrport, physbase); globalstart = rdtscll(); - - decode_edid((unsigned char *)&x60_edid_data, + intel_gmbus_read_edid(pmmio, 3, 0x50, x60_edid_data); + decode_edid(x60_edid_data, sizeof(x60_edid_data), &edid); htotal = (edid.ha - 1) | ((edid.ha + edid.hbl - 1) << 16); diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 433152c..9240686 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -92,7 +92,7 @@ static void gma_func1_init(struct device *dev) /* IGD needs to be Bus Master, also enable IO accesss */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | - PCI_COMMAND_MASTER | PCI_COMMAND_IO); + PCI_COMMAND_MASTER | PCI_COMMAND_MEM | PCI_COMMAND_IO); if (get_option(&val, "tft_brightness") == CB_SUCCESS) pci_write_config8(dev, 0xf4, val);

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Patch set updated for coreboot: 10f4afa NOTFORMERGE: x60gfx: step 1
by Vladimir Serbinenko 23 Feb '14

23 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5287 -gerrit commit 10f4afa135a80cac88059c9b3c09e288fbaf94fb Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 23 14:17:03 2014 +0100 NOTFORMERGE: x60gfx: step 1 Change-Id: I91c5619d7c2a212a55e301733374de8b23f8aa1f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/gma/edid.c | 4 ++-- src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/lenovo/x60/i915.c | 18 +++++------------- 3 files changed, 8 insertions(+), 15 deletions(-) diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 0066b6a..bb6cba8 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -49,11 +49,11 @@ intel_gmbus_read_edid(u32 mmio, u8 bus, u8 slave, u8 *edid) wait_rdy(mmio); /* Ensure index bits are disabled. */ write32(mmio + PCH_GMBUS5, 0); - write32(mmio + PCH_GMBUS1, 0x46000000 | (slave << 1)); + write32(mmio + PCH_GMBUS1, 0x46000000 | 0x10000 | (slave << 1)); wait_rdy(mmio); /* Ensure index bits are disabled. */ write32(mmio + PCH_GMBUS5, 0); - write32(mmio + PCH_GMBUS1, 0x4a800001 | (slave << 1)); + write32(mmio + PCH_GMBUS1, 0x46800001 | (slave << 1)); for (i = 0; i < 128 / 4; i++) { u32 reg32; wait_rdy(mmio); diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 7ed2665..977d9e5 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT select H8_DOCK_EARLY_INIT + select INTEL_EDID config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 4870fd8..d420cb8 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -43,6 +43,7 @@ #include <cpu/x86/msr.h> #include <edid.h> #include "i915io.h" +#include <drivers/intel/gma/edid.h> enum { vmsg = 1, vio = 2, vspin = 4, @@ -64,16 +65,6 @@ static unsigned int physbase; static u32 htotal, hblank, hsync, vtotal, vblank, vsync; -const u8 x60_edid_data[] = { - 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0xae, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x0f, 0x01, 0x03, 0x80, 0x19, 0x12, 0x78, 0xea, 0xed, 0x75, 0x91, 0x57, 0x4f, 0x8b, 0x26, - 0x21, 0x50, 0x54, 0x21, 0x08, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x28, 0x15, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, 0x18, 0x88, - 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0xed, 0x10, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, - 0x18, 0x88, 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x61, - 0x43, 0x32, 0x61, 0x43, 0x28, 0x0f, 0x01, 0x00, 0x4c, 0xa3, 0x58, 0x4a, 0x00, 0x00, 0x00, 0xfe, - 0x00, 0x4c, 0x54, 0x4e, 0x31, 0x32, 0x31, 0x58, 0x4a, 0x2d, 0x4c, 0x30, 0x37, 0x0a, 0x00, 0x00, -}; #define READ32(addr) io_i915_READ32(addr) #define WRITE32(val, addr) io_i915_WRITE32(val, addr) @@ -278,7 +269,8 @@ int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, int i915lightup(unsigned int pphysbase, unsigned int piobase, unsigned int pmmio, unsigned int pgfx) { - static struct edid edid; + struct edid edid; + u8 x60_edid_data[256]; int index; unsigned long temp; @@ -292,8 +284,8 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, (void *)graphics, mmio, addrport, physbase); globalstart = rdtscll(); - - decode_edid((unsigned char *)&x60_edid_data, + intel_gmbus_read_edid(pmmio, 3, 0x50, x60_edid_data); + decode_edid(x60_edid_data, sizeof(x60_edid_data), &edid); htotal = (edid.ha - 1) | ((edid.ha + edid.hbl - 1) << 16);

1 0

Patch set updated for coreboot: c4dbe00 NOTFORMERGE: x60gfx: step 1
by Vladimir Serbinenko 23 Feb '14

23 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5287 -gerrit commit c4dbe006f126a6c2b36f533601f7dc3bc6d86990 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 23 14:17:03 2014 +0100 NOTFORMERGE: x60gfx: step 1 Change-Id: I91c5619d7c2a212a55e301733374de8b23f8aa1f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/lenovo/x60/i915.c | 18 +++++------------- 2 files changed, 6 insertions(+), 13 deletions(-) diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 7ed2665..977d9e5 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT select H8_DOCK_EARLY_INIT + select INTEL_EDID config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 4870fd8..d420cb8 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -43,6 +43,7 @@ #include <cpu/x86/msr.h> #include <edid.h> #include "i915io.h" +#include <drivers/intel/gma/edid.h> enum { vmsg = 1, vio = 2, vspin = 4, @@ -64,16 +65,6 @@ static unsigned int physbase; static u32 htotal, hblank, hsync, vtotal, vblank, vsync; -const u8 x60_edid_data[] = { - 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0xae, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x0f, 0x01, 0x03, 0x80, 0x19, 0x12, 0x78, 0xea, 0xed, 0x75, 0x91, 0x57, 0x4f, 0x8b, 0x26, - 0x21, 0x50, 0x54, 0x21, 0x08, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x28, 0x15, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, 0x18, 0x88, - 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0xed, 0x10, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, - 0x18, 0x88, 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x61, - 0x43, 0x32, 0x61, 0x43, 0x28, 0x0f, 0x01, 0x00, 0x4c, 0xa3, 0x58, 0x4a, 0x00, 0x00, 0x00, 0xfe, - 0x00, 0x4c, 0x54, 0x4e, 0x31, 0x32, 0x31, 0x58, 0x4a, 0x2d, 0x4c, 0x30, 0x37, 0x0a, 0x00, 0x00, -}; #define READ32(addr) io_i915_READ32(addr) #define WRITE32(val, addr) io_i915_WRITE32(val, addr) @@ -278,7 +269,8 @@ int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, int i915lightup(unsigned int pphysbase, unsigned int piobase, unsigned int pmmio, unsigned int pgfx) { - static struct edid edid; + struct edid edid; + u8 x60_edid_data[256]; int index; unsigned long temp; @@ -292,8 +284,8 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, (void *)graphics, mmio, addrport, physbase); globalstart = rdtscll(); - - decode_edid((unsigned char *)&x60_edid_data, + intel_gmbus_read_edid(pmmio, 3, 0x50, x60_edid_data); + decode_edid(x60_edid_data, sizeof(x60_edid_data), &edid); htotal = (edid.ha - 1) | ((edid.ha + edid.hbl - 1) << 16);

1 0

Patch set updated for coreboot: 92bb344 ivybridge: LVDS gfx init.
by Vladimir Serbinenko 23 Feb '14

23 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5285 -gerrit commit 92bb34480db1d1822248c405777b70fe6431105c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 23 00:10:35 2014 +0100 ivybridge: LVDS gfx init. Change-Id: If71e9c94922cd4283d5e175dfd8757d398a72be1 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/gma/i915_reg.h | 5 + src/mainboard/lenovo/x230/Kconfig | 5 + src/mainboard/lenovo/x230/devicetree.cb | 6 + src/northbridge/intel/sandybridge/Kconfig | 4 + src/northbridge/intel/sandybridge/Makefile.inc | 1 + src/northbridge/intel/sandybridge/chip.h | 5 + .../intel/sandybridge/gma_ivybridge_lvds.c | 514 +++++++++++++++++++++ 7 files changed, 540 insertions(+) diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 8c08d9f..820d10e 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -4049,6 +4049,11 @@ #define PCH_LVDS 0xe1180 #define LVDS_DETECTED (1 << 1) +#define LVDS_BORDER_ENABLE (1 << 15) +#define LVDS_PORT_ENABLE (1 << 31) +#define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) +#define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) +#define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) /* vlv has 2 sets of panel control regs. */ #define PIPEA_PP_STATUS 0x61200 diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index cd1f761..7d03c50 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -16,6 +16,11 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select GFXUMA select EARLY_CBMEM_INIT + select VGA + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_NATIVE_VGA_INIT_TEXTMODECFG + select IVYBRIDGE_LVDS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index a76de5f..1a93ad8 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -10,6 +10,12 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms + register "gpu_use_spread_spectrum_clock" = "1" + register "gpu_lvds_dual_channel" = "0" + register "gpu_link_frequency_270_mhz" = "1" + register "gpu_lvds_num_lanes" = "1" + register "gpu_cpu_backlight" = "0x1155" + register "gpu_pch_backlight" = "0x11551155" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 83da527..fb92e40 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -41,6 +41,10 @@ config CACHE_MRC_SIZE_KB int default 512 +config IVYBRIDGE_LVDS + bool + default n + config MRC_CACHE_SIZE hex depends on !CHROMEOS diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index a201745..6655e2a 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -20,6 +20,7 @@ ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c +ramstage-$(CONFIG_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-y += mrccache.c diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index 16df91b..e55d593 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -38,5 +38,10 @@ struct northbridge_intel_sandybridge_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ + + int gpu_use_spread_spectrum_clock; + int gpu_lvds_dual_channel; + int gpu_link_frequency_270_mhz; + int gpu_lvds_num_lanes; }; diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c new file mode 100644 index 0000000..1e7c446 --- /dev/null +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -0,0 +1,514 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013, 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 or (at your option) + * any later version of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <string.h> + +#include <drivers/intel/gma/edid.h> +#include <drivers/intel/gma/i915.h> +#include "gma.h" +#include "chip.h" +#include <pc80/vga.h> +#include <pc80/vga_io.h> + +#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) + +static void link_train(u32 mmio) +{ + write32(mmio+0xf000c,0x40); + write32(mmio+0x60100,0x40000); + write32(mmio+0xf0018,0x8ff); + write32(mmio+0xf1018,0x8ff); + write32(mmio+0xf000c,0x2040); + mdelay(1); + write32(mmio+0xf000c,0x2050); + write32(mmio+0x60100,0x44000); + mdelay(1); + write32(mmio+0x70008,0x40); + write32(mmio+0xe0300,0x60000418); + write32(mmio+0xf000c,0x22050); + write32(mmio+0x70008,0x50); + write32(mmio+0x70008,0x80000050); +} + +static void link_normal_operation(u32 mmio) +{ + write32(mmio + FDI_TX_CTL(0), 0x80044f02); + write32(mmio + FDI_RX_CTL(0), + FDI_RX_ENABLE | FDI_6BPC + | 0x2f50); +} + +static void enable_port(u32 mmio) +{ + write32(mmio + 0xec008, 0x2c010000); + write32(mmio + 0xec020, 0x2c010000); + write32(mmio + 0xec038, 0x2c010000); + write32(mmio + 0xec050, 0x2c010000); + write32(mmio + 0xec408, 0x2c010000); + write32(mmio + 0xec420, 0x2c010000); + write32(mmio + 0xec438, 0x2c010000); + write32(mmio + 0xec450, 0x2c010000); + write32(mmio + 0xf0010, 0x200090); + write32(mmio + 0xf1010, 0x200090); + write32(mmio + 0xf2010, 0x200090); + write32(mmio + 0xfd034, 0x8420000); + write32(mmio + 0x45010, 0x3); + write32(mmio + 0xf0060, 0x10); + write32(mmio + 0xf1060, 0x10); + write32(mmio + 0xf2060, 0x10); + write32(mmio + 0x9840, 0x0); + write32(mmio + 0x42000, 0xa0000000); + write32(mmio + 0xe4f00, 0x100030c); + write32(mmio + 0xe4f04, 0xb8230c); + write32(mmio + 0xe4f08, 0x6f8930c); + write32(mmio + 0xe4f0c, 0x5f8e38e); + write32(mmio + 0xe4f10, 0xb8030c); + write32(mmio + 0xe4f14, 0xb78830c); + write32(mmio + 0xe4f18, 0x9f8d3cf); + write32(mmio + 0xe4f1c, 0x1e8030c); + write32(mmio + 0xe4f20, 0x9f863cf); + write32(mmio + 0xe4f24, 0xff803cf); + read32(mmio + 0xe4100); + write32(mmio + 0xc4030, 0x10); + write32(mmio + 0xe4110, 0x8004003e); + write32(mmio + 0xe4114, 0x80060000); + write32(mmio + 0xe4118, 0x1000000); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x5344003e); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x8054003e); + read32(mmio + 0xe4110); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x5344003e); + mdelay(1); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x8054003e); + read32(mmio + 0xe4110); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x5344003e); + mdelay(1); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x8054003e); + read32(mmio + 0xe4110); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x5344003e); + mdelay(1); + read32(mmio + 0xc4000); + read32(mmio + 0xe1140); + write32(mmio + 0xc4030, 0x10); + read32(mmio + 0xc4000); + write32(mmio + 0xe4f00, 0x100030c); + write32(mmio + 0xe4f04, 0xb8230c); + write32(mmio + 0xe4f08, 0x6f8930c); + write32(mmio + 0xe4f0c, 0x5f8e38e); + write32(mmio + 0xe4f10, 0xb8030c); + write32(mmio + 0xe4f14, 0xb78830c); + write32(mmio + 0xe4f18, 0x9f8d3cf); + write32(mmio + 0xe4f1c, 0x1e8030c); + write32(mmio + 0xe4f20, 0x9f863cf); + write32(mmio + 0xe4f24, 0xff803cf); + read32(mmio + 0xe4200); + write32(mmio + 0xc4030, 0x1010); + write32(mmio + 0xe4210, 0x8004003e); + write32(mmio + 0xe4214, 0x80060000); + write32(mmio + 0xe4218, 0x1002000); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x5344003e); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x8054003e); + read32(mmio + 0xe4210); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x5344003e); + mdelay(1); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x8054003e); + read32(mmio + 0xe4210); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x5344003e); + mdelay(1); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x8054003e); + read32(mmio + 0xe4210); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x5344003e); + mdelay(1); + read32(mmio + 0xc4000); +} + +void i915lightup(const struct northbridge_intel_sandybridge_config *info, + u32 physbase, u16 piobase, u32 mmio, u32 lfb) +{ + int i; + u8 edid_data[128]; + struct edid edid; + + write32(mmio + 0x00070080, 0x00000000); + write32(mmio + DSPCNTR(0), 0x00000000); + write32(mmio + 0x00071180, 0x00000000); + write32(mmio + CPU_VGACNTRL, 0x0000298e | VGA_DISP_DISABLE); + write32(mmio + 0x0007019c, 0x00000000); + write32(mmio + 0x0007119c, 0x00000000); + write32(mmio + 0x000fc008, 0x2c010000); + write32(mmio + 0x000fc020, 0x2c010000); + write32(mmio + 0x000fc038, 0x2c010000); + write32(mmio + 0x000fc050, 0x2c010000); + write32(mmio + 0x000fc408, 0x2c010000); + write32(mmio + 0x000fc420, 0x2c010000); + write32(mmio + 0x000fc438, 0x2c010000); + write32(mmio + 0x000fc450, 0x2c010000); + vga_gr_write(0x18, 0); + write32(mmio + 0x00042004, 0x02000000); + write32(mmio + 0x000fd034, 0x8421ffe0); + + /* Setup GTT. */ + for (i = 0; i < 0x2000; i++) + { + outl((i << 2) | 1, piobase); + outl(physbase + (i << 12) + 1, piobase + 4); + } + + vga_misc_write(0x67); + + u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, + 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, + 0xff + }; + vga_cr_write(0x11, 0); + + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + + enable_port(mmio); + + intel_gmbus_read_edid(mmio, 3, 0x50, edid_data); + decode_edid(edid_data, + sizeof(edid_data), &edid); + + + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + u32 hactive = edid.x_resolution; + u32 vactive = edid.y_resolution; + u32 right_border = edid.hborder; + u32 bottom_border = edid.vborder; + int hpolarity = (edid.phsync == '-'); + int vpolarity = (edid.pvsync == '-'); + u32 vsync = edid.vspw; + u32 hsync = edid.hspw; + u32 vblank = edid.vbl; + u32 hblank = edid.hbl; + u32 hfront_porch = edid.hso; + u32 vfront_porch = edid.vso; + + u32 candp1, candn; + u32 best_delta = 0xffffffff; + + u32 target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + : (2 * edid.pixel_clock); + u32 pixel_p1 = 1; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; + +#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + vga_textmode_init(); +#else + vga_sr_write(1, 1); + vga_sr_write(0x2, 0xf); + vga_sr_write(0x3, 0x0); + vga_sr_write(0x4, 0xe); + vga_gr_write(0, 0x0); + vga_gr_write(1, 0x0); + vga_gr_write(2, 0x0); + vga_gr_write(3, 0x0); + vga_gr_write(4, 0x0); + vga_gr_write(5, 0x0); + vga_gr_write(6, 0x5); + vga_gr_write(7, 0xf); + vga_gr_write(0x10, 0x1); + vga_gr_write(0x11, 0); + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + + write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888); + write32(mmio + DSPADDR(0), 0); + write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(mmio + DSPSURF(0), 0); + for (i = 0; i < 0x100; i++) + write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); +#endif + + /* Find suitable divisors. */ + for (candp1 = 1; candp1 <= 8; candp1++) { + for (candn = 5; candn <= 10; candn++) { + u32 cur_frequency; + u32 m; /* 77 - 131. */ + u32 denom; /* 35 - 560. */ + u32 current_delta; + + denom = candn * candp1 * 7; + /* Doesnt overflow for up to + 5000000 kHz = 5 GHz. */ + m = (target_frequency * denom + 60000) / 120000; + + if (m < 77 || m > 131) + continue; + + cur_frequency = (120000 * m) / denom; + if (target_frequency > cur_frequency) + current_delta = target_frequency - cur_frequency; + else + current_delta = cur_frequency - target_frequency; + + + if (best_delta > current_delta) { + best_delta = current_delta; + pixel_n = candn; + pixel_p1 = candp1; + pixel_m2 = ((m + 3) % 5) + 7; + pixel_m1 = (m - pixel_m2) / 5; + } + } + } + + if (best_delta == 0xffffffff) { + printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return; + } + + u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 data_m1; + u32 data_n1 = 0x00800000; + u32 link_m1; + u32 link_n1 = 0x00080000; + + link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; + + data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) + / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 1)); + + printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", + hactive, vactive); + printk(BIOS_DEBUG, "Borders %d x %d\n", + right_border, bottom_border); + printk(BIOS_DEBUG, "Blank %d x %d\n", + hblank, vblank); + printk(BIOS_DEBUG, "Sync %d x %d\n", + hsync, vsync); + printk(BIOS_DEBUG, "Front porch %d x %d\n", + hfront_porch, vfront_porch); + printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + ? "Spread spectrum clock\n" : "DREF clock\n")); + printk(BIOS_DEBUG, + info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + printk(BIOS_DEBUG, "Polarities %d, %d\n", + hpolarity, vpolarity); + printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", + data_m1, data_n1); + printk(BIOS_DEBUG, "Link frequency %d kHz\n", + link_frequency); + printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", + link_m1, link_n1); + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", + 120000 * (5 * pixel_m1 + pixel_m2) / pixel_n + / (pixel_p1 * 7)); + + write32(mmio + PCH_LVDS, + (hpolarity << 20) | (vpolarity << 21) + | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_DETECTED); + write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); + write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock + ? 0x1002 : 0x400)); + mdelay(1); + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(mmio + _PCH_FP0(0), + ((pixel_n - 2) << 16) + | ((pixel_m1 - 2) << 8) | pixel_m2); + write32(mmio + _PCH_DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + + mdelay(1); + write32(mmio + 0xc7000, 0x8); + + mdelay(1); + write32(mmio + _PCH_DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + /* Re-lock the registers. */ + write32(mmio + PCH_PP_CONTROL, + (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + + write32(mmio + PCH_LVDS, + (hpolarity << 20) | (vpolarity << 21) + | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_DETECTED); + + write32(mmio + HTOTAL(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); + write32(mmio + HSYNC(0), + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); + + write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), + (vactive + bottom_border + vfront_porch + vsync - 1) + | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + 0xf0008, 0); + +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1)); + write32(mmio + PF_CTL(0),0); + write32(mmio + PF_WIN_SZ(0), 0); + write32(mmio + PF_WIN_POS(0), 0); +#else + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(mmio + PF_WIN_POS(0), 0); +#endif + + mdelay(1); + + write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); + write32(mmio + PIPE_DATA_N1(0), data_n1); + write32(mmio + PIPE_LINK_M1(0), link_m1); + write32(mmio + PIPE_LINK_N1(0), link_n1); + + link_train(mmio); +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(mmio+CPU_VGACNTRL,0x298e | VGA_DISP_DISABLE); +#else + write32(mmio+CPU_VGACNTRL,0x298e); +#endif + write32(mmio+0x60100,0x44300); + write32(mmio+0x60100,0x80044f00); + + mdelay(1); + read32(mmio + 0x000f0014); // = 0x00000600 + +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); + mdelay(1); +#endif + + write32(mmio + TRANS_HTOTAL(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + TRANS_HBLANK(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); + write32(mmio + TRANS_HSYNC(0), + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); + + write32(mmio + TRANS_VTOTAL(0), + ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); + write32(mmio + TRANS_VBLANK(0), + ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); + write32(mmio + TRANS_VSYNC(0), + (vactive + bottom_border + vfront_porch + vsync - 1) + | (vactive + bottom_border + vfront_porch - 1)); + + link_normal_operation(mmio); + + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + + mdelay(1); + + write32(mmio + PCH_TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + | TRANS_STATE_MASK +#endif + ); + write32(mmio + PCH_LVDS, + LVDS_PORT_ENABLE + | (hpolarity << 20) | (vpolarity << 21) + | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_DETECTED); + + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); + mdelay(1); + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS + | PANEL_POWER_ON | PANEL_POWER_RESET); + + printk (BIOS_DEBUG, "waiting for panel powerup\n"); + while (1) + { + u32 reg32; + reg32 = read32(mmio + PCH_PP_STATUS); + if (((reg32 >> 28) & 3) == 0) + break; + } + printk (BIOS_DEBUG, "panel powered up\n"); + + write32(mmio + PCH_PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + + /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); + +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4); + set_vbe_mode_info_valid(&edid, lfb); +#endif +} + +#endif

1 0

New patch to review for coreboot: 909d72e NOTFORMERGE: x60gfx: step 1
by Vladimir Serbinenko 23 Feb '14

23 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5287 -gerrit commit 909d72e779aeb7588bd57d9d14b3aff1f84171f4 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 23 14:17:03 2014 +0100 NOTFORMERGE: x60gfx: step 1 Change-Id: I91c5619d7c2a212a55e301733374de8b23f8aa1f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x60/i915.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 4870fd8..9d9d106 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -64,16 +64,6 @@ static unsigned int physbase; static u32 htotal, hblank, hsync, vtotal, vblank, vsync; -const u8 x60_edid_data[] = { - 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0xae, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x0f, 0x01, 0x03, 0x80, 0x19, 0x12, 0x78, 0xea, 0xed, 0x75, 0x91, 0x57, 0x4f, 0x8b, 0x26, - 0x21, 0x50, 0x54, 0x21, 0x08, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x28, 0x15, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, 0x18, 0x88, - 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0xed, 0x10, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, - 0x18, 0x88, 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x61, - 0x43, 0x32, 0x61, 0x43, 0x28, 0x0f, 0x01, 0x00, 0x4c, 0xa3, 0x58, 0x4a, 0x00, 0x00, 0x00, 0xfe, - 0x00, 0x4c, 0x54, 0x4e, 0x31, 0x32, 0x31, 0x58, 0x4a, 0x2d, 0x4c, 0x30, 0x37, 0x0a, 0x00, 0x00, -}; #define READ32(addr) io_i915_READ32(addr) #define WRITE32(val, addr) io_i915_WRITE32(val, addr) @@ -278,7 +268,8 @@ int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, int i915lightup(unsigned int pphysbase, unsigned int piobase, unsigned int pmmio, unsigned int pgfx) { - static struct edid edid; + struct edid edid; + u8 x60_edid_data[256]; int index; unsigned long temp; @@ -292,8 +283,8 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, (void *)graphics, mmio, addrport, physbase); globalstart = rdtscll(); - - decode_edid((unsigned char *)&x60_edid_data, + intel_gmbus_read_edid(pmmio, 3, 0x50, x60_edid_data); + decode_edid(x60_edid_data, sizeof(x60_edid_data), &edid); htotal = (edid.ha - 1) | ((edid.ha + edid.hbl - 1) << 16);

1 0

Patch set updated for coreboot: 0b3e7ea gma: Add EDID retrieving functions.
by Vladimir Serbinenko 23 Feb '14

23 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5278 -gerrit commit 0b3e7eaabe954a65766a7b117d580c6d549bb499 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Feb 21 07:21:00 2014 +0100 gma: Add EDID retrieving functions. Change-Id: I64f2fcc5ad52d6a0188d02b28769001ada718c4f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/Makefile.inc | 2 +- src/drivers/intel/gma/Kconfig | 4 ++ src/drivers/intel/gma/Makefile.inc | 2 +- src/drivers/intel/gma/edid.c | 78 ++++++++++++++++++++++++++++++++++++++ src/drivers/intel/gma/edid.h | 2 + 5 files changed, 86 insertions(+), 2 deletions(-) diff --git a/src/drivers/intel/Makefile.inc b/src/drivers/intel/Makefile.inc index 82d5449..eb8617c 100644 --- a/src/drivers/intel/Makefile.inc +++ b/src/drivers/intel/Makefile.inc @@ -1 +1 @@ -subdirs-$(CONFIG_INTEL_DP) += gma +subdirs-y += gma diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 073f708..e26c297 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -28,3 +28,7 @@ config INTEL_DDI default n help helper functions for intel DDI operations + +config INTEL_EDID + bool + default n diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index 0c3f45a..bea597e 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -19,4 +19,4 @@ ramstage-$(CONFIG_INTEL_DP) += intel_dp.c drm_dp_helper.c ramstage-$(CONFIG_INTEL_DDI) += intel_ddi.c - +ramstage-$(CONFIG_INTEL_EDID) += edid.c diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c new file mode 100644 index 0000000..0066b6a --- /dev/null +++ b/src/drivers/intel/gma/edid.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko <phcoder(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2, or (at your option) + * any later verion of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> + +#include "i915_reg.h" +#include "edid.h" + +static void +wait_rdy(u32 mmio) +{ + unsigned try = 100; + + while (try--) { + if (read32(mmio + PCH_GMBUS2) & (1 << 11)) + return; + udelay(10); + } +} + +void +intel_gmbus_read_edid(u32 mmio, u8 bus, u8 slave, u8 *edid) +{ + int i; + + wait_rdy(mmio); + /* 100 KHz, hold 0ns, */ + write32(mmio + PCH_GMBUS0, bus); + wait_rdy(mmio); + /* Ensure index bits are disabled. */ + write32(mmio + PCH_GMBUS5, 0); + write32(mmio + PCH_GMBUS1, 0x46000000 | (slave << 1)); + wait_rdy(mmio); + /* Ensure index bits are disabled. */ + write32(mmio + PCH_GMBUS5, 0); + write32(mmio + PCH_GMBUS1, 0x4a800001 | (slave << 1)); + for (i = 0; i < 128 / 4; i++) { + u32 reg32; + wait_rdy(mmio); + reg32 = read32(mmio + PCH_GMBUS3); + edid[4 * i] = reg32 & 0xff; + edid[4 * i + 1] = (reg32 >> 8) & 0xff; + edid[4 * i + 2] = (reg32 >> 16) & 0xff; + edid[4 * i + 3] = (reg32 >> 24) & 0xff; + } + wait_rdy(mmio); + write32(mmio + PCH_GMBUS1, 0x4a800000 | (slave << 1)); + wait_rdy(mmio); + write32(mmio + PCH_GMBUS0, 0x48000000); + write32(mmio + PCH_GMBUS2, 0x00008000); + + printk (BIOS_INFO, "EDID:\n"); + for (i = 0; i < 128; i++) { + printk (BIOS_INFO, "%02x ", edid[i]); + if ((i & 0xf) == 0xf) + printk (BIOS_INFO, "\n"); + } +} diff --git a/src/drivers/intel/gma/edid.h b/src/drivers/intel/gma/edid.h new file mode 100644 index 0000000..1d91f70 --- /dev/null +++ b/src/drivers/intel/gma/edid.h @@ -0,0 +1,2 @@ +void +intel_gmbus_read_edid(u32 mmio, u8 bus, u8 slave, u8 *edid);

1 0

New patch to review for coreboot: ca15c60 jetway/nf81-t56n-lf: Use proper category.
by Vladimir Serbinenko 23 Feb '14

23 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5286 -gerrit commit ca15c6061acde237d5af810857a1bde3b146579b Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 23 14:06:58 2014 +0100 jetway/nf81-t56n-lf: Use proper category. "Mini-ITX" was a pure inventional name for category called "mini". Change-Id: I6450fd27c1a7679f252ce7f46f409b7dc459c50d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/jetway/nf81-t56n-lf/board_info.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/board_info.txt b/src/mainboard/jetway/nf81-t56n-lf/board_info.txt index 6748751..0253ea2 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/board_info.txt +++ b/src/mainboard/jetway/nf81-t56n-lf/board_info.txt @@ -1,5 +1,5 @@ Board URL: http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=822&proname=NF81-T5… -Category: Mini-ITX +Category: mini ROM package: SOIC8 ROM protocol: SPI ROM socketed: n

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New patch to review for coreboot: cda2098 ivybridge: LVDS gfx init.
by Vladimir Serbinenko 22 Feb '14

22 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5285 -gerrit commit cda209878f8e591426dcccae4f423898a0f68a8f Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 23 00:10:35 2014 +0100 ivybridge: LVDS gfx init. Change-Id: If71e9c94922cd4283d5e175dfd8757d398a72be1 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/gma/i915_reg.h | 5 + src/mainboard/lenovo/x230/Kconfig | 5 + src/mainboard/lenovo/x230/devicetree.cb | 6 + src/northbridge/intel/sandybridge/Kconfig | 4 + src/northbridge/intel/sandybridge/Makefile.inc | 1 + src/northbridge/intel/sandybridge/chip.h | 5 + .../intel/sandybridge/gma_ivybridge_lvds.c | 514 +++++++++++++++++++++ 7 files changed, 540 insertions(+) diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 8c08d9f..820d10e 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -4049,6 +4049,11 @@ #define PCH_LVDS 0xe1180 #define LVDS_DETECTED (1 << 1) +#define LVDS_BORDER_ENABLE (1 << 15) +#define LVDS_PORT_ENABLE (1 << 31) +#define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) +#define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) +#define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) /* vlv has 2 sets of panel control regs. */ #define PIPEA_PP_STATUS 0x61200 diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index cd1f761..7d03c50 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -16,6 +16,11 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select GFXUMA select EARLY_CBMEM_INIT + select VGA + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_NATIVE_VGA_INIT_TEXTMODECFG + select IVYBRIDGE_LVDS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index a76de5f..1a93ad8 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -10,6 +10,12 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms + register "gpu_use_spread_spectrum_clock" = "1" + register "gpu_lvds_dual_channel" = "0" + register "gpu_link_frequency_270_mhz" = "1" + register "gpu_lvds_num_lanes" = "1" + register "gpu_cpu_backlight" = "0x1155" + register "gpu_pch_backlight" = "0x11551155" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 83da527..fb92e40 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -41,6 +41,10 @@ config CACHE_MRC_SIZE_KB int default 512 +config IVYBRIDGE_LVDS + bool + default n + config MRC_CACHE_SIZE hex depends on !CHROMEOS diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index a201745..6655e2a 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -20,6 +20,7 @@ ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c +ramstage-$(CONFIG_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-y += mrccache.c diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index 16df91b..e55d593 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -38,5 +38,10 @@ struct northbridge_intel_sandybridge_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ + + int gpu_use_spread_spectrum_clock; + int gpu_lvds_dual_channel; + int gpu_link_frequency_270_mhz; + int gpu_lvds_num_lanes; }; diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c new file mode 100644 index 0000000..bc84c2d --- /dev/null +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -0,0 +1,514 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013, 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 or (at your option) + * any later version of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <string.h> + +#include <drivers/intel/gma/edid.h> +#include <drivers/intel/gma/i915.h> +#include "gma.h" +#include "chip.h" +#include <pc80/vga.h> +#include <pc80/vga_io.h> + +#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) + +static void link_train(u32 mmio) +{ + write32(mmio+0xf000c,0x40); + write32(mmio+0x60100,0x40000); + write32(mmio+0xf0018,0x8ff); + write32(mmio+0xf1018,0x8ff); + write32(mmio+0xf000c,0x2040); + mdelay(1); + write32(mmio+0xf000c,0x2050); + write32(mmio+0x60100,0x44000); + mdelay(1); + write32(mmio+0x70008,0x40); + write32(mmio+0xe0300,0x60000418); + write32(mmio+0xf000c,0x22050); + write32(mmio+0x70008,0x50); + write32(mmio+0x70008,0x80000050); +} + +static void link_normal_operation(u32 mmio) +{ + write32(mmio + FDI_TX_CTL(0), 0x80044f02); + write32(mmio + FDI_RX_CTL(0), + FDI_RX_ENABLE | FDI_6BPC + | 0x2f50); +} + +static void enable_port(u32 mmio) +{ + write32(mmio + 0xec008, 0x2c010000); + write32(mmio + 0xec020, 0x2c010000); + write32(mmio + 0xec038, 0x2c010000); + write32(mmio + 0xec050, 0x2c010000); + write32(mmio + 0xec408, 0x2c010000); + write32(mmio + 0xec420, 0x2c010000); + write32(mmio + 0xec438, 0x2c010000); + write32(mmio + 0xec450, 0x2c010000); + write32(mmio + 0xf0010, 0x200090); + write32(mmio + 0xf1010, 0x200090); + write32(mmio + 0xf2010, 0x200090); + write32(mmio + 0xfd034, 0x8420000); + write32(mmio + 0x45010, 0x3); + write32(mmio + 0xf0060, 0x10); + write32(mmio + 0xf1060, 0x10); + write32(mmio + 0xf2060, 0x10); + write32(mmio + 0x9840, 0x0); + write32(mmio + 0x42000, 0xa0000000); + write32(mmio + 0xe4f00, 0x100030c); + write32(mmio + 0xe4f04, 0xb8230c); + write32(mmio + 0xe4f08, 0x6f8930c); + write32(mmio + 0xe4f0c, 0x5f8e38e); + write32(mmio + 0xe4f10, 0xb8030c); + write32(mmio + 0xe4f14, 0xb78830c); + write32(mmio + 0xe4f18, 0x9f8d3cf); + write32(mmio + 0xe4f1c, 0x1e8030c); + write32(mmio + 0xe4f20, 0x9f863cf); + write32(mmio + 0xe4f24, 0xff803cf); + read32(mmio + 0xe4100); + write32(mmio + 0xc4030, 0x10); + write32(mmio + 0xe4110, 0x8004003e); + write32(mmio + 0xe4114, 0x80060000); + write32(mmio + 0xe4118, 0x1000000); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x5344003e); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x8054003e); + read32(mmio + 0xe4110); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x5344003e); + mdelay(1); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x8054003e); + read32(mmio + 0xe4110); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x5344003e); + mdelay(1); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x8054003e); + read32(mmio + 0xe4110); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x5344003e); + mdelay(1); + read32(mmio + 0xc4000); + read32(mmio + 0xe1140); + write32(mmio + 0xc4030, 0x10); + read32(mmio + 0xc4000); + write32(mmio + 0xe4f00, 0x100030c); + write32(mmio + 0xe4f04, 0xb8230c); + write32(mmio + 0xe4f08, 0x6f8930c); + write32(mmio + 0xe4f0c, 0x5f8e38e); + write32(mmio + 0xe4f10, 0xb8030c); + write32(mmio + 0xe4f14, 0xb78830c); + write32(mmio + 0xe4f18, 0x9f8d3cf); + write32(mmio + 0xe4f1c, 0x1e8030c); + write32(mmio + 0xe4f20, 0x9f863cf); + write32(mmio + 0xe4f24, 0xff803cf); + read32(mmio + 0xe4200); + write32(mmio + 0xc4030, 0x1010); + write32(mmio + 0xe4210, 0x8004003e); + write32(mmio + 0xe4214, 0x80060000); + write32(mmio + 0xe4218, 0x1002000); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x5344003e); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x8054003e); + read32(mmio + 0xe4210); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x5344003e); + mdelay(1); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x8054003e); + read32(mmio + 0xe4210); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x5344003e); + mdelay(1); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x8054003e); + read32(mmio + 0xe4210); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x5344003e); + mdelay(1); + read32(mmio + 0xc4000); +} + +void i915lightup(const struct northbridge_intel_sandybridge_config *info, + u32 physbase, u16 piobase, u32 mmio, u32 lfb) +{ + int i; + u8 edid_data[128]; + struct edid edid; + + write32(mmio + 0x00070080, 0x00000000); + write32(mmio + DSPCNTR(0), 0x00000000); + write32(mmio + 0x00071180, 0x00000000); + write32(mmio + CPU_VGACNTRL, 0x0000298e | VGA_DISP_DISABLE); + write32(mmio + 0x0007019c, 0x00000000); + write32(mmio + 0x0007119c, 0x00000000); + write32(mmio + 0x000fc008, 0x2c010000); + write32(mmio + 0x000fc020, 0x2c010000); + write32(mmio + 0x000fc038, 0x2c010000); + write32(mmio + 0x000fc050, 0x2c010000); + write32(mmio + 0x000fc408, 0x2c010000); + write32(mmio + 0x000fc420, 0x2c010000); + write32(mmio + 0x000fc438, 0x2c010000); + write32(mmio + 0x000fc450, 0x2c010000); + vga_gr_write(0x18, 0); + write32(mmio + 0x00042004, 0x02000000); + write32(mmio + 0x000fd034, 0x8421ffe0); + + /* Setup GTT. */ + for (i = 0; i < 0x2000; i++) + { + outl((i << 2) | 1, piobase); + outl(physbase + (i << 12) + 1, piobase + 4); + } + + vga_misc_write(0x67); + + u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, + 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, + 0xff + }; + vga_cr_write(0x11, 0); + + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + + enable_port(mmio); + + intel_gmbus_read_edid(mmio, 3, 0x50, edid_data); + decode_edid(edid_data, + sizeof(edid_data), &edid); + + + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + u32 hactive = edid.x_resolution; + u32 vactive = edid.y_resolution; + u32 right_border = edid.hborder; + u32 bottom_border = edid.vborder; + int hpolarity = (edid.phsync == '-'); + int vpolarity = (edid.pvsync == '-'); + u32 vsync = edid.vspw; + u32 hsync = edid.hspw; + u32 vblank = edid.vbl; + u32 hblank = edid.hbl; + u32 hfront_porch = edid.hso; + u32 vfront_porch = edid.vso; + + u32 candp1, candn; + u32 best_delta = 0xffffffff; + + u32 target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + : (2 * edid.pixel_clock); + u32 pixel_p1 = 1; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; + +#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + vga_textmode_init(); +#else + vga_sr_write(1, 1); + vga_sr_write(0x2, 0xf); + vga_sr_write(0x3, 0x0); + vga_sr_write(0x4, 0xe); + vga_gr_write(0, 0x0); + vga_gr_write(1, 0x0); + vga_gr_write(2, 0x0); + vga_gr_write(3, 0x0); + vga_gr_write(4, 0x0); + vga_gr_write(5, 0x0); + vga_gr_write(6, 0x5); + vga_gr_write(7, 0xf); + vga_gr_write(0x10, 0x1); + vga_gr_write(0x11, 0); + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + + write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888); + write32(mmio + DSPADDR(0), 0); + write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(mmio + DSPSURF(0), 0); + for (i = 0; i < 0x100; i++) + write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); +#endif + + /* Find suitable divisors. */ + for (candp1 = 1; candp1 <= 8; candp1++) { + for (candn = 5; candn <= 10; candn++) { + u32 cur_frequency; + u32 m; /* 77 - 131. */ + u32 denom; /* 35 - 560. */ + u32 current_delta; + + denom = candn * candp1 * 7; + /* Doesnt overflow for up to + 5000000 kHz = 5 GHz. */ + m = (target_frequency * denom + 60000) / 120000; + + if (m < 77 || m > 131) + continue; + + cur_frequency = (120000 * m) / denom; + if (target_frequency > cur_frequency) + current_delta = target_frequency - cur_frequency; + else + current_delta = cur_frequency - target_frequency; + + + if (best_delta > current_delta) { + best_delta = current_delta; + pixel_n = candn; + pixel_p1 = candp1; + pixel_m2 = ((m + 3) % 5) + 7; + pixel_m1 = (m - pixel_m2) / 5; + } + } + } + + if (best_delta == 0xffffffff) { + printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return; + } + + u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 data_m1; + u32 data_n1 = 0x00800000; + u32 link_m1; + u32 link_n1 = 0x00080000; + + link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; + + data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) + / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 1)); + + printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", + hactive, vactive); + printk(BIOS_DEBUG, "Borders %d x %d\n", + right_border, bottom_border); + printk(BIOS_DEBUG, "Blank %d x %d\n", + hblank, vblank); + printk(BIOS_DEBUG, "Sync %d x %d\n", + hsync, vsync); + printk(BIOS_DEBUG, "Front porch %d x %d\n", + hfront_porch, vfront_porch); + printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + ? "Spread spectrum clock\n" : "DREF clock\n")); + printk(BIOS_DEBUG, + info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + printk(BIOS_DEBUG, "Polarities %d, %d\n", + hpolarity, vpolarity); + printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", + data_m1, data_n1); + printk(BIOS_DEBUG, "Link frequency %d kHz\n", + link_frequency); + printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", + link_m1, link_n1); + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", + 120000 * (5 * pixel_m1 + pixel_m2) / pixel_n + / (pixel_p1 * 7)); + + write32(mmio + PCH_LVDS, + (hpolarity << 20) | (vpolarity << 21) + | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_DETECTED); + write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); + write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock + ? 0x1002 : 0x400)); + mdelay(1); + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(mmio + _PCH_FP0(0), + ((pixel_n - 2) << 16) + | ((pixel_m1 - 2) << 8) | pixel_m2); + write32(mmio + _PCH_DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + + mdelay(1); + write32(mmio + 0xc7000, 0x8); + + mdelay(1); + write32(mmio + _PCH_DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + /* Re-lock the registers. */ + write32(mmio + PCH_PP_CONTROL, + (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + + write32(mmio + PCH_LVDS, + (hpolarity << 20) | (vpolarity << 21) + | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_DETECTED); + + write32(mmio + HTOTAL(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); + write32(mmio + HSYNC(0), + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); + + write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), + (vactive + bottom_border + vfront_porch + vsync - 1) + | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + 0xf0008, 0); + +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1)); + write32(mmio + PF_CTL(0),0); + write32(mmio + PF_WIN_SZ(0), 0); + write32(mmio + PF_WIN_POS(0), 0); +#else + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(mmio + PF_WIN_POS(0), 0); +#endif + + mdelay(1); + + write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); + write32(mmio + PIPE_DATA_N1(0), data_n1); + write32(mmio + PIPE_LINK_M1(0), link_m1); + write32(mmio + PIPE_LINK_N1(0), link_n1); + + link_train(mmio); +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(mmio+CPU_VGACNTRL,0x298e | VGA_DISP_DISABLE); +#else + write32(mmio+CPU_VGACNTRL,0x298e); +#endif + write32(mmio+0x60100,0x44300); + write32(mmio+0x60100,0x80044f00); + + mdelay(1); + read32(mmio + 0x000f0014); // = 0x00000600 + +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); + mdelay(1); +#endif + + write32(mmio + TRANS_HTOTAL(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + TRANS_HBLANK(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); + write32(mmio + TRANS_HSYNC(0), + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); + + write32(mmio + TRANS_VTOTAL(0), + ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); + write32(mmio + TRANS_VBLANK(0), + ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); + write32(mmio + TRANS_VSYNC(0), + (vactive + bottom_border + vfront_porch + vsync - 1) + | (vactive + bottom_border + vfront_porch - 1)); + + link_normal_operation(mmio); + + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + + mdelay(1); + + write32(mmio + PCH_TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + | TRANS_STATE_MASK +#endif + ); + write32(mmio + PCH_LVDS, + LVDS_PORT_ENABLE + | (hpolarity << 20) | (vpolarity << 21) + | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_DETECTED); + + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); + mdelay(1); + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS + | PANEL_POWER_ON | PANEL_POWER_RESET); + + printk (BIOS_DEBUG, "waiting for panel powerup\n"); + while (1) + { + u32 reg32; + reg32 = read32(mmio + PCH_PP_STATUS); + if (((reg32 >> 28) & 3) == 0) + break; + } + printk (BIOS_DEBUG, "panel powered up\n"); + + write32(mmio + PCH_PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + + /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); + +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4); + set_vbe_mode_info_valid(&edid, lfb); +#endif +} + +#endif

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coreboot-gerrit February 2014