coreboot-gerrit December 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 5c73b7a mainboard/storm: setup mmu in storm mainboard_init
by Marc Jones 31 Dec '14

31 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8010 -gerrit commit 5c73b7a237da910b238e60030aff9486ec615f72 Author: Deepa Dinamani <deepad(a)codeaurora.org> Date: Thu May 15 17:14:12 2014 -0700 mainboard/storm: setup mmu in storm mainboard_init enable protection of zero page access, provide for uncached device memory range, and protect against access outside of DRAM except to device registers. BUG=chrome-os-partner:28467 TEST=verified mmu.pagetable.list output: _______address___________|_physical________________|sec|_d_|_size____|_permissions____________________|_glb|_shr|_pageflags______________________| C:00000000--000FFFFF| | | | | | | | | C:00100000--3FFFFFFF| A:00:00100000--3FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:40000000--428FFFFF| A:00:40000000--428FFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | C:42900000--43CFFFFF| A:00:42900000--43CFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:43D00000--5FFFFFFF| A:00:43D00000--5FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | Original-Change-Id: If9beb10938841aead5105d662f0aef741995d708 Original-Signed-off-by: Deepa Dinamani <deepad(a)codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/200341 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb(a)chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> (cherry picked from commit 09dd137453d8c6f1b60692b01226498e22f34fb2) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Conflicts: src/mainboard/google/storm/mainboard.c Change-Id: Idff7e3f0bc5903933e9f1b980f595666380696d1 --- src/mainboard/google/storm/mainboard.c | 38 ++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 0b0182f..1e622f4 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. + * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,11 +17,45 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <device/device.h> +#include <arch/cache.h> #include <boot/coreboot_tables.h> +#include <device/device.h> + +#define TO_MB(x) ((x)>>20) + +/* convenient shorthand (in MB) */ +#define DRAM_START TO_MB(CONFIG_SYS_SDRAM_BASE) +#define DRAM_SIZE (CONFIG_DRAM_SIZE_MB) +#define DRAM_END (DRAM_START + DRAM_SIZE) + +/* DMA memory for drivers */ +#define DMA_START TO_MB(CONFIG_DRAM_DMA_START) +#define DMA_SIZE TO_MB(CONFIG_DRAM_DMA_SIZE) + +static void setup_mmu(void) +{ + dcache_mmu_disable(); + + /* Map Device memory. */ + mmu_config_range(0, DRAM_START, DCACHE_OFF); + /* Disable Page 0 for trapping NULL pointer references. */ + mmu_disable_range(0, 1); + /* Map DRAM memory */ + mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); + /* Map DMA memory */ + if (DMA_SIZE) + mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); + + mmu_disable_range(DRAM_END, 4096 - DRAM_END); + + mmu_init(); + + dcache_mmu_enable(); +} static void mainboard_init(device_t dev) { + setup_mmu(); } static void mainboard_enable(device_t dev)

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Patch set updated for coreboot: 5572258 ipq806x: clean up UART driver tx_byte function
by Marc Jones 31 Dec '14

31 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8011 -gerrit commit 55722584a90e75f92b4c8244e253fe7712edff3c Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue May 27 18:03:38 2014 -0700 ipq806x: clean up UART driver tx_byte function The driver as it was copied from u-boot provided a function to transmit multiple characters in one invocation. This feature was not ported to coreboot, there is no need to maintain the complexity when only one character at a time is transmitted. It is also very desirable to get rid of a 1024 byte array allocated on the stack. The array was necessary to allow to convert multiple newline characters in the transmit data flow into two character sequences CRLF. Now just a single word is enough to keep one or two characters to transmit. BUG=chrome-os-partner:27784 TEST=verified that coreboot with the new code prints generates console output. Original-Change-Id: I73869c5f4ca87210b34811b583386554bafff1e7 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201782 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Reviewed-by: Trevor Bourget <tbourget(a)codeaurora.org> (cherry picked from commit eab3dc9d30c7e8355a2563e18ada78e4070e6151) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I4274b8f7188bf9636906b39bcd9ec7adf0e1222e --- src/soc/qualcomm/ipq806x/include/ipq_uart.h | 9 --- src/soc/qualcomm/ipq806x/uart.c | 121 +++++----------------------- 2 files changed, 18 insertions(+), 112 deletions(-) diff --git a/src/soc/qualcomm/ipq806x/include/ipq_uart.h b/src/soc/qualcomm/ipq806x/include/ipq_uart.h index da943b9..90ca704 100644 --- a/src/soc/qualcomm/ipq806x/include/ipq_uart.h +++ b/src/soc/qualcomm/ipq806x/include/ipq_uart.h @@ -38,15 +38,6 @@ ((value << (32 - end_pos))\ >> (32 - (end_pos - start_pos))) - -#define PACK_CHARS_INTO_WORDS(a, cnt, word) { \ - word = 0; \ - int j; \ - for(j=0; j < (int)cnt; j++) { \ - word |= (a[j] & 0xff)<< (j * 8);\ - } \ - } - extern void __udelay(unsigned long usec); diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index f7b5d02..e09bd0f 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -192,108 +192,32 @@ msm_boot_uart_dm_read(unsigned int *data, int *count, int wait) } #endif -/** - * msm_boot_uart_replace_lr_with_cr - replaces "\n" with "\r\n" - * @data_in: characters to be converted - * @num_of_chars: no. of characters - * @data_out: location where converted chars are stored - * - * Replace linefeed char "\n" with carriage return + linefeed - * "\r\n". Currently keeping it simple than efficient. - */ -static unsigned int -msm_boot_uart_replace_lr_with_cr(unsigned char *data_in, - int num_of_chars, - char *data_out, int *num_of_chars_out) +void uart_tx_byte(int idx, unsigned char data) { - int i = 0, j = 0; - - if ((data_in == NULL) || (data_out == NULL) || (num_of_chars < 0)) - return MSM_BOOT_UART_DM_E_INVAL; - - for (i = 0, j = 0; i < num_of_chars; i++, j++) { - if (data_in[i] == '\n') - data_out[j++] = '\r'; - - data_out[j] = data_in[i]; - } - - *num_of_chars_out = j; - - return MSM_BOOT_UART_DM_E_SUCCESS; -} - -/** - * msm_boot_uart_dm_write - transmit data - * @data: data to transmit - * @num_of_chars: no. of bytes to transmit - * - * Writes the data to the TX FIFO. If no space is available blocks - * till space becomes available. - */ -static unsigned int -msm_boot_uart_dm_write(unsigned char *data, unsigned int num_of_chars) -{ - unsigned int tx_word_count = 0; - unsigned int tx_char_left = 0, tx_char = 0; - unsigned int tx_word = 0; - int i = 0; - char *tx_data = NULL; - char new_data[1024]; + int num_of_chars = 1; + unsigned tx_data = 0; unsigned int base = uart_board_param.uart_dm_base; - if ((data == NULL) || (num_of_chars <= 0)) - return MSM_BOOT_UART_DM_E_INVAL; - - /* Replace line-feed (/n) with carriage-return + line-feed (/r/n) */ - msm_boot_uart_replace_lr_with_cr(data, num_of_chars, new_data, &i); - - tx_data = new_data; - num_of_chars = i; - - /* Write to NO_CHARS_FOR_TX register number of characters - * to be transmitted. However, before writing TX_FIFO must - * be empty as indicated by TX_READY interrupt in IMR register - */ - /* Check if transmit FIFO is empty. - * If not we'll wait for TX_READY interrupt. */ - - if (!(readl_i(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXEMT)) { - while (!(readl_i(MSM_BOOT_UART_DM_ISR(base)) & - MSM_BOOT_UART_DM_TX_READY)) - udelay(1); + /* Add CR to every LF. */ + if (data == '\n') { + num_of_chars++; + tx_data = '\r' | ('\n' << 8); + } else { + tx_data = data; } - /* We are here. FIFO is ready to be written. */ - /* Write number of characters to be written */ - writel_i(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base)); - - /* Clear TX_READY interrupt */ - writel_i(MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT, - MSM_BOOT_UART_DM_CR(base)); - - /* We use four-character word FIFO. So we need to divide data into - * four characters and write in UART_DM_TF register */ - tx_word_count = (num_of_chars % 4) ? ((num_of_chars / 4) + 1) : - (num_of_chars / 4); - tx_char_left = num_of_chars; - - for (i = 0; i < (int)tx_word_count; i++) { - tx_char = (tx_char_left < 4) ? tx_char_left : 4; - PACK_CHARS_INTO_WORDS(tx_data, tx_char, tx_word); - - /* Wait till TX FIFO has space */ + /* Wait until transmit FIFO is empty. */ while (!(readl_i(MSM_BOOT_UART_DM_SR(base)) & - MSM_BOOT_UART_DM_SR_TXRDY)) + MSM_BOOT_UART_DM_SR_TXEMT)) udelay(1); + /* + * TX FIFO is ready to accept new character(s). First write number of + * characters to be transmitted. + */ + writel_i(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base)); - /* TX FIFO has space. Write the chars */ - writel_i(tx_word, MSM_BOOT_UART_DM_TF(base, 0)); - tx_char_left = num_of_chars - (i + 1) * 4; - tx_data = tx_data + 4; - } - - return MSM_BOOT_UART_DM_E_SUCCESS; + /* And now write the character(s) */ + writel_i(tx_data, MSM_BOOT_UART_DM_TF(base, 0)); } /* @@ -419,15 +343,6 @@ uint32_t uartmem_getbaseaddr(void) #endif /** - * uart_tx_byte - transmits a character - * @c: character to transmit - */ -void uart_tx_byte(int idx, unsigned char c) -{ - msm_boot_uart_dm_write(&c, 1); -} - -/** * uart_tx_flush - transmits a string of data * @s: string to transmit */

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Patch set updated for coreboot: 3d0bc98 libpayload: Do not tolerate compilation warnings when building
by Marc Jones 31 Dec '14

31 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7911 -gerrit commit 3d0bc98be804f581d867b0357d2dee368e991c37 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu May 15 14:12:54 2014 -0700 libpayload: Do not tolerate compilation warnings when building Make sure the build breaks in case of warnings. BUG=none TEST= All builds succeed with the restored patch and fail when a compilation warning is thrown. Original-Change-Id: I9bdcd8938f59913e4ba86df5e4921b3f821ef920 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/200110 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 16dde875950d6806cc770cdbee4d3ff456ed6f02) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I86988f8d3f1acaa6ceeabdcbfa3cede1e67c28fe --- payloads/libpayload/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index ffe8371..dd83f88 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -57,7 +57,7 @@ CFLAGS = $(EXTRA_CFLAGS) $(INCLUDES) -Os -pipe -nostdinc -ggdb3 CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -CFLAGS += -Wstrict-aliasing -Wshadow +CFLAGS += -Wstrict-aliasing -Wshadow -Werror $(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER) cmp $@ $< 2>/dev/null || cp $< $@

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Patch merged into coreboot/master: 79a591f libpayload: Fix pointer related casts
by gerrit＠coreboot.org 31 Dec '14

31 Dec '14

the following patch was just integrated into master: commit 79a591fb3879a663208e5e3fb29886e0fe735f7e Author: Furquan Shaikh <furquan(a)google.com> Date: Tue May 13 13:47:32 2014 -0700 libpayload: Fix pointer related casts Fix pointer related casts since this can create a problem for 64-bit systems. BUG=None BRANCH=None TEST=Compiled successfully for link, nyan using emerge-* libpayload Original-Change-Id: I4cbd2d9f1efaaac87c3eba69204337fd6893ed66 Original-Reviewed-on: https://chromium-review.googlesource.com/199564 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 914b118a64b0691aeca463dff24252db9c24109e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I11f070ed5d3eddd8b9be30c428cb24c8439e617b Reviewed-on: http://review.coreboot.org/7905 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7905 for details. -gerrit

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New patch to review for coreboot: 4c58169 northbridge/amd/agesa/family1{4, 5}: Remove cruff from dimmSpd.c
by Edward O'Callaghan 31 Dec '14

31 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8017 -gerrit commit 4c581692819249d030bdd5f009f5dceb46603fd1 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jan 1 04:09:04 2015 +1100 northbridge/amd/agesa/family1{4,5}: Remove cruff from dimmSpd.c Remove useless comment pretaining to abusing pragma's for old GCC/GDB interaction issues. Change-Id: Ic83a0285ac947a23699a81a82b89de08a47ab052 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/agesa/family14/dimmSpd.c | 3 --- src/northbridge/amd/agesa/family15/dimmSpd.c | 3 --- 2 files changed, 6 deletions(-) diff --git a/src/northbridge/amd/agesa/family14/dimmSpd.c b/src/northbridge/amd/agesa/family14/dimmSpd.c index 6ca2ce1..bee2c7e 100644 --- a/src/northbridge/amd/agesa/family14/dimmSpd.c +++ b/src/northbridge/amd/agesa/family14/dimmSpd.c @@ -30,9 +30,6 @@ #include <northbridge/amd/agesa/dimmSpd.h> -/* uncomment for source level debug - GDB gets really confused otherwise. */ -//#pragma optimize ("", off) - /** * Gets the SMBus address for an SPD from the array in devicetree.cb * then read the SPD into the supplied buffer. diff --git a/src/northbridge/amd/agesa/family15/dimmSpd.c b/src/northbridge/amd/agesa/family15/dimmSpd.c index bf8e59e..201f293 100644 --- a/src/northbridge/amd/agesa/family15/dimmSpd.c +++ b/src/northbridge/amd/agesa/family15/dimmSpd.c @@ -30,9 +30,6 @@ #include <northbridge/amd/agesa/dimmSpd.h> -/* uncomment for source level debug - GDB gets really confused otherwise. */ -//#pragma optimize ("", off) - /** * Gets the SMBus address for an SPD from the array in devicetree.cb * then read the SPD into the supplied buffer.

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New patch to review for coreboot: 50659e1 amd/agesa/family12/dimmSpd.c: Indent (tab) fix
by Edward O'Callaghan 31 Dec '14

31 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8016 -gerrit commit 50659e15dce8455970be4c74bcff0f824019b104 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jan 1 04:02:55 2015 +1100 amd/agesa/family12/dimmSpd.c: Indent (tab) fix Trivial, Use tab over space for indent. Clean up some ASCII art while here. Change-Id: Id2478d140a98596c5eeefdf5b047c1ca23203909 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/agesa/family12/dimmSpd.c | 44 +++++++++++++++------------- 1 file changed, 23 insertions(+), 21 deletions(-) diff --git a/src/northbridge/amd/agesa/family12/dimmSpd.c b/src/northbridge/amd/agesa/family12/dimmSpd.c index e8ef02a..3fbc6df 100644 --- a/src/northbridge/amd/agesa/family12/dimmSpd.c +++ b/src/northbridge/amd/agesa/family12/dimmSpd.c @@ -1,4 +1,4 @@ -/***************************************************************************** +/* * * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. @@ -25,7 +25,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ***************************************************************************/ + */ #include <stdlib.h> #include "Porting.h" @@ -34,20 +34,21 @@ #include <northbridge/amd/agesa/dimmSpd.h> -typedef struct _DIMM_INFO_SMBUS{ - UINT8 SocketId; - UINT8 MemChannelId; - UINT8 DimmId; - UINT8 SmbusAddress; +typedef struct _DIMM_INFO_SMBUS { + UINT8 SocketId; + UINT8 MemChannelId; + UINT8 DimmId; + UINT8 SmbusAddress; } DIMM_INFO_SMBUS; + /* * SPD address table - porting required */ STATIC CONST DIMM_INFO_SMBUS SpdAddrLookup [] = { - /* Socket, Channel, Dimm, Smbus */ - {0, 0, 0, 0xA0}, - {0, 1, 0, 0xA2} + /* Socket, Channel, Dimm, Smbus */ + {0, 0, 0, 0xA0}, + {0, 1, 0, 0xA2} }; AGESA_STATUS @@ -57,17 +58,18 @@ AmdMemoryReadSPD ( IN OUT AGESA_READ_SPD_PARAMS *SpdData ) { - UINT8 SmBusAddress = 0; - UINTN Index; - UINTN MaxSocket = ARRAY_SIZE(SpdAddrLookup); - for (Index = 0; Index < MaxSocket; Index ++){ - if ((SpdData->SocketId == SpdAddrLookup[Index].SocketId) && - (SpdData->MemChannelId == SpdAddrLookup[Index].MemChannelId) && - (SpdData->DimmId == SpdAddrLookup[Index].DimmId)) { - SmBusAddress = SpdAddrLookup[Index].SmbusAddress; - break; - } - } + UINT8 SmBusAddress = 0; + UINTN Index; + UINTN MaxSocket = ARRAY_SIZE(SpdAddrLookup); + + for (Index = 0; Index < MaxSocket; Index ++) { + if ((SpdData->SocketId == SpdAddrLookup[Index].SocketId) && + (SpdData->MemChannelId == SpdAddrLookup[Index].MemChannelId) && + (SpdData->DimmId == SpdAddrLookup[Index].DimmId)) { + SmBusAddress = SpdAddrLookup[Index].SmbusAddress; + break; + } + } if (SmBusAddress == 0) return AGESA_ERROR;

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New patch to review for coreboot: 051fe3d amd/agesa/family12/northbridge.c: Indent (tab) fix
by Edward O'Callaghan 31 Dec '14

31 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8015 -gerrit commit 051fe3de721ebd8857dbbd014de8479866edd883 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jan 1 03:49:47 2015 +1100 amd/agesa/family12/northbridge.c: Indent (tab) fix Trivial, Use tab over space for indent. Change-Id: Iba0e006197a020157b11746dd4999d87a8ca8d97 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/agesa/family12/northbridge.c | 189 +++++++++++------------ 1 file changed, 92 insertions(+), 97 deletions(-) diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index fe9cd72..6301852 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -58,71 +58,66 @@ static device_t get_node_pci(u32 nodeid, u32 fn) static void get_fx_devs(void) { - int i; - for(i = 0; i < FX_DEVS; i++) { - __f0_dev[i] = get_node_pci(i, 0); - __f1_dev[i] = get_node_pci(i, 1); - __f2_dev[i] = get_node_pci(i, 2); - __f4_dev[i] = get_node_pci(i, 4); - if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) - fx_devs = i+1; - } - if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { - die("Cannot find 0:0x18.[0|1]\n"); - } -} + int i; + for(i = 0; i < FX_DEVS; i++) { + __f0_dev[i] = get_node_pci(i, 0); + __f1_dev[i] = get_node_pci(i, 1); + __f2_dev[i] = get_node_pci(i, 2); + __f4_dev[i] = get_node_pci(i, 4); + if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) + fx_devs = i+1; + } + if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) + die("Cannot find 0:0x18.[0|1]\n"); +} static u32 f1_read_config32(unsigned reg) { - if (fx_devs == 0) - get_fx_devs(); - return pci_read_config32(__f1_dev[0], reg); -} + if (fx_devs == 0) + get_fx_devs(); + return pci_read_config32(__f1_dev[0], reg); +} static void f1_write_config32(unsigned reg, u32 value) { - int i; - if (fx_devs == 0) - get_fx_devs(); - for(i = 0; i < fx_devs; i++) { - device_t dev; - dev = __f1_dev[i]; - if (dev && dev->enabled) { - pci_write_config32(dev, reg, value); - } - } + int i; + if (fx_devs == 0) + get_fx_devs(); + for(i = 0; i < fx_devs; i++) { + device_t dev = __f1_dev[i]; + if (dev && dev->enabled) { + pci_write_config32(dev, reg, value); + } + } } - static u32 amdfam12_nodeid(device_t dev) { - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s\n",__func__); - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s\n",__func__); + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; } - #include "amdfam12_conf.c" - static void northbridge_init(device_t dev) { - printk(BIOS_DEBUG, "Northbridge init\n"); + printk(BIOS_DEBUG, "Northbridge init\n"); } static void set_vga_enable_reg(u32 nodeid, u32 linkn) { - u32 val; + u32 val; - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - val = 1 | (nodeid<<4) | (linkn<<12); - /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb, - 0x3c0:0x3df */ - f1_write_config32(0xf4, val); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); + val = 1 | (nodeid<<4) | (linkn<<12); + /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb, + 0x3c0:0x3df */ + f1_write_config32(0xf4, val); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } @@ -768,35 +763,35 @@ static void domain_enable_resources(device_t dev) static void cpu_bus_read_resources(device_t dev) { - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); #if CONFIG_MMCONF_SUPPORT - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + struct resource *resource = new_resource(dev, 0xc0010058); + resource->base = CONFIG_MMCONF_BASE_ADDRESS; + resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; #endif - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } static void cpu_bus_set_resources(device_t dev) { - struct resource *resource = find_resource(dev, 0xc0010058); + struct resource *resource = find_resource(dev, 0xc0010058); - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - if (resource) { - report_resource_stored(dev, resource, " <mmconfig>"); - } - pci_dev_set_resources(dev); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); + if (resource) { + report_resource_stored(dev, resource, " <mmconfig>"); + } + pci_dev_set_resources(dev); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } static void cpu_bus_init(device_t dev) { - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - initialize_cpus(dev->link_list); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); + initialize_cpus(dev->link_list); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } @@ -911,27 +906,27 @@ static unsigned long agesa_write_acpi_tables(unsigned long current, static struct device_operations northbridge_operations = { - .read_resources = read_resources, - .set_resources = set_resources, - .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, - .write_acpi_tables = agesa_write_acpi_tables, - .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .enable = 0, - .ops_pci = 0, + .read_resources = read_resources, + .set_resources = set_resources, + .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, + .write_acpi_tables = agesa_write_acpi_tables, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .enable = 0, + .ops_pci = 0, }; static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &northbridge_operations, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1705, + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x1705, }; struct chip_operations northbridge_amd_agesa_family12_ops = { - CHIP_NAME("AMD Family 12h Northbridge") - .enable_dev = 0, + CHIP_NAME("AMD Family 12h Northbridge") + .enable_dev = 0, }; @@ -939,48 +934,48 @@ struct chip_operations northbridge_amd_agesa_family12_ops = { static struct device_operations pci_domain_ops = { - .read_resources = domain_read_resources, - .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, - .init = NULL, - .scan_bus = pci_domain_scan_bus, +.read_resources = domain_read_resources, +.set_resources = domain_set_resources, +.enable_resources = domain_enable_resources, +.init = NULL, +.scan_bus = pci_domain_scan_bus, }; static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, - .set_resources = cpu_bus_set_resources, - .enable_resources = NULL, - .init = cpu_bus_init, - .scan_bus = 0, +.read_resources = cpu_bus_read_resources, +.set_resources = cpu_bus_set_resources, +.enable_resources = NULL, +.init = cpu_bus_init, +.scan_bus = 0, }; static void root_complex_enable_dev(struct device *dev) { - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - static int done = 0; + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); + static int done = 0; /* Do not delay UMA setup, as a device on the PCI bus may evaluate the global uma_memory variables already in its enable function. */ - if (!done) { - setup_bsp_ramtop(); - setup_uma_memory(); - done = 1; - } + if (!done) { + setup_bsp_ramtop(); + setup_uma_memory(); + done = 1; + } - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } struct chip_operations northbridge_amd_agesa_family12_root_complex_ops = { - CHIP_NAME("AMD Family 12h Root Complex") - .enable_dev = root_complex_enable_dev, + CHIP_NAME("AMD Family 12h Root Complex") + .enable_dev = root_complex_enable_dev, };

1 0

Patch set updated for coreboot: e574f12 i82801gx: remove wrong code from pci bridge init
by Mono Moosbart 31 Dec '14

31 Dec '14

Mono Moosbart (mono(a)posteo.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7990 -gerrit commit e574f12bfe12d109e140e8d6ae86c3d76a4bc500 Author: Axel Holewa <mono(a)posteo.de> Date: Wed Dec 31 01:52:27 2014 +0100 i82801gx: remove wrong code from pci bridge init This code uses missleading register name PCI_MIN_GNT defined in pci_def.h with 0x3e. However this device has no register with this name. Moreover, this device's register at offset 0x3e has the name BCTRL defined in i82801gx.h. Right above this removed code, in line 41-44, bits 0 and 1 at offset 0x3e (BCTRL) are cleared disabling Parity Error Response and SERR#. The removed code then enables SERR# and ISA. Tested with printk and lspci. Other southbridges maybe use the same wrong code (lynxpoint, bd82x6x). Change-Id: I61270441a56067e4255c75d39428258dc39ffaef Signed-off-by: Axel Holewa <mono(a)posteo.de> --- src/southbridge/intel/i82801gx/pci.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index 0f372e7..90d9107 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -49,9 +49,6 @@ static void pci_init(struct device *dev) reg8 |= (0x04 << 3); pci_write_config8(dev, SMLT, reg8); - /* Will this improve throughput of bus masters? */ - pci_write_config8(dev, PCI_MIN_GNT, 0x06); - /* Clear errors in status registers */ reg16 = pci_read_config16(dev, PSTS); //reg16 |= 0xf900;

1 0

Patch set updated for coreboot: c0bf642 soc: Use 'pci_devfn' where appropriate
by Edward O'Callaghan 31 Dec '14

31 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8014 -gerrit commit c0bf6425926b85c5ec783ed58618cdfa12d8ee3e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Dec 31 20:55:07 2014 +1100 soc: Use 'pci_devfn' where appropriate Change-Id: Ief2dd10b71623c48b92949e64f60c7e7f7189144 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/soc/intel/baytrail/pmutil.c | 4 ++-- src/soc/intel/baytrail/smihandler.c | 2 +- src/soc/intel/baytrail/spi.c | 2 +- src/soc/intel/fsp_baytrail/pmutil.c | 4 ++-- src/soc/intel/fsp_baytrail/smihandler.c | 2 +- src/soc/intel/fsp_baytrail/spi.c | 2 +- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index 6a62a34..935253c 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -28,9 +28,9 @@ #if defined(__SMM__) -static const device_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); +static const pci_devfn_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); -static inline device_t get_pcu_dev(void) +static inline pci_devfn_t get_pcu_dev(void) { return pcu_dev; } diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index a2718e2..66e075c 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -71,7 +71,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index ad33eb9..bcc50c8 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -289,7 +289,7 @@ static ich9_spi_regs *spi_regs(void) /* N.B. dev is stage dependent typed */ #ifdef __SMM__ - device_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); #else struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); #endif diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c index 6a62a34..90a17a7 100644 --- a/src/soc/intel/fsp_baytrail/pmutil.c +++ b/src/soc/intel/fsp_baytrail/pmutil.c @@ -28,9 +28,9 @@ #if defined(__SMM__) -static const device_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); +static const pci_devfn pcu_dev = PCI_DEV(0, PCU_DEV, 0); -static inline device_t get_pcu_dev(void) +static inline pci_devfn get_pcu_dev(void) { return pcu_dev; } diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c index d78288c..694fcf8 100644 --- a/src/soc/intel/fsp_baytrail/smihandler.c +++ b/src/soc/intel/fsp_baytrail/smihandler.c @@ -71,7 +71,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index ea4b30f..8c456da 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -286,7 +286,7 @@ static ich9_spi_regs *spi_regs(void) /* N.B. dev is type-dependent on stage */ #ifdef __SMM__ - device_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); #else struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); #endif

1 0

Patch set updated for coreboot: 9b4ccc4 soc: Don't hide pointers behind typedefs
by Edward O'Callaghan 31 Dec '14

31 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7277 -gerrit commit 9b4ccc4b33f249c8ec022b3e2a69fc7c311d492e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Oct 28 23:00:45 2014 +1100 soc: Don't hide pointers behind typedefs Change-Id: I05bb3b09cd1059cf43905a310f5c1ba04ed32336 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/soc/intel/baytrail/baytrail/ramstage.h | 6 ++--- src/soc/intel/baytrail/chip.c | 6 ++--- src/soc/intel/baytrail/cpu.c | 4 ++-- src/soc/intel/baytrail/ehci.c | 4 ++-- src/soc/intel/baytrail/emmc.c | 2 +- src/soc/intel/baytrail/gfx.c | 16 ++++++------- src/soc/intel/baytrail/hda.c | 2 +- src/soc/intel/baytrail/lpe.c | 12 +++++----- src/soc/intel/baytrail/lpss.c | 10 ++++---- src/soc/intel/baytrail/northcluster.c | 2 +- src/soc/intel/baytrail/pcie.c | 14 +++++------ src/soc/intel/baytrail/pmutil.c | 4 ++-- src/soc/intel/baytrail/ramstage.c | 2 +- src/soc/intel/baytrail/sata.c | 2 +- src/soc/intel/baytrail/scc.c | 2 +- src/soc/intel/baytrail/sd.c | 2 +- src/soc/intel/baytrail/southcluster.c | 24 +++++++++---------- src/soc/intel/baytrail/spi.c | 6 ++--- src/soc/intel/baytrail/xhci.c | 6 ++--- src/soc/intel/broadwell/acpi.c | 2 +- src/soc/intel/broadwell/broadwell/me.h | 2 +- src/soc/intel/broadwell/broadwell/pch.h | 2 +- src/soc/intel/broadwell/broadwell/ramstage.h | 4 ++-- src/soc/intel/broadwell/broadwell/xhci.h | 2 +- src/soc/intel/broadwell/chip.c | 6 ++--- src/soc/intel/broadwell/cpu.c | 6 ++--- src/soc/intel/broadwell/ehci.c | 2 +- src/soc/intel/broadwell/lpc.c | 18 +++++++-------- src/soc/intel/broadwell/me.c | 24 +++++++++---------- src/soc/intel/broadwell/pch.c | 6 ++--- src/soc/intel/broadwell/pcie.c | 32 +++++++++++++------------- src/soc/intel/broadwell/romstage/uart.c | 2 +- src/soc/intel/broadwell/sata.c | 2 +- src/soc/intel/broadwell/smbus.c | 8 +++---- src/soc/intel/broadwell/smihandler.c | 2 +- src/soc/intel/broadwell/smmrelocate.c | 6 ++--- src/soc/intel/broadwell/spi.c | 2 +- src/soc/intel/broadwell/systemagent.c | 22 +++++++++--------- src/soc/intel/broadwell/xhci.c | 8 +++---- src/soc/intel/fsp_baytrail/baytrail/baytrail.h | 2 +- src/soc/intel/fsp_baytrail/baytrail/ramstage.h | 6 ++--- src/soc/intel/fsp_baytrail/chip.c | 8 +++---- src/soc/intel/fsp_baytrail/cpu.c | 4 ++-- src/soc/intel/fsp_baytrail/northcluster.c | 8 +++---- src/soc/intel/fsp_baytrail/pmutil.c | 4 ++-- src/soc/intel/fsp_baytrail/ramstage.c | 2 +- src/soc/intel/fsp_baytrail/southcluster.c | 26 ++++++++++----------- src/soc/intel/fsp_baytrail/spi.c | 6 ++--- src/soc/nvidia/tegra/dc.h | 2 +- src/soc/nvidia/tegra124/display.c | 2 +- src/soc/nvidia/tegra124/soc.c | 6 ++--- src/soc/samsung/exynos5250/cpu.c | 8 +++---- src/soc/samsung/exynos5420/cpu.c | 8 +++---- 53 files changed, 188 insertions(+), 188 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h index a8b5fdc..4a7b536 100644 --- a/src/soc/intel/baytrail/baytrail/ramstage.h +++ b/src/soc/intel/baytrail/baytrail/ramstage.h @@ -26,16 +26,16 @@ /* The baytrail_init_pre_device() function is called prior to device * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config); -void baytrail_init_cpus(device_t dev); +void baytrail_init_cpus(struct device *dev); void set_max_freq(void); -void southcluster_enable_dev(device_t dev); +void southcluster_enable_dev(struct device *dev); #if CONFIG_HAVE_REFCODE_BLOB void baytrail_run_reference_code(void); #else static inline void baytrail_run_reference_code(void) {} #endif void baytrail_init_scc(void); -void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); +void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index 7a5b9c2..a29bef2 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -26,7 +26,7 @@ #include <baytrail/ramstage.h> #include "chip.h" -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -49,7 +49,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { @@ -77,7 +77,7 @@ struct chip_operations soc_intel_baytrail_ops = { .init = soc_init, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index e8f95ae..a5106dd 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -78,7 +78,7 @@ const struct reg_script core_msr_script[] = { REG_SCRIPT_END }; -void baytrail_init_cpus(device_t dev) +void baytrail_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; const struct pattrs *pattrs = pattrs_get(); @@ -121,7 +121,7 @@ void baytrail_init_cpus(device_t dev) restore_default_smm_area(default_smm_area); } -static void baytrail_core_init(device_t cpu) +static void baytrail_core_init(struct device *cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c index 5d1a4d8..accfed2 100644 --- a/src/soc/intel/baytrail/ehci.c +++ b/src/soc/intel/baytrail/ehci.c @@ -91,7 +91,7 @@ static const struct reg_script ehci_hc_reset[] = { REG_SCRIPT_END }; -static void usb2_phy_init(device_t dev) +static void usb2_phy_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script usb2_phy_script[] = { @@ -123,7 +123,7 @@ static void usb2_phy_init(device_t dev) reg_script_run(usb2_phy_script); } -static void ehci_init(device_t dev) +static void ehci_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script ehci_hc_init[] = { diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index f88614b..74bdb4b 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -49,7 +49,7 @@ static const struct reg_script emmc_ops[] = { REG_SCRIPT_END, }; -static void emmc_init(device_t dev) +static void emmc_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 4cce877..eacfc62 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -39,7 +39,7 @@ * Lock Power Context Base Register to point to a 24KB block * of memory in GSM. Power context save data is stored here. */ -static void gfx_lock_pcbase(device_t dev) +static void gfx_lock_pcbase(struct device *dev) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256, @@ -264,18 +264,18 @@ static const struct reg_script gfx_post_vbios_script[] = { REG_SCRIPT_END }; -static inline void gfx_run_script(device_t dev, const struct reg_script *ops) +static inline void gfx_run_script(struct device *dev, const struct reg_script *ops) { reg_script_run_on_dev(dev, ops); } -static void gfx_pre_vbios_init(device_t dev) +static void gfx_pre_vbios_init(struct device *dev) { printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); gfx_run_script(dev, gpu_pre_vbios_script); } -static void gfx_pm_init(device_t dev) +static void gfx_pm_init(struct device *dev) { printk(BIOS_INFO, "GFX: Power Management Init\n"); gfx_run_script(dev, gfx_init_script); @@ -284,13 +284,13 @@ static void gfx_pm_init(device_t dev) gfx_lock_pcbase(dev); } -static void gfx_post_vbios_init(device_t dev) +static void gfx_post_vbios_init(struct device *dev) { printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); gfx_run_script(dev, gfx_post_vbios_script); } -static void set_backlight_pwm(device_t dev, uint32_t bklt_reg, int req_hz) +static void set_backlight_pwm(struct device *dev, uint32_t bklt_reg, int req_hz) { int divider; struct resource *res; @@ -311,7 +311,7 @@ static void set_backlight_pwm(device_t dev, uint32_t bklt_reg, int req_hz) write32(res->base + bklt_reg, divider << 16); } -static void gfx_panel_setup(device_t dev) +static void gfx_panel_setup(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script gfx_pipea_init[] = { @@ -366,7 +366,7 @@ static void gfx_panel_setup(device_t dev) } } -static void gfx_init(device_t dev) +static void gfx_init(struct device *dev) { /* Pre VBIOS Init */ gfx_pre_vbios_init(dev); diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c index c5de654..5733b95 100644 --- a/src/soc/intel/baytrail/hda.c +++ b/src/soc/intel/baytrail/hda.c @@ -78,7 +78,7 @@ static const uint32_t hdmi_codec_verb_table[] = { 0x20671f58, }; -static void hda_init(device_t dev) +static void hda_init(struct device *dev) { struct resource *res; int codec_mask; diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index 581f42b..b6fb7c2 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -45,7 +45,7 @@ #define FIRMWARE_REG_BASE_C0 0x144000 #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4) -static void assign_device_nvs(device_t dev, u32 *field, unsigned index) +static void assign_device_nvs(struct device *dev, u32 *field, unsigned index) { struct resource *res; @@ -54,7 +54,7 @@ static void assign_device_nvs(device_t dev, u32 *field, unsigned index) *field = res->base; } -static void lpe_enable_acpi_mode(device_t dev) +static void lpe_enable_acpi_mode(struct device *dev) { static const struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ @@ -87,7 +87,7 @@ static void lpe_enable_acpi_mode(device_t dev) reg_script_run_on_dev(dev, ops); } -static void setup_codec_clock(device_t dev) +static void setup_codec_clock(struct device *dev) { uint32_t reg; int clk_reg; @@ -125,7 +125,7 @@ static void setup_codec_clock(device_t dev) write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); } -static void lpe_stash_firmware_info(device_t dev) +static void lpe_stash_firmware_info(struct device *dev) { struct resource *res; struct resource *mmio; @@ -149,7 +149,7 @@ static void lpe_stash_firmware_info(device_t dev) } } -static void lpe_init(device_t dev) +static void lpe_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -161,7 +161,7 @@ static void lpe_init(device_t dev) lpe_enable_acpi_mode(dev); } -static void lpe_read_resources(device_t dev) +static void lpe_read_resources(struct device *dev) { pci_dev_read_resources(dev); diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index 3ee648a..c548370 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -33,7 +33,7 @@ #include "chip.h" -static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) +static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ @@ -70,7 +70,7 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) reg_script_run_on_dev(dev, ops); } -static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) +static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg) { struct reg_script ops[] = { REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg, @@ -82,7 +82,7 @@ static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) reg_script_run_on_dev(dev, ops); } -static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) +static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) { *iosf_reg = -1; *nvs_index = -1; @@ -123,7 +123,7 @@ static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) } } -static void i2c_disable_resets(device_t dev) +static void i2c_disable_resets(struct device *dev) { /* Release the I2C devices from reset. */ static const struct reg_script ops[] = { @@ -150,7 +150,7 @@ static void i2c_disable_resets(device_t dev) } } -static void lpss_init(device_t dev) +static void lpss_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; int iosf_reg, nvs_index; diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index 8ff9712..b648923 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -71,7 +71,7 @@ uint32_t nc_read_top_of_low_memory(void) return iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1); } -static void nc_read_resources(device_t dev) +static void nc_read_resources(struct device *dev) { unsigned long mmconf; unsigned long bmbound; diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 71b90de..0db9d0f 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -34,12 +34,12 @@ static int pll_en_off; static uint32_t strpfusecfg; -static inline int root_port_offset(device_t dev) +static inline int root_port_offset(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn); } -static inline int is_first_port(device_t dev) +static inline int is_first_port(struct device *dev) { return root_port_offset(dev) == PCIE_PORT1_FUNC; } @@ -88,7 +88,7 @@ static const struct reg_script init_static_after_exit_latency[] = { REG_SCRIPT_END, }; -static void byt_pcie_init(device_t dev) +static void byt_pcie_init(struct device *dev) { struct reg_script init_script[] = { REG_SCRIPT_NEXT(init_static_before_exit_latency), @@ -129,7 +129,7 @@ static const struct reg_script no_dev_behind_port[] = { REG_SCRIPT_END, }; -static void check_port_enabled(device_t dev) +static void check_port_enabled(struct device *dev) { int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT; @@ -155,7 +155,7 @@ static void check_port_enabled(device_t dev) } } -static void check_device_present(device_t dev) +static void check_device_present(struct device *dev) { /* Set slot implemented. */ pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); @@ -172,7 +172,7 @@ static void check_device_present(device_t dev) } } -static void byt_pcie_enable(device_t dev) +static void byt_pcie_enable(struct device *dev) { if (is_first_port(dev)) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -194,7 +194,7 @@ static void byt_pcie_enable(device_t dev) southcluster_enable_dev(dev); } -static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did) +static void pcie_root_set_subsystem(struct device *dev, unsigned vid, unsigned did) { uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff); diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index aee3726..6a62a34 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -39,8 +39,8 @@ static inline device_t get_pcu_dev(void) #include <device/device.h> #include <device/pci.h> -static device_t pcu_dev; -static device_t get_pcu_dev(void) +static struct device *pcu_dev; +static struct device *get_pcu_dev(void) { if (pcu_dev == NULL) pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0)); diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 9622930..10f7ff2 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -78,7 +78,7 @@ static const char *stepping_str[] = { static void fill_in_pattrs(void) { - device_t dev; + struct device *dev; msr_t msr; struct pattrs *attrs = (struct pattrs *)pattrs_get(); diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c index 28a2f8c..3c69985 100644 --- a/src/soc/intel/baytrail/sata.c +++ b/src/soc/intel/baytrail/sata.c @@ -159,7 +159,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x98, reg32); } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { config_t *config = dev->chip_info; u8 reg8; diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 7efb66d..e2bd1dd 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -87,7 +87,7 @@ void baytrail_init_scc(void) reg_script_run(scc_after_dll); } -void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) +void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c index 97c8628..6068e61 100644 --- a/src/soc/intel/baytrail/sd.c +++ b/src/soc/intel/baytrail/sd.c @@ -34,7 +34,7 @@ #define CAP_OVERRIDE_HIGH 0xa4 # define USE_CAP_OVERRIDES (1 << 31) -static void sd_init(device_t dev) +static void sd_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 5274b03..21766b7 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -43,12 +43,12 @@ #include "chip.h" static inline void -add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) +add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size) { mmio_resource(dev, i, addr >> 10, size >> 10); } -static void sc_add_mmio_resources(device_t dev) +static void sc_add_mmio_resources(struct device *dev) { add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); @@ -83,7 +83,7 @@ static inline int io_range_in_default(int base, int size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void sc_add_io_resource(device_t dev, int base, int size, int index) +static void sc_add_io_resource(struct device *dev, int base, int size, int index) { struct resource *res; @@ -96,7 +96,7 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void sc_add_io_resources(device_t dev) +static void sc_add_io_resources(struct device *dev) { struct resource *res; @@ -113,7 +113,7 @@ static void sc_add_io_resources(device_t dev) sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE); } -static void sc_read_resources(device_t dev) +static void sc_read_resources(struct device *dev) { /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -154,7 +154,7 @@ static void sc_rtc_init(void) * or configuration. This is definitely a hack, but it helps the kernel * along. */ -static void com1_configure_resume(device_t dev) +static void com1_configure_resume(struct device *dev) { const uint16_t port = 0x3f8; @@ -182,7 +182,7 @@ static void com1_configure_resume(device_t dev) outb(3, port + UART8250_LCR); } -static void sc_init(device_t dev) +static void sc_init(struct device *dev) { int i; const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; @@ -224,7 +224,7 @@ static void sc_init(device_t dev) */ /* Set bit in function disable register to hide this device. */ -static void sc_disable_devfn(device_t dev) +static void sc_disable_devfn(struct device *dev) { const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; @@ -333,7 +333,7 @@ static void sc_disable_devfn(device_t dev) } } -static inline void set_d3hot_bits(device_t dev, int offset) +static inline void set_d3hot_bits(struct device *dev, int offset) { uint32_t reg8; printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); @@ -345,7 +345,7 @@ static inline void set_d3hot_bits(device_t dev, int offset) /* Parts of the audio subsystem are powered by the HDA device. Therefore, one * cannot put HDA into D3Hot. Instead perform this workaround to make some of * the audio paths work for LPE audio. */ -static void hda_work_around(device_t dev) +static void hda_work_around(struct device *dev) { unsigned long gctl = TEMP_BASE_ADDRESS + 0x8; @@ -362,7 +362,7 @@ static void hda_work_around(device_t dev) pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); } -static int place_device_in_d3hot(device_t dev) +static int place_device_in_d3hot(struct device *dev) { unsigned offset; @@ -478,7 +478,7 @@ static int place_device_in_d3hot(device_t dev) } /* Common PCI device function disable. */ -void southcluster_enable_dev(device_t dev) +void southcluster_enable_dev(struct device *dev) { uint32_t reg32; diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 8605dfc..ad33eb9 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -285,13 +285,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) static ich9_spi_regs *spi_regs(void) { - device_t dev; uint32_t sbase; +/* N.B. dev is stage dependent typed */ #ifdef __SMM__ - dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + device_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); #else - dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); #endif pci_read_config_dword(dev, SBASE, &sbase); sbase &= ~0x1ff; diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 8d076c2..3f3ed91 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -148,7 +148,7 @@ const struct reg_script xhci_clock_gating_script[] = { }; /* Warm Reset a USB3 port */ -static void xhci_reset_port_usb3(device_t dev, int port) +static void xhci_reset_port_usb3(struct device *dev, int port) { struct reg_script reset_port_usb3_script[] = { /* Issue Warm Port Rest to the port */ @@ -167,7 +167,7 @@ static void xhci_reset_port_usb3(device_t dev, int port) } /* Prepare ports to be routed to EHCI or XHCI */ -static void xhci_route_all(device_t dev) +static void xhci_route_all(struct device *dev) { static const struct reg_script xhci_route_all_script[] = { /* USB3 SuperSpeed Enable */ @@ -196,7 +196,7 @@ static void xhci_route_all(device_t dev) } } -static void xhci_init(device_t dev) +static void xhci_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script xhci_hc_init[] = { diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 5e7b72b..4b16256 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -394,7 +394,7 @@ static int generate_T_state_entries(int core, int cores_per_package) static int generate_C_state_entries(void) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; config_t *config = dev->chip_info; acpi_cstate_t map[3]; int *set; diff --git a/src/soc/intel/broadwell/broadwell/me.h b/src/soc/intel/broadwell/broadwell/me.h index ddecaf8..f3021ee 100644 --- a/src/soc/intel/broadwell/broadwell/me.h +++ b/src/soc/intel/broadwell/broadwell/me.h @@ -465,7 +465,7 @@ typedef struct { } __attribute__ ((packed)) mbp_plat_time; typedef struct { - u32 device_type : 2; + u32 struct device *ype : 2; u32 reserved : 30; } __attribute__ ((packed)) mbp_nfc_data; diff --git a/src/soc/intel/broadwell/broadwell/pch.h b/src/soc/intel/broadwell/broadwell/pch.h index e677215..c58b695 100644 --- a/src/soc/intel/broadwell/broadwell/pch.h +++ b/src/soc/intel/broadwell/broadwell/pch.h @@ -47,6 +47,6 @@ int pch_is_wpt(void); int pch_is_wpt_ulx(void); u32 pch_read_soft_strap(int id); void pch_log_state(void); -void pch_disable_devfn(device_t dev); +void pch_disable_devfn(struct device *dev); #endif diff --git a/src/soc/intel/broadwell/broadwell/ramstage.h b/src/soc/intel/broadwell/broadwell/ramstage.h index 685de14..d66e8cc 100644 --- a/src/soc/intel/broadwell/broadwell/ramstage.h +++ b/src/soc/intel/broadwell/broadwell/ramstage.h @@ -24,8 +24,8 @@ #include <chip.h> void broadwell_init_pre_device(void *chip_info); -void broadwell_init_cpus(device_t dev); -void broadwell_pch_enable_dev(device_t dev); +void broadwell_init_cpus(struct device *dev); +void broadwell_pch_enable_dev(struct device *dev); #if CONFIG_HAVE_REFCODE_BLOB void broadwell_run_reference_code(void); diff --git a/src/soc/intel/broadwell/broadwell/xhci.h b/src/soc/intel/broadwell/broadwell/xhci.h index 3f4fb4e..a5536fc 100644 --- a/src/soc/intel/broadwell/broadwell/xhci.h +++ b/src/soc/intel/broadwell/broadwell/xhci.h @@ -55,7 +55,7 @@ #define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */ #ifdef __SMM__ -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ); +void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ); #endif #endif diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c index 2a12820..ef19e8e 100644 --- a/src/soc/intel/broadwell/chip.c +++ b/src/soc/intel/broadwell/chip.c @@ -24,7 +24,7 @@ #include <broadwell/ramstage.h> #include <chip.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -43,7 +43,7 @@ static struct device_operations cpu_bus_ops = { .init = &broadwell_init_cpus, }; -static void broadwell_enable(device_t dev) +static void broadwell_enable(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { @@ -65,7 +65,7 @@ struct chip_operations soc_intel_broadwell_ops = { .init = &broadwell_init_pre_device, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index afd2dcb..d2b1bcd 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -444,7 +444,7 @@ static void configure_c_states(void) static void configure_thermal_target(void) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; config_t *conf = dev->chip_info; msr_t msr; @@ -587,7 +587,7 @@ static void bsp_init_before_ap_bringup(struct bus *cpu_bus) } /* All CPUs including BSP will run the following function. */ -static void cpu_core_init(device_t cpu) +static void cpu_core_init(struct device *cpu) { /* Clear out pending MCEs */ configure_mca(); @@ -671,7 +671,7 @@ static const struct cpu_driver driver __cpu_driver = { .id_table = cpu_table, }; -void broadwell_init_cpus(device_t dev) +void broadwell_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; int num_threads; diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c index a59d3c8..30f4acd 100644 --- a/src/soc/intel/broadwell/ehci.c +++ b/src/soc/intel/broadwell/ehci.c @@ -28,7 +28,7 @@ #include <broadwell/ehci.h> #include <broadwell/pch.h> -static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { u8 access_cntl; diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 394a9d7..4ed8a11 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -92,9 +92,9 @@ static void pch_enable_ioapic(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; config_t *config = dev->chip_info; pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); @@ -129,7 +129,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u16 reg16; const char *state; @@ -328,7 +328,7 @@ static void pch_pm_init(struct device *dev) RCBA32_OR(0x3a6c, 0x00000001); } -static void pch_cg_init(device_t dev) +static void pch_cg_init(struct device *dev) { u32 reg32; u16 reg16; @@ -423,7 +423,7 @@ static void lpc_init(struct device *dev) pch_set_acpi_mode(); } -static void pch_lpc_add_mmio_resources(device_t dev) +static void pch_lpc_add_mmio_resources(struct device *dev) { u32 reg; struct resource *res; @@ -485,7 +485,7 @@ static inline int pch_io_range_in_default(u16 base, u16 size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) +static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index) { struct resource *res; @@ -498,7 +498,7 @@ static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) +static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index) { /* * Check if the register is enabled. If so and the base exceeds the @@ -511,7 +511,7 @@ static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) } } -static void pch_lpc_add_io_resources(device_t dev) +static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -536,7 +536,7 @@ static void pch_lpc_add_io_resources(device_t dev) pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { global_nvs_t *gnvs; diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 2bdb1ed..45bbac7 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -57,11 +57,11 @@ static const char *me_bios_path_values[] = { [ME_DISABLE_BIOS_PATH] = "Disable", [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev); +static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev); /* MMIO base address for MEI interface */ static u32 mei_base_address; -void intel_me_mbp_clear(device_t dev); +void intel_me_mbp_clear(struct device *dev); #if CONFIG_DEBUG_INTEL_ME static void mei_dump(void *ptr, int dword, int offset, const char *type) @@ -116,7 +116,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) mei_dump(ptr, dword, offset, "WRITE"); } -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -439,7 +439,7 @@ static inline int mei_sendrecv_icc(struct icc_header *icc, * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read * state machine on the BIOS end doesn't match the ME's state machine. */ -static void intel_me_mbp_give_up(device_t dev) +static void intel_me_mbp_give_up(struct device *dev) { struct mei_csr csr; @@ -455,7 +455,7 @@ static void intel_me_mbp_give_up(device_t dev) * mbp clear routine. This will wait for the ME to indicate that * the MBP has been read and cleared. */ -void intel_me_mbp_clear(device_t dev) +void intel_me_mbp_clear(struct device *dev) { int count; struct me_hfs2 hfs2; @@ -567,7 +567,7 @@ static int mkhi_end_of_post(void) void intel_me_finalize(void) { - device_t dev = PCH_DEV_ME; + struct device *dev = PCH_DEV_ME; struct me_hfs hfs; u32 reg32; @@ -628,7 +628,7 @@ static int me_icc_set_clock_enables(u32 mask) } /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -698,7 +698,7 @@ static me_bios_path intel_me_path(device_t dev) } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -728,7 +728,7 @@ static int intel_mei_setup(device_t dev) } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -775,7 +775,7 @@ static int intel_me_extend_valid(device_t dev) } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { config_t *config = dev->chip_info; me_bios_path path = intel_me_path(dev); @@ -828,7 +828,7 @@ static void intel_me_init(device_t dev) */ } -static void intel_me_enable(device_t dev) +static void intel_me_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME /* Avoid talking to the device in S3 path */ @@ -881,7 +881,7 @@ struct mbp_payload { * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. */ -static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) +static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) { mbp_header mbp_hdr; u32 me2host_pending; diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index 492d177..d44ef78 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -81,7 +81,7 @@ u32 pch_read_soft_strap(int id) #ifndef __PRE_RAM__ /* Put device in D3Hot Power State */ -static void pch_enable_d3hot(device_t dev) +static void pch_enable_d3hot(struct device *dev) { u32 reg32 = pci_read_config32(dev, PCH_PCS); reg32 |= PCH_PCS_PS_D3HOT; @@ -89,7 +89,7 @@ static void pch_enable_d3hot(device_t dev) } /* Set bit in Function Disable register to hide this device */ -void pch_disable_devfn(device_t dev) +void pch_disable_devfn(struct device *dev) { switch (dev->path.pci.devfn) { case PCH_DEVFN_ADSP: /* Audio DSP */ @@ -179,7 +179,7 @@ void pch_disable_devfn(device_t dev) } } -void broadwell_pch_enable_dev(device_t dev) +void broadwell_pch_enable_dev(struct device *dev) { u32 reg32; diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index f167ca3..ad4470e 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -32,8 +32,8 @@ #include <broadwell/rcba.h> #include <chip.h> -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or); -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or); +static void pcie_update_cfg8(struct device *dev, int reg, u8 mask, u8 or); +static void pcie_update_cfg(struct device *dev, int reg, u32 mask, u32 or); /* Low Power variant has 6 root ports. */ #define NUM_ROOT_PORTS 6 @@ -52,23 +52,23 @@ struct root_port_config { int coalesce; int gbe_port; int num_ports; - device_t ports[NUM_ROOT_PORTS]; + struct device *ports[NUM_ROOT_PORTS]; }; static struct root_port_config rpc; -static inline int root_port_is_first(device_t dev) +static inline int root_port_is_first(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) == 0; } -static inline int root_port_is_last(device_t dev) +static inline int root_port_is_last(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1); } /* Root ports are numbered 1..N in the documentation. */ -static inline int root_port_number(device_t dev) +static inline int root_port_number(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) + 1; } @@ -98,7 +98,7 @@ static void root_port_config_update_gbe_port(void) } } -static void root_port_init_config(device_t dev) +static void root_port_init_config(struct device *dev) { int rp; @@ -149,7 +149,7 @@ static void root_port_init_config(device_t dev) /* Update devicetree with new Root Port function number assignment */ static void pch_pcie_device_set_func(int index, int pci_func) { - device_t dev; + struct device *dev; unsigned new_devfn; dev = rpc.ports[index]; @@ -178,7 +178,7 @@ static void pcie_enable_clock_gating(void) int enabled_ports = 0; for (i = 0; i < rpc.num_ports; i++) { - device_t dev; + struct device *dev; int rp; dev = rpc.ports[i]; @@ -244,7 +244,7 @@ static void root_port_commit_config(void) pcie_enable_clock_gating(); for (i = 0; i < rpc.num_ports; i++) { - device_t dev; + struct device *dev; u32 reg32; dev = rpc.ports[i]; @@ -297,7 +297,7 @@ static void root_port_commit_config(void) RCBA32(RPFN) = rpc.new_rpfn; } -static void root_port_mark_disable(device_t dev) +static void root_port_mark_disable(struct device *dev) { /* Mark device as disabled. */ dev->enabled = 0; @@ -305,7 +305,7 @@ static void root_port_mark_disable(device_t dev) rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); } -static void root_port_check_disable(device_t dev) +static void root_port_check_disable(struct device *dev) { int rp; @@ -376,7 +376,7 @@ static void root_port_check_disable(device_t dev) } } -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or) +static void pcie_update_cfg8(struct device *dev, int reg, u8 mask, u8 or) { u8 reg8; @@ -386,7 +386,7 @@ static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or) pci_write_config8(dev, reg, reg8); } -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) +static void pcie_update_cfg(struct device *dev, int reg, u32 mask, u32 or) { u32 reg32; @@ -574,7 +574,7 @@ static void pch_pcie_init(struct device *dev) pci_write_config16(dev, 0x1e, reg16); } -static void pch_pcie_enable(device_t dev) +static void pch_pcie_enable(struct device *dev) { /* Add this device to the root port config structure. */ root_port_init_config(dev); @@ -594,7 +594,7 @@ static void pch_pcie_enable(device_t dev) root_port_commit_config(); } -static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pcie_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { /* NOTE: This is not the default position! */ if (!vendor || !device) diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c index 8214a8a..2517fef 100644 --- a/src/soc/intel/broadwell/romstage/uart.c +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -52,7 +52,7 @@ void pch_uart_init(void) { /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */ u32 gpiodf = 0x131f; - device_t dev; + struct device *dev; /* Put UART in byte access mode for 16550 compatibility */ switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) { diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index e8d1fbe..24a8ebe 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -221,7 +221,7 @@ static void sata_init(struct device *dev) * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index a1dbdfe..c214510 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -31,7 +31,7 @@ #include <broadwell/ramstage.h> #include <broadwell/smbus.h> -static void pch_smbus_init(device_t dev) +static void pch_smbus_init(struct device *dev) { struct resource *res; u16 reg16; @@ -47,7 +47,7 @@ static void pch_smbus_init(device_t dev) outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device *dev, u8 address) { u16 device; struct resource *res; @@ -60,7 +60,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 data) +static int lsmbus_write_byte(struct device *dev, u8 address, u8 data) { u16 device; struct resource *res; @@ -77,7 +77,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -static void smbus_read_resources(device_t dev) +static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); res->base = SMBUS_BASE_ADDRESS; diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 064a9dc..5f616d0 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -83,7 +83,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + struct device *dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index bd1fc26..9ba6a00 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -196,7 +196,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) } } -static u32 northbridge_get_base_reg(device_t dev, int reg) +static u32 northbridge_get_base_reg(struct device *dev, int reg) { u32 value; @@ -206,7 +206,7 @@ static u32 northbridge_get_base_reg(device_t dev, int reg) return value; } -static void fill_in_relocation_params(device_t dev, +static void fill_in_relocation_params(struct device *dev, struct smm_relocation_params *params) { u32 tseg_size; @@ -351,7 +351,7 @@ static int install_permanent_handler(int num_cpus, static int cpu_smm_setup(void) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; int num_cpus; msr_t msr; diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 935c532..783eb93 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -286,7 +286,7 @@ void spi_init(void) uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; - device_t dev = PCH_DEV_LPC; + struct device *dev = PCH_DEV_LPC; ich9_spi_regs *ich9_spi; pci_read_config_dword(dev, 0xf0, &rcba); diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 7fc45a3..0923b0b 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -37,7 +37,7 @@ #include <broadwell/ramstage.h> #include <broadwell/systemagent.h> -static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; @@ -70,7 +70,7 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) return 0; } -static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -89,7 +89,7 @@ static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) /* There are special BARs that actually are programmed in the MCHBAR. These * Intel special features, but they do consume resources that need to be * accounted for. */ -static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, +static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -109,7 +109,7 @@ static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(device_t dev, unsigned int index, + int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); const char *description; }; @@ -127,7 +127,7 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = { * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. */ -static void mc_add_fixed_mmio_resources(device_t dev) +static void mc_add_fixed_mmio_resources(struct device *dev) { int i; @@ -184,7 +184,7 @@ struct map_entry { const char *description; }; -static void read_map_entry(device_t dev, struct map_entry *entry, +static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) { uint64_t value; @@ -253,7 +253,7 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), }; -static void mc_read_map_entries(device_t dev, uint64_t *values) +static void mc_read_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -261,7 +261,7 @@ static void mc_read_map_entries(device_t dev, uint64_t *values) } } -static void mc_report_map_entries(device_t dev, uint64_t *values) +static void mc_report_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -272,7 +272,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values) printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device *dev) { unsigned long base_k, size_k; unsigned long touud_k; @@ -376,7 +376,7 @@ static void mc_add_dram_resources(device_t dev) chromeos_reserve_ram_oops(dev, index++); } -static void systemagent_read_resources(device_t dev) +static void systemagent_read_resources(struct device *dev) { /* Read standard PCI resources. */ pci_dev_read_resources(dev); @@ -412,7 +412,7 @@ static void systemagent_init(struct device *dev) set_power_limits(28); } -static void systemagent_enable(device_t dev) +static void systemagent_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME struct romstage_handoff *handoff; diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index 89e1139..9530422 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -27,7 +27,7 @@ #include <broadwell/xhci.h> #ifdef __SMM__ -static u32 usb_xhci_mem_base(device_t dev) +static u32 usb_xhci_mem_base(struct device *dev) { u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -38,7 +38,7 @@ static u32 usb_xhci_mem_base(device_t dev) return mem_base & ~0xf; } -static int usb_xhci_port_count_usb3(device_t dev) +static int usb_xhci_port_count_usb3(struct device *dev) { /* PCH-LP has 4 SS ports */ return 4; @@ -71,7 +71,7 @@ static void usb_xhci_reset_port_usb3(u32 mem_base, int port) * b) Poll for warm reset complete * c) Write 1 to port change status bits */ -static void usb_xhci_reset_usb3(device_t dev, int all) +static void usb_xhci_reset_usb3(struct device *dev, int all) { u32 status, port_disabled; int timeout, port; @@ -142,7 +142,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all) } /* Handler for XHCI controller on entry to S3/S4/S5 */ -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) +void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ) { u16 reg16; u32 reg32; diff --git a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h index d3a2377..d991d34 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h +++ b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h @@ -57,7 +57,7 @@ void rangeley_early_initialization(void); int soc_silicon_revision(void); int soc_silicon_type(void); int soc_silicon_supported(int type, int rev); -void soc_enable(device_t dev); +void soc_enable(struct device *dev); /* debugging functions */ void print_pci_devices(void); diff --git a/src/soc/intel/fsp_baytrail/baytrail/ramstage.h b/src/soc/intel/fsp_baytrail/baytrail/ramstage.h index 095f09c..c1114df 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/ramstage.h +++ b/src/soc/intel/fsp_baytrail/baytrail/ramstage.h @@ -25,10 +25,10 @@ /* The baytrail_init_pre_device() function is called prior to device * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(void); -void baytrail_init_cpus(device_t dev); +void baytrail_init_cpus(struct device *dev); void set_max_freq(void); -void southcluster_enable_dev(device_t dev); -void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); +void southcluster_enable_dev(struct device *dev); +void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c index 732d1dc..5b54874 100644 --- a/src/soc/intel/fsp_baytrail/chip.c +++ b/src/soc/intel/fsp_baytrail/chip.c @@ -25,12 +25,12 @@ #include <drivers/intel/fsp/fsp_util.h> #include "chip.h" -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } -static void finalize_dev (device_t dev) +static void finalize_dev (struct device *dev) { /* * Notify FSP for PostPciEnumeration. @@ -58,7 +58,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = NULL, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { printk(BIOS_DEBUG, "enable_dev(%s, %d)\n", dev_name(dev), dev->path.type); @@ -98,7 +98,7 @@ struct chip_operations soc_intel_fsp_baytrail_ops = { .final = &finalize_chip, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 1d8c6ea..c8dd775 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -68,7 +68,7 @@ const struct reg_script core_msr_script[] = { REG_SCRIPT_END }; -void baytrail_init_cpus(device_t dev) +void baytrail_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; const struct pattrs *pattrs = pattrs_get(); @@ -91,7 +91,7 @@ void baytrail_init_cpus(device_t dev) } } -static void baytrail_core_init(device_t cpu) +static void baytrail_core_init(struct device *cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 838e554..010063e 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -92,7 +92,7 @@ uint32_t nc_read_top_of_low_memory(void) static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -141,7 +141,7 @@ static int add_fixed_resources(struct device *dev, int index) return index; } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device *dev) { u32 bmbound, bsmmrrl; int index = 0; @@ -189,7 +189,7 @@ static void mc_add_dram_resources(device_t dev) index = add_fixed_resources(dev, index); } -static void nc_read_resources(device_t dev) +static void nc_read_resources(struct device *dev) { /* Call the normal read_resources */ pci_dev_read_resources(dev); @@ -199,7 +199,7 @@ static void nc_read_resources(device_t dev) mc_add_dram_resources(dev); } -static void nc_enable(device_t dev) +static void nc_enable(struct device *dev) { print_fsp_info(); } diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c index aee3726..6a62a34 100644 --- a/src/soc/intel/fsp_baytrail/pmutil.c +++ b/src/soc/intel/fsp_baytrail/pmutil.c @@ -39,8 +39,8 @@ static inline device_t get_pcu_dev(void) #include <device/device.h> #include <device/pci.h> -static device_t pcu_dev; -static device_t get_pcu_dev(void) +static struct device *pcu_dev; +static struct device *get_pcu_dev(void) { if (pcu_dev == NULL) pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0)); diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index 814b16e..55abb4d 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -76,7 +76,7 @@ static const char *stepping_str[] = { static void fill_in_pattrs(void) { - device_t dev; + struct device *dev; msr_t msr; struct pattrs *attrs = (struct pattrs *)pattrs_get(); diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index d87935b..40b783a 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -51,12 +51,12 @@ typedef struct soc_intel_fsp_baytrail_config config_t; static inline void -add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) +add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size) { mmio_resource(dev, i, addr >> 10, size >> 10); } -static void sc_add_mmio_resources(device_t dev) +static void sc_add_mmio_resources(struct device *dev) { #ifndef CONFIG_VIRTUAL_ROM_SIZE #error CONFIG_VIRTUAL_ROM_SIZE must be set. @@ -171,8 +171,8 @@ static void sc_enable_serial_irqs(struct device *dev) */ static void write_pci_config_irqs(void) { - device_t irq_dev; - device_t targ_dev; + struct device *irq_dev; + struct device *targ_dev; uint8_t int_line = 0; uint8_t original_int_pin = 0; uint8_t new_int_pin = 0; @@ -255,7 +255,7 @@ static void write_pci_config_irqs(void) printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); } -static void sc_pirq_init(device_t dev) +static void sc_pirq_init(struct device *dev) { int i, j; int pirq; @@ -318,7 +318,7 @@ static inline int io_range_in_default(int base, int size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void sc_add_io_resource(device_t dev, int base, int size, int index) +static void sc_add_io_resource(struct device *dev, int base, int size, int index) { struct resource *res; @@ -332,7 +332,7 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index) IORESOURCE_FIXED; } -static void sc_add_io_resources(device_t dev) +static void sc_add_io_resources(struct device *dev) { struct resource *res; u8 io_index = 0; @@ -354,7 +354,7 @@ static void sc_add_io_resources(device_t dev) sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); } -static void sc_read_resources(device_t dev) +static void sc_read_resources(struct device *dev) { /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -409,7 +409,7 @@ static void sc_init(struct device *dev) */ /* Set bit in function disable register to hide this device. */ -static void sc_disable_devfn(device_t dev) +static void sc_disable_devfn(struct device *dev) { const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; @@ -457,7 +457,7 @@ static void sc_disable_devfn(device_t dev) } } -static inline void set_d3hot_bits(device_t dev, int offset) +static inline void set_d3hot_bits(struct device *dev, int offset) { uint32_t reg8; printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); @@ -469,7 +469,7 @@ static inline void set_d3hot_bits(device_t dev, int offset) /* Parts of the audio subsystem are powered by the HDA device. Therefore, one * cannot put HDA into D3Hot. Instead perform this workaround to make some of * the audio paths work for LPE audio. */ -static void hda_work_around(device_t dev) +static void hda_work_around(struct device *dev) { unsigned long gctl = TEMP_BASE_ADDRESS + 0x8; @@ -486,7 +486,7 @@ static void hda_work_around(device_t dev) pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); } -static int place_device_in_d3hot(device_t dev) +static int place_device_in_d3hot(struct device *dev) { unsigned offset; @@ -563,7 +563,7 @@ static int place_device_in_d3hot(device_t dev) } /* Common PCI device function disable. */ -void southcluster_enable_dev(device_t dev) +void southcluster_enable_dev(struct device *dev) { uint32_t reg32; diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 0c3c63d..ea4b30f 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -282,13 +282,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) static ich9_spi_regs *spi_regs(void) { - device_t dev; uint32_t sbase; +/* N.B. dev is type-dependent on stage */ #ifdef __SMM__ - dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + device_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); #else - dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); #endif pci_read_config_dword(dev, SBASE, &sbase); sbase &= ~0x1ff; diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index c0b1986..099f668 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -500,7 +500,7 @@ struct tegra_dc { unsigned long READL(void * p); void WRITEL(unsigned long value, void * p); -void display_startup(device_t dev); +void display_startup(struct device *dev); void dp_init(void * _config); void dp_enable(void * _dp); unsigned int fb_base_mb(void); diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 9ad76f0..21e29a5 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -215,7 +215,7 @@ uint32_t fb_base_mb(void) /* this is really aimed at the lcd panel. That said, there are two display * devices on this part and we may someday want to extend it for other boards. */ -void display_startup(device_t dev) +void display_startup(struct device *dev) { struct soc_nvidia_tegra124_config *config = dev->chip_info; struct display_controller *disp_ctrl = (void *)config->display_controller; diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index 48e50bd..028524b 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -32,7 +32,7 @@ * Will break if we get 2. Sigh. * We assume it's all multiples of MiB for MMUs sake. */ -static void soc_enable(device_t dev) +static void soc_enable(struct device *dev) { u32 lcdbase = fb_base_mb(); unsigned long fb_size = FB_SIZE_MB; @@ -49,7 +49,7 @@ static void soc_enable(device_t dev) (sdram_end_mb - sdram_max_addressable_mb())*KiB); } -static void soc_init(device_t dev) +static void soc_init(struct device *dev) { if (vboot_skip_display_init()) printk(BIOS_INFO, "Skipping display init.\n"); @@ -66,7 +66,7 @@ static struct device_operations soc_ops = { .scan_bus = 0, }; -static void enable_tegra124_dev(device_t dev) +static void enable_tegra124_dev(struct device *dev) { dev->ops = &soc_ops; } diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index 60fa55a..639a45a 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -59,7 +59,7 @@ static void set_cpu_id(void) * involving lots of machine and callbacks, is hard to debug and * verify. */ -static void exynos_displayport_init(device_t dev, u32 lcdbase, +static void exynos_displayport_init(struct device *dev, u32 lcdbase, unsigned long fb_size) { struct soc_samsung_exynos5250_config *conf = dev->chip_info; @@ -110,7 +110,7 @@ static void exynos_displayport_init(device_t dev, u32 lcdbase, lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); } -static void cpu_enable(device_t dev) +static void cpu_enable(struct device *dev) { unsigned long fb_size = FB_SIZE_KB * KiB; u32 lcdbase = get_fb_base_kb() * KiB; @@ -123,7 +123,7 @@ static void cpu_enable(device_t dev) set_cpu_id(); } -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", cpu_id, get_arm_clk() / (1024*1024)); @@ -137,7 +137,7 @@ static struct device_operations cpu_ops = { .scan_bus = 0, }; -static void enable_exynos5250_dev(device_t dev) +static void enable_exynos5250_dev(struct device *dev) { dev->ops = &cpu_ops; } diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index e8649a0..8a1335d 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -73,7 +73,7 @@ static void set_cpu_id(void) * involving lots of machine and callbacks, is hard to debug and * verify. */ -static void exynos_displayport_init(device_t dev, u32 lcdbase, +static void exynos_displayport_init(struct device *dev, u32 lcdbase, unsigned long fb_size) { struct soc_samsung_exynos5420_config *conf = dev->chip_info; @@ -133,7 +133,7 @@ static void tps65090_thru_ec_fet_disable(int index) } } -static void cpu_enable(device_t dev) +static void cpu_enable(struct device *dev) { unsigned long fb_size = FB_SIZE_KB * KiB; u32 lcdbase = get_fb_base_kb() * KiB; @@ -154,7 +154,7 @@ static void cpu_enable(device_t dev) set_cpu_id(); } -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", cpu_id, get_arm_clk() / 1000000); @@ -168,7 +168,7 @@ static struct device_operations cpu_ops = { .scan_bus = 0, }; -static void enable_exynos5420_dev(device_t dev) +static void enable_exynos5420_dev(struct device *dev) { dev->ops = &cpu_ops; }

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coreboot-gerrit December 2014