coreboot-gerrit December 2014

coreboot-gerrit@coreboot.org

1 participants
1346 discussions

New patch to review for coreboot: ab51c1c storm: Put the page table at a correct address
by Marc Jones 31 Dec '14

31 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8019 -gerrit commit ab51c1ca4dd2ca2f6aeaf28f5033a8b679d7171b Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Jun 4 17:38:51 2014 -0700 storm: Put the page table at a correct address The recently introduced page table location value is wrong, it overlaps with other areas of the code. This patch fixes the location, a more robust scheme is needed for memory layout management. BUG=none TEST=manual . occasional random failures disappear after this patch is applied Original-Change-Id: Idc9047d38712736c5e8197e933c373488b333649 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202641 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit d26bb18e506680a1f481c3950007b2ea6a48e54d) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I7afcab42db259e53541fb991b36d680fc2186304 --- src/soc/qualcomm/ipq806x/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 8ab5e67..c91686e 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -73,6 +73,6 @@ config CBFS_CACHE_SIZE config TTB_BUFFER hex "memory address for page tables" - default 0x405f0000 + default 0x405c0000 endif

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Patch set updated for coreboot: 03ccb86 ipq8064: work around for slow timer clock
by Marc Jones 31 Dec '14

31 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8004 -gerrit commit 03ccb86af9cf5f8f582b457e5332c9e65d16549d Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri May 23 14:18:35 2014 -0700 ipq8064: work around for slow timer clock Libpayload libc requires timer clock frequency to be at least 1MHz. Ipq8064 code presently provides a single option of 32kHz. Pretend to be running at 1 MHz without additional accuracy. This is a hack which will be reverted as soon as the SOC is configured to supply a faster running clock. BUG=chrome-os-partner:27784, chrome-os-partner:28880 TEST=with other changes depthcharge boots to the CLI console Original-Change-Id: I80ec6652bc5693a549668cd6e824e9cf5c26b182 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201342 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 466a59967b13986099106f8b44924648c1e6e6cd) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I113689191db70710e7a45ccd02d672f482343e35 --- payloads/libpayload/drivers/timer/ipq806x.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/timer/ipq806x.c b/payloads/libpayload/drivers/timer/ipq806x.c index 4edbf8e..0d70a86 100644 --- a/payloads/libpayload/drivers/timer/ipq806x.c +++ b/payloads/libpayload/drivers/timer/ipq806x.c @@ -29,13 +29,31 @@ #include <libpayload.h> +/* + * TODO(vbendeb): reverted this hack once proper timer code is in place (see + * http://crosbug.com/p/28880 for details. + */ +#define MIN_TIMER_FREQ 1000000 + uint64_t timer_hz(void) { - return CONFIG_LP_IPQ806X_TIMER_FREQ; + return (CONFIG_LP_IPQ806X_TIMER_FREQ >= MIN_TIMER_FREQ) ? + CONFIG_LP_IPQ806X_TIMER_FREQ : MIN_TIMER_FREQ; } uint64_t timer_raw_value(void) { - return readl((void *)CONFIG_LP_IPQ806X_TIMER_REG); + uint64_t rawv = readl((void *)CONFIG_LP_IPQ806X_TIMER_REG); + + /* + * This is extremely crude, but it kicks in only for the case when the + * timer clock frequency is below 1MHz, which should never be the case + * on a properly configured system. The compiler will eliminate the + * check as long as config value exceeds 1MHz. + */ + if (CONFIG_LP_IPQ806X_TIMER_FREQ < MIN_TIMER_FREQ) + rawv *= (MIN_TIMER_FREQ / CONFIG_LP_IPQ806X_TIMER_FREQ); + + return rawv; }

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Patch set updated for coreboot: 32d429e libpayload: ipq8064: Add rudimentary timer driver
by Marc Jones 31 Dec '14

31 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8002 -gerrit commit 32d429ecbe4736c95a6242a09babe128db4f6fba Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed May 21 16:28:57 2014 -0700 libpayload: ipq8064: Add rudimentary timer driver This is still using the 32kHz timer coreboot uses. A finer granularity timer implementation for 806x is in the works. BUG=chrome-os-partner:27784,chrome-os-partner:28880 TEST=none yet. Original-Change-Id: Iae206749000d45040090df48199c8d86d76bbae5 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/198021 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 8f49f752ab8f84b7c5dc189238732360e8d2aae2) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ia150c974e5b66939de0b007cf7c1308c187f3289 --- payloads/libpayload/Config.in | 18 +++++++++++++ payloads/libpayload/configs/defconfig-arm | 3 ++- payloads/libpayload/drivers/Makefile.inc | 1 + payloads/libpayload/drivers/timer/ipq806x.c | 41 +++++++++++++++++++++++++++++ 4 files changed, 62 insertions(+), 1 deletion(-) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index bef0e05..3c5c342 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -354,6 +354,9 @@ config TIMER_MCT config TIMER_TEGRA_1US bool "Tegra 1us" +config TIMER_IPQ806X + bool "Timer for ipq806x platforms" + endchoice config TIMER_MCT_HZ @@ -371,6 +374,21 @@ config TIMER_TEGRA_1US_ADDRESS depends on TIMER_TEGRA_1US default 0x60005010 +config IPQ806X_TIMER_FREQ + int "Hardware timer frequency" + default 32000 + depends on TIMER_IPQ806X + help + IPQ hardware presently provides a single timer running at 32KHz, a + finer granulariry timer is available but is not yet enabled. + +config IPQ806X_TIMER_REG + hex "Timer register address" + default 0x0200A008 + depends on TIMER_IPQ806X + help + Address of the register to read a free running timer value. + config USB bool "USB Support" default n diff --git a/payloads/libpayload/configs/defconfig-arm b/payloads/libpayload/configs/defconfig-arm index fe47d0c..83731bb 100644 --- a/payloads/libpayload/configs/defconfig-arm +++ b/payloads/libpayload/configs/defconfig-arm @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # libpayload version: 0.2.0 -# Tue Dec 23 15:19:30 2014 +# Wed Dec 31 11:11:44 2014 # # @@ -55,6 +55,7 @@ CONFIG_LP_STORAGE_ATAPI=y CONFIG_LP_TIMER_NONE=y # CONFIG_LP_TIMER_MCT is not set # CONFIG_LP_TIMER_TEGRA_1US is not set +# CONFIG_LP_TIMER_IPQ806X is not set CONFIG_LP_USB=y CONFIG_LP_USB_OHCI=y CONFIG_LP_USB_EHCI=y diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index 7212389..d46bb11 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -48,6 +48,7 @@ libc-$(CONFIG_LP_NVRAM) += options.c libc-$(CONFIG_LP_TIMER_MCT) += timer/mct.c libc-$(CONFIG_LP_TIMER_RDTSC) += timer/rdtsc.c libc-$(CONFIG_LP_TIMER_TEGRA_1US) += timer/tegra_1us.c +libc-$(CONFIG_LP_TIMER_IPQ806X) += timer/ipq806x.c # Video console drivers libc-$(CONFIG_LP_VIDEO_CONSOLE) += video/video.c diff --git a/payloads/libpayload/drivers/timer/ipq806x.c b/payloads/libpayload/drivers/timer/ipq806x.c new file mode 100644 index 0000000..4edbf8e --- /dev/null +++ b/payloads/libpayload/drivers/timer/ipq806x.c @@ -0,0 +1,41 @@ +/* + * This file is part of the depthcharge project. + * + * Copyright (C) 2014 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload.h> + +uint64_t timer_hz(void) +{ + return CONFIG_LP_IPQ806X_TIMER_FREQ; +} + +uint64_t timer_raw_value(void) +{ + return readl((void *)CONFIG_LP_IPQ806X_TIMER_REG); +} +

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Patch set updated for coreboot: 7607aa4 libpayload: Provide selfboot() external declaration in a common file
by Marc Jones 31 Dec '14

31 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8003 -gerrit commit 7607aa4964ec2371ee8ec1973f0a96027d15e26b Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri May 23 14:37:10 2014 -0700 libpayload: Provide selfboot() external declaration in a common file The earlier compilation warning fix (7e4aa17) incorrectly assumed that selfboot() is a function defined in the cbfs driver. This is a commonly available function, it should not come from cbfs.h. BUG=none TEST=the following build command succeeds: rambi storm nyan_big Original-Change-Id: I3ef49d849168ad9dc24589cbd9ce7382052345bd Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201386 (cherry picked from commit d5090e8410530f41b9fd33e2caa1d8aa25438105) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I8404fb52112b391982f954a6d06fe4b451dfcb8a --- payloads/libpayload/include/cbfs.h | 3 --- payloads/libpayload/include/libpayload.h | 6 +++--- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/payloads/libpayload/include/cbfs.h b/payloads/libpayload/include/cbfs.h index c5c811c..1b5c51a 100644 --- a/payloads/libpayload/include/cbfs.h +++ b/payloads/libpayload/include/cbfs.h @@ -81,9 +81,6 @@ void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, // Utility functions int run_address(void *f); -/* Defined in src/lib/selfboot.c */ -void selfboot(void *entry); - /* Defined in individual arch / board implementation. */ int init_default_cbfs_media(struct cbfs_media *media); diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 1d4d0da..9781c9e 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -60,9 +60,6 @@ #ifdef CONFIG_LP_LAR #include <lar.h> #endif -#ifdef CONFIG_LP_CBFS -#include <cbfs.h> -#endif #define MIN(a,b) ((a) < (b) ? (a) : (b)) #define MAX(a,b) ((a) > (b) ? (a) : (b)) @@ -445,4 +442,7 @@ char *readline(const char *prompt); int getline(char *buffer, int len); /** @} */ +/* Defined in arch/${ARCH}/selfboot.c */ +void selfboot(void *entry); + #endif

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New patch to review for coreboot: ffa7141 NOTFORMERGE: gm45: fix broken text-mode graphics.
by Francis Rowe 31 Dec '14

31 Dec '14

Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8018 -gerrit commit ffa714170abc11d7b31853fcd3308a436226c8d0 Author: Francis Rowe <info(a)gluglug.org.uk> Date: Wed Dec 31 18:04:25 2014 +0000 NOTFORMERGE: gm45: fix broken text-mode graphics. When text-mode graphics (disable "Keep VESA Framebuffer") is selected, backlight turns on at payload stage (GRUB tested) but no graphics are shown (black screen). Graphics do work after payload stage, when booting a GNU/Linux distribution. (tested on X200. fix doesn't work yet) Change-Id: Idf6496bb2f578c7dfb15c07f3e46a00ba3da11e7 Signed-off-by: Francis Rowe <info(a)gluglug.org.uk> --- src/northbridge/intel/gm45/gma.c | 53 ++++++++++++++++++++++------------------ 1 file changed, 29 insertions(+), 24 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 74e16ad..482aa1d 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -174,9 +174,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); -#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - vga_textmode_init(); -#else + vga_sr_write(1, 1); vga_sr_write(0x2, 0xf); vga_sr_write(0x3, 0x0); @@ -200,7 +198,6 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + DSPSURF(0), 0); for (i = 0; i < 0x100; i++) write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -#endif /* Find suitable divisors. */ for (candp1 = 1; candp1 <= 8; candp1++) { @@ -272,6 +269,21 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, 120000 * (5 * pixel_m1 + pixel_m2) / pixel_n / (pixel_p1 * 7)); + write32(mmio + PF_WIN_POS(0), 0); +#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(mmio + PFIT_CONTROL, 0xa0000000); +#else + write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1)); + write32(mmio + PF_CTL(0),0); + write32(mmio + PF_WIN_SZ(0), 0); + write32(mmio + PFIT_CONTROL, 0x20000000); +#endif + + mdelay(1); + write32(mmio + LVDS, (hpolarity << 20) | (vpolarity << 21) | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL @@ -328,21 +340,6 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - write32(mmio + PF_WIN_POS(0), 0); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1)); - write32(mmio + PF_CTL(0),0); - write32(mmio + PF_WIN_SZ(0), 0); - write32(mmio + PFIT_CONTROL, 0x20000000); -#else - write32(mmio + PIPESRC(0), (639 << 16) | 399); - write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); - write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); - write32(mmio + PFIT_CONTROL, 0xa0000000); -#endif - - mdelay(1); - write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); write32(mmio + PIPE_DATA_N1(0), data_n1); write32(mmio + PIPE_LINK_M1(0), link_m1); @@ -359,13 +356,13 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) +#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(mmio + VGACNTRL, 0x22c4008e); +#else write32(mmio + VGACNTRL, 0x22c4008e | VGA_DISP_DISABLE); write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); - mdelay(1); -#else - write32(mmio + VGACNTRL, 0x22c4008e); #endif + mdelay(1); write32(mmio + TRANS_HTOTAL(0), ((hactive + right_border + hblank - 1) << 16) @@ -426,7 +423,15 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + DEIIR, 0xffffffff); write32(mmio + SDEIIR, 0xffffffff); -#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) +#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + vga_misc_write(0x67); + + write32(mmio + DSPCNTR(0), DISPPLANE_SEL_PIPE_B); + + write32(mmio + VGACNTRL, 0x22c4008e | VGA_PIPE_B_SELECT); + + vga_textmode_init(); +#else memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4); set_vbe_mode_info_valid(&edid, lfb); #endif

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Patch merged into coreboot/master: 19c3da5 libpayload: Do not tolerate compilation warnings when building
by gerrit＠coreboot.org 31 Dec '14

31 Dec '14

the following patch was just integrated into master: commit 19c3da5e64e09d360895804be7db780d481ddc75 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu May 15 14:12:54 2014 -0700 libpayload: Do not tolerate compilation warnings when building Make sure the build breaks in case of warnings. BUG=none TEST= All builds succeed with the restored patch and fail when a compilation warning is thrown. Original-Change-Id: I9bdcd8938f59913e4ba86df5e4921b3f821ef920 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/200110 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 16dde875950d6806cc770cdbee4d3ff456ed6f02) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I86988f8d3f1acaa6ceeabdcbfa3cede1e67c28fe Reviewed-on: http://review.coreboot.org/7911 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7911 for details. -gerrit

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Patch set updated for coreboot: 40b7df8 ipq8064: add SOC initialization skeleton
by Marc Jones 31 Dec '14

31 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8000 -gerrit commit 40b7df8057135ed3fe247ca133ed13adfc79869c Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue May 13 17:47:57 2014 -0700 ipq8064: add SOC initialization skeleton The main benefit of adding this skeleton is the addition of the correct memory map to CBMEM. Attempts to load depthcharge do not fail because of unavailability of the bounce buffer. BUG=chrome-os-partner:27784 TEST=boot updated firmware on AP148, observe CPU: Qualcomm 8064 in the ramstage console output as well as not failing to load depthcharge any more. Original-Change-Id: I56c1fa34ce3967852be6eaa0de6e823e64c3ede8 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199675 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit a8fdbdd268a2bba1405d585881eb95510ad17a2a) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I7b982f222ac3b93371fe77961f18719c5d269013 --- src/soc/qualcomm/ipq806x/Makefile.inc | 1 + src/soc/qualcomm/ipq806x/soc.c | 49 +++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 68829e2..86bc0a6 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -34,6 +34,7 @@ romstage-$(CONFIG_DYNAMIC_CBMEM) += cbmem.c ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += gpio.c +ramstage-y += soc.c ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += timer.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c diff --git a/src/soc/qualcomm/ipq806x/soc.c b/src/soc/qualcomm/ipq806x/soc.c new file mode 100644 index 0000000..53f5716 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/soc.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> + +static void soc_read_resources(device_t dev) +{ + ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB, + CONFIG_DRAM_SIZE_MB * (1 << 10)); +} + +static void soc_init(device_t dev) +{ + printk(BIOS_INFO, "CPU: Qualcomm 8064\n"); +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(device_t dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_qualcomm_ipq806x_ops = { + CHIP_NAME("SOC Qualcomm 8064") + .enable_dev = enable_soc_dev, +};

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Patch set updated for coreboot: c34ed81 storm: modify memory layout
by Marc Jones 31 Dec '14

31 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8012 -gerrit commit c34ed81da4889caa1a6b5cad7a7cd73a2cc236a3 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed May 28 10:49:51 2014 -0700 storm: modify memory layout This is an interim change (before EFS is enabled), align ROM and RAM stages so that they have enough room and do not step over each other. BUG=chrome-os-partner:27784 TEST=manual . booted coreboot successfully on ap148 Original-Change-Id: I6e1710ac7ca494a69aea5ba3b117bfd882aded26 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202046 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Trevor Bourget <tbourget(a)codeaurora.org> (cherry picked from commit f1fd4e3f9d699cc694cf7840c169db9bbe9193b6) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I9861d34a8bdd6963afbeed7fca7fda8a891ec481 --- src/soc/qualcomm/ipq806x/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 5769a77..8ab5e67 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -45,11 +45,11 @@ config BOOTBLOCK_BASE config ROMSTAGE_BASE hex - default 0x40608000 + default 0x40620000 config RAMSTAGE_BASE hex - default 0x4060c000 + default 0x40640000 config SYS_SDRAM_BASE hex

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Patch set updated for coreboot: a432aff storm: initialize dynamic cbmem properly
by Marc Jones 31 Dec '14

31 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7999 -gerrit commit a432aff018d7f8bcd03bdc6ec6758878032f315f Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue May 13 17:17:22 2014 -0700 storm: initialize dynamic cbmem properly Dynamic cbmem support has been enabled on storm, but the proper initialization at romstage is missing. Proper DRAM base address definition is also necessary so that CBMEM is placed in the correct address range (presently at the top of DRAM). BUG=chrome-os-partner:27784 TEST=build boot coreboot on ap148, observe the following in the console output: Wrote coreboot table at: 5fffd000, 0xe8 bytes, checksum 44a5 coreboot table: 256 bytes. CBMEM ROOT 0. 5ffff000 00001000 COREBOOT 1. 5fffd000 00002000 Original-Change-Id: I74ccd252ddfdeaa0a5bcc929be72be174f310730 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199674 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit e2aeb2f4e7f3959d5f5336f42a29909134a7ddb7) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I9358a65756ef97dc88493c55d69a5673832a22b0 --- src/mainboard/google/storm/romstage.c | 2 ++ src/soc/qualcomm/ipq806x/Kconfig | 11 +++++++---- src/soc/qualcomm/ipq806x/Makefile.inc | 1 + 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/storm/romstage.c b/src/mainboard/google/storm/romstage.c index 6fadedf..85d6b48 100644 --- a/src/mainboard/google/storm/romstage.c +++ b/src/mainboard/google/storm/romstage.c @@ -19,12 +19,14 @@ #include <arch/stages.h> #include <cbfs.h> +#include <cbmem.h> #include <console/console.h> void main(void) { void *entry; + cbmem_initialize_empty(); console_init(); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 385c793..cf11177 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -51,6 +51,9 @@ config RAMSTAGE_BASE hex default 0x4060c000 +config SYS_SDRAM_BASE + hex + default 0x40000000 config STACK_TOP hex @@ -61,11 +64,11 @@ config STACK_BOTTOM default 0x405fc000 config CBFS_CACHE_ADDRESS - hex "memory address to put CBFS cache data" - default 0x405e6000 + hex "memory address to put CBFS cache data" + default 0x405e6000 config CBFS_CACHE_SIZE - hex "size of CBFS cache data" - default 0x00016000 + hex "size of CBFS cache data" + default 0x00016000 endif diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 2379d63..68829e2 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -29,6 +29,7 @@ romstage-y += gpio.c romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-y += timer.c romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-$(CONFIG_DYNAMIC_CBMEM) += cbmem.c ramstage-y += cbmem.c ramstage-y += clock.c

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Patch set updated for coreboot: 0b86218 soc/ipq806x : Add CONFIG_TTB_BUFFER for the soc.
by Marc Jones 31 Dec '14

31 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8009 -gerrit commit 0b8621875016fd01c2e116d3a4eea289bd7a5feb Author: Deepa Dinamani <deepad(a)codeaurora.org> Date: Tue May 13 13:49:42 2014 -0700 soc/ipq806x : Add CONFIG_TTB_BUFFER for the soc. Define a base address for page table entries. Place it 64KB below the bootblock loading address. BUG=chrome-os-partner:28467 TEST=verified that the page tables are being populated at this address. Also observed that the SPI driver takes 900 ns to process a byte as opposed to 1.5 us in case caching is not enabled. Original-Change-Id: I3d8bd3104c55389aa5768033642ebbf1fda0fec7 Original-Signed-off-by: Deepa Dinamani <deepad(a)codeaurora.org> Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/200332 (cherry picked from commit 483dbea46c7d4c8ea8dbaf11bc82990f4cffff8c) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ifef78b9bd6938533bed415ec99fd75a8031a7068 --- src/soc/qualcomm/ipq806x/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index cf11177..5769a77 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -71,4 +71,8 @@ config CBFS_CACHE_SIZE hex "size of CBFS cache data" default 0x00016000 +config TTB_BUFFER + hex "memory address for page tables" + default 0x405f0000 + endif

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coreboot-gerrit December 2014