coreboot-gerrit December 2014

coreboot-gerrit@coreboot.org

1 participants
1346 discussions

New patch to review for coreboot: d06de58 soc/ipq806x : Add CONFIG_TTB_BUFFER for the soc.
by Marc Jones 31 Dec '14

31 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8009 -gerrit commit d06de582a1c3710856c2178d4be60a548c523c2d Author: Deepa Dinamani <deepad(a)codeaurora.org> Date: Tue May 13 13:49:42 2014 -0700 soc/ipq806x : Add CONFIG_TTB_BUFFER for the soc. Define a base address for page table entries. Place it 64KB below the bootblock loading address. BUG=chrome-os-partner:28467 TEST=verified that the page tables are being populated at this address. Also observed that the SPI driver takes 900 ns to process a byte as opposed to 1.5 us in case caching is not enabled. Original-Change-Id: I3d8bd3104c55389aa5768033642ebbf1fda0fec7 Original-Signed-off-by: Deepa Dinamani <deepad(a)codeaurora.org> Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/200332 (cherry picked from commit 483dbea46c7d4c8ea8dbaf11bc82990f4cffff8c) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ifef78b9bd6938533bed415ec99fd75a8031a7068 --- src/soc/qualcomm/ipq806x/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index d6b00ba..fccb251 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -71,4 +71,8 @@ config CBFS_CACHE_SIZE hex "size of CBFS cache data" default 0x00016000 +config TTB_BUFFER + hex "memory address for page tables" + default 0x405f0000 + endif

1 0

New patch to review for coreboot: ea56edb blaze: change ramcode 1000/1001/1010 to use 792MHz bct
by Marc Jones 31 Dec '14

31 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8008 -gerrit commit ea56edbd7c38e4cedcc2d9f34e4abaf4119e3d81 Author: Neil Chen <neilc(a)nvidia.com> Date: Thu May 29 18:20:17 2014 +0800 blaze: change ramcode 1000/1001/1010 to use 792MHz bct This change updates the cfg file for Hynix/Micron/Samsung 4GB, 792MHz DRAM based on the data generated by t124_emc_reg_tool. BUG=none BRANCH=blaze TEST=emerged coreboot, booted successfully into kernel. Original-Change-Id: I7621e60d8dcc568e0bb400a6c96b7f8909a15aa6 Original-Signed-off-by: Neil Chen <neilc(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/202059 Original-Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> (cherry picked from commit 04e74d2fb0fefa6a1786225638380c8831bd9481) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I6615e34a17bb372eda9dd0844ecddbcde902ad7c --- .../google/nyan_blaze/bct/sdram-hynix-4GB-792.inc | 92 +++--- .../google/nyan_blaze/bct/sdram-micron-4GB-792.inc | 311 +++++++++++++++++++++ .../nyan_blaze/bct/sdram-samsung-4GB-792.inc | 311 +++++++++++++++++++++ src/mainboard/google/nyan_blaze/sdram_configs.c | 6 +- 4 files changed, 671 insertions(+), 49 deletions(-) diff --git a/src/mainboard/google/nyan_blaze/bct/sdram-hynix-4GB-792.inc b/src/mainboard/google/nyan_blaze/bct/sdram-hynix-4GB-792.inc index 5c8d09c..6afd3b7 100644 --- a/src/mainboard/google/nyan_blaze/bct/sdram-hynix-4GB-792.inc +++ b/src/mainboard/google/nyan_blaze/bct/sdram-hynix-4GB-792.inc @@ -1,4 +1,4 @@ -{ /* generated from sdram-0100-792-4GB.cfg; do not edit. */ +{ /* generated from Hynix_4GB_H5TC8G63AFR_PBA_792MHz_release.cfg; do not edit. */ .MemoryType = NvBootMemoryType_Ddr3, .PllMInputDivider = 0x00000001, .PllMFeedbackDivider = 0x00000042, @@ -24,7 +24,7 @@ .EmcBctSpare11 = 0x00000000, .EmcClockSource = 0x80000000, .EmcAutoCalInterval = 0x001fffff, - .EmcAutoCalConfig = 0xa1430000, + .EmcAutoCalConfig = 0xa1430404, .EmcAutoCalConfig2 = 0x00000000, .EmcAutoCalConfig3 = 0x00000000, .EmcAutoCalWait = 0x00000190, @@ -32,19 +32,19 @@ .EmcPinProgramWait = 0x00000001, .EmcPinExtraWait = 0x00000000, .EmcTimingControlWait = 0x00000000, - .EmcRc = 0x00000025, + .EmcRc = 0x00000024, .EmcRfc = 0x00000114, .EmcRfcSlr = 0x00000000, - .EmcRas = 0x0000001a, - .EmcRp = 0x00000007, + .EmcRas = 0x00000019, + .EmcRp = 0x0000000a, .EmcR2r = 0x00000000, .EmcW2w = 0x00000000, .EmcR2w = 0x00000008, .EmcW2r = 0x0000000d, .EmcR2p = 0x00000004, .EmcW2p = 0x00000013, - .EmcRdRcd = 0x00000009, - .EmcWrRcd = 0x00000009, + .EmcRdRcd = 0x0000000a, + .EmcWrRcd = 0x0000000a, .EmcRrd = 0x00000003, .EmcRext = 0x00000002, .EmcWext = 0x00000000, @@ -105,8 +105,8 @@ .EmcExtraModeRegWriteEnable = 0x00000000, .EmcMrwResetCommand = 0x00000000, .EmcMrwResetNInitWait = 0x00000000, - .EmcMrsWaitCnt = 0x006f000c, - .EmcMrsWaitCnt2 = 0x006f000c, + .EmcMrsWaitCnt = 0x006f000e, + .EmcMrsWaitCnt2 = 0x006f000e, .EmcCfg = 0x73300000, .EmcCfg2 = 0x0000089d, .EmcCfgPipe = 0x00004080, @@ -123,18 +123,18 @@ .EmcDllXformDqs1 = 0x00000008, .EmcDllXformDqs2 = 0x00000008, .EmcDllXformDqs3 = 0x00000008, - .EmcDllXformDqs4 = 0x00000008, - .EmcDllXformDqs5 = 0x00000008, - .EmcDllXformDqs6 = 0x00000008, - .EmcDllXformDqs7 = 0x00000008, + .EmcDllXformDqs4 = 0x00000006, + .EmcDllXformDqs5 = 0x00000006, + .EmcDllXformDqs6 = 0x00000006, + .EmcDllXformDqs7 = 0x007F8008, .EmcDllXformDqs8 = 0x00000008, .EmcDllXformDqs9 = 0x00000008, .EmcDllXformDqs10 = 0x00000008, .EmcDllXformDqs11 = 0x00000008, - .EmcDllXformDqs12 = 0x00000008, - .EmcDllXformDqs13 = 0x00000008, - .EmcDllXformDqs14 = 0x00000008, - .EmcDllXformDqs15 = 0x00000008, + .EmcDllXformDqs12 = 0x00000006, + .EmcDllXformDqs13 = 0x00000006, + .EmcDllXformDqs14 = 0x00000006, + .EmcDllXformDqs15 = 0x007F8008, .EmcDllXformQUse0 = 0x00000000, .EmcDllXformQUse1 = 0x00000000, .EmcDllXformQUse2 = 0x00000000, @@ -143,11 +143,11 @@ .EmcDllXformQUse5 = 0x00000000, .EmcDllXformQUse6 = 0x00000000, .EmcDllXformQUse7 = 0x00000000, - .EmcDllXformAddr0 = 0x00034000, - .EmcDllXformAddr1 = 0x00034000, + .EmcDllXformAddr0 = 0x0002c000, + .EmcDllXformAddr1 = 0x0002c000, .EmcDllXformAddr2 = 0x00000000, - .EmcDllXformAddr3 = 0x00034000, - .EmcDllXformAddr4 = 0x00034000, + .EmcDllXformAddr3 = 0x0002c000, + .EmcDllXformAddr4 = 0x0002c000, .EmcDllXformAddr5 = 0x00000000, .EmcDllXformQUse8 = 0x00000000, .EmcDllXformQUse9 = 0x00000000, @@ -160,19 +160,19 @@ .EmcDliTrimTxDqs0 = 0x00000008, .EmcDliTrimTxDqs1 = 0x00000008, .EmcDliTrimTxDqs2 = 0x00000005, - .EmcDliTrimTxDqs3 = 0x00000009, - .EmcDliTrimTxDqs4 = 0x00000009, - .EmcDliTrimTxDqs5 = 0x00000007, - .EmcDliTrimTxDqs6 = 0x00000009, - .EmcDliTrimTxDqs7 = 0x00000008, + .EmcDliTrimTxDqs3 = 0x00000008, + .EmcDliTrimTxDqs4 = 0x0000000a, + .EmcDliTrimTxDqs5 = 0x00000008, + .EmcDliTrimTxDqs6 = 0x0000000a, + .EmcDliTrimTxDqs7 = 0x0000000a, .EmcDliTrimTxDqs8 = 0x00000008, .EmcDliTrimTxDqs9 = 0x00000008, .EmcDliTrimTxDqs10 = 0x00000005, - .EmcDliTrimTxDqs11 = 0x00000009, - .EmcDliTrimTxDqs12 = 0x00000009, - .EmcDliTrimTxDqs13 = 0x00000007, - .EmcDliTrimTxDqs14 = 0x00000009, - .EmcDliTrimTxDqs15 = 0x00000008, + .EmcDliTrimTxDqs11 = 0x00000008, + .EmcDliTrimTxDqs12 = 0x0000000a, + .EmcDliTrimTxDqs13 = 0x00000008, + .EmcDliTrimTxDqs14 = 0x0000000a, + .EmcDliTrimTxDqs15 = 0x0000000a, .EmcDllXformDq0 = 0x0000000e, .EmcDllXformDq1 = 0x0000000e, .EmcDllXformDq2 = 0x0000000e, @@ -226,30 +226,30 @@ .EmcXm2CmdPadCtrl5 = 0x00111111, .EmcXm2DqsPadCtrl = 0x770c1414, .EmcXm2DqsPadCtrl2 = 0x0120113d, - .EmcXm2DqsPadCtrl3 = 0x61861820, + .EmcXm2DqsPadCtrl3 = 0x69A69A20, .EmcXm2DqsPadCtrl4 = 0x00514514, - .EmcXm2DqsPadCtrl5 = 0x00514514, - .EmcXm2DqsPadCtrl6 = 0x61861800, + .EmcXm2DqsPadCtrl5 = 0x00514510, + .EmcXm2DqsPadCtrl6 = 0x69A69A00, .EmcXm2DqPadCtrl = 0x770c2990, .EmcXm2DqPadCtrl2 = 0x00000000, .EmcXm2DqPadCtrl3 = 0x00000000, .EmcXm2ClkPadCtrl = 0x77ffc085, - .EmcXm2ClkPadCtrl2 = 0x00000101, + .EmcXm2ClkPadCtrl2 = 0x00000202, .EmcXm2CompPadCtrl = 0x81f1f108, .EmcXm2VttGenPadCtrl = 0x07070004, .EmcXm2VttGenPadCtrl2 = 0x00000000, .EmcXm2VttGenPadCtrl3 = 0x016eeeee, .EmcAcpdControl = 0x00000000, .EmcSwizzleRank0ByteCfg = 0x00003120, - .EmcSwizzleRank0Byte0 = 0x25143067, - .EmcSwizzleRank0Byte1 = 0x45367102, - .EmcSwizzleRank0Byte2 = 0x47106253, - .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank0Byte0 = 0x01643752, + .EmcSwizzleRank0Byte1 = 0x34675021, + .EmcSwizzleRank0Byte2 = 0x63170254, + .EmcSwizzleRank0Byte3 = 0x14065327, .EmcSwizzleRank1ByteCfg = 0x00003120, - .EmcSwizzleRank1Byte0 = 0x71546032, - .EmcSwizzleRank1Byte1 = 0x35104276, - .EmcSwizzleRank1Byte2 = 0x27043615, - .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcSwizzleRank1Byte0 = 0x73541062, + .EmcSwizzleRank1Byte1 = 0x10637254, + .EmcSwizzleRank1Byte2 = 0x62043715, + .EmcSwizzleRank1Byte3 = 0x73015624, .EmcDsrVttgenDrv = 0x0606003f, .EmcTxdsrvttgen = 0x00000000, .EmcBgbiasCtl0 = 0x00000000, @@ -264,7 +264,7 @@ .McEmemArbCfg = 0x0e00000b, .McEmemArbOutstandingReq = 0x80000040, .McEmemArbTimingRcd = 0x00000004, - .McEmemArbTimingRp = 0x00000004, + .McEmemArbTimingRp = 0x00000005, .McEmemArbTimingRc = 0x00000013, .McEmemArbTimingRas = 0x0000000c, .McEmemArbTimingFaw = 0x0000000f, @@ -276,7 +276,7 @@ .McEmemArbTimingR2W = 0x00000006, .McEmemArbTimingW2R = 0x00000008, .McEmemArbDaTurns = 0x08060202, - .McEmemArbDaCovers = 0x00150c13, + .McEmemArbDaCovers = 0x00170e13, .McEmemArbMisc0 = 0x746c2414, .McEmemArbMisc1 = 0x70000f02, .McEmemArbRing1Throttle = 0x001f0000, @@ -301,7 +301,7 @@ .EmcCaTrainingEnable = 0x00000000, .EmcCaTrainingTimingCntl1 = 0x1f7df7df, .EmcCaTrainingTimingCntl2 = 0x0000001f, - .SwizzleRankByteEncode = 0x0000006f, + .SwizzleRankByteEncode = 0x0000000b, .BootRomPatchControl = 0x00000000, .BootRomPatchData = 0x00000000, .McMtsCarveoutBom = 0xfff00000, diff --git a/src/mainboard/google/nyan_blaze/bct/sdram-micron-4GB-792.inc b/src/mainboard/google/nyan_blaze/bct/sdram-micron-4GB-792.inc new file mode 100644 index 0000000..5a7b6be --- /dev/null +++ b/src/mainboard/google/nyan_blaze/bct/sdram-micron-4GB-792.inc @@ -0,0 +1,311 @@ +{ /* generated from Micron_4GB_MT41K512M16TNA-125_792MHz.cfg; do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x00000042, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x80000000, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xA1430404, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000001, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x00000025, + .EmcRfc = 0x000000cc, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x0000001a, + .EmcRp = 0x00000009, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000008, + .EmcW2r = 0x0000000d, + .EmcR2p = 0x00000004, + .EmcW2p = 0x00000013, + .EmcRdRcd = 0x00000009, + .EmcWrRcd = 0x00000009, + .EmcRrd = 0x00000004, + .EmcRext = 0x00000002, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000006, + .EmcWdvMask = 0x00000006, + .EmcQUse = 0x0000000b, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000002, + .EmcEInputDuration = 0x0000000d, + .EmcPutermExtra = 0x00080000, + .EmcPutermWidth = 0x00000004, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000001, + .EmcQSafe = 0x00000014, + .EmcRdv = 0x00000018, + .EmcRdvMask = 0x0000001a, + .EmcQpop = 0x0000000f, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000004, + .EmcRefresh = 0x000017e2, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x000005f8, + .EmcPdEx2Wr = 0x00000003, + .EmcPdEx2Rd = 0x00000011, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x000000c6, + .EmcRw2Pden = 0x00000018, + .EmcTxsr = 0x000000d6, + .EmcTxsrDll = 0x00000200, + .EmcTcke = 0x00000005, + .EmcTckesr = 0x00000006, + .EmcTpd = 0x00000005, + .EmcTfaw = 0x0000001d, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x00000008, + .EmcTClkStop = 0x00000008, + .EmcTRefBw = 0x00001822, + .EmcFbioCfg5 = 0x104ab098, + .EmcFbioCfg6 = 0x00000000, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x00000d71, + .EmcEmrs = 0x00100002, + .EmcEmrs2 = 0x00200018, + .EmcEmrs3 = 0x00300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x00b6000c, + .EmcMrsWaitCnt2 = 0x00b6000c, + .EmcCfg = 0x73300000, + .EmcCfg2 = 0x0000089d, + .EmcCfgPipe = 0x00004080, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x80003012, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0xe00700b1, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000000, + .EmcSelDpdCtrl = 0x00040000, + .EmcDllXformDqs0 = 0x00000008, + .EmcDllXformDqs1 = 0x00000008, + .EmcDllXformDqs2 = 0x00000008, + .EmcDllXformDqs3 = 0x00000008, + .EmcDllXformDqs4 = 0x00000008, + .EmcDllXformDqs5 = 0x00000008, + .EmcDllXformDqs6 = 0x00000008, + .EmcDllXformDqs7 = 0x00000008, + .EmcDllXformDqs8 = 0x00000008, + .EmcDllXformDqs9 = 0x00000008, + .EmcDllXformDqs10 = 0x00000008, + .EmcDllXformDqs11 = 0x00000008, + .EmcDllXformDqs12 = 0x00000008, + .EmcDllXformDqs13 = 0x00000008, + .EmcDllXformDqs14 = 0x00000008, + .EmcDllXformDqs15 = 0x00000008, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x0002c000, + .EmcDllXformAddr1 = 0x0002c000, + .EmcDllXformAddr2 = 0x00000000, + .EmcDllXformAddr3 = 0x0002c000, + .EmcDllXformAddr4 = 0x0002c000, + .EmcDllXformAddr5 = 0x00000000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000008, + .EmcDliTrimTxDqs1 = 0x00000008, + .EmcDliTrimTxDqs2 = 0x00000005, + .EmcDliTrimTxDqs3 = 0x00000008, + .EmcDliTrimTxDqs4 = 0x0000000a, + .EmcDliTrimTxDqs5 = 0x00000008, + .EmcDliTrimTxDqs6 = 0x0000000a, + .EmcDliTrimTxDqs7 = 0x0000000a, + .EmcDliTrimTxDqs8 = 0x00000008, + .EmcDliTrimTxDqs9 = 0x00000008, + .EmcDliTrimTxDqs10 = 0x00000005, + .EmcDliTrimTxDqs11 = 0x00000008, + .EmcDliTrimTxDqs12 = 0x0000000a, + .EmcDliTrimTxDqs13 = 0x00000008, + .EmcDliTrimTxDqs14 = 0x0000000a, + .EmcDliTrimTxDqs15 = 0x0000000a, + .EmcDllXformDq0 = 0x0000000e, + .EmcDllXformDq1 = 0x0000000e, + .EmcDllXformDq2 = 0x0000000e, + .EmcDllXformDq3 = 0x0000000e, + .EmcDllXformDq4 = 0x0000000e, + .EmcDllXformDq5 = 0x0000000e, + .EmcDllXformDq6 = 0x0000000e, + .EmcDllXformDq7 = 0x0000000e, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x00000042, + .EmcZcalMrwCmd = 0x00000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x40000011, + .EmcZcalInitWait = 0x00000001, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000001, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x00000d71, + .EmcWarmBootMrsExtra = 0x00100002, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fffffff, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x100002a0, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0120113d, + .EmcXm2DqsPadCtrl3 = 0x61861820, + .EmcXm2DqsPadCtrl4 = 0x00514514, + .EmcXm2DqsPadCtrl5 = 0x00514514, + .EmcXm2DqsPadCtrl6 = 0x61861800, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc085, + .EmcXm2ClkPadCtrl2 = 0x00000202, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x00000000, + .EmcXm2VttGenPadCtrl3 = 0x016eeeee, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x01643752, + .EmcSwizzleRank0Byte1 = 0x34675021, + .EmcSwizzleRank0Byte2 = 0x63170254, + .EmcSwizzleRank0Byte3 = 0x14065327, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x73541062, + .EmcSwizzleRank1Byte1 = 0x10637254, + .EmcSwizzleRank1Byte2 = 0x62043715, + .EmcSwizzleRank1Byte3 = 0x73015624, + .EmcDsrVttgenDrv = 0x0606003f, + .EmcTxdsrvttgen = 0x00000000, + .EmcBgbiasCtl0 = 0x00000000, + .McEmemAdrCfg = 0x00000001, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00001000, + .McEmemArbCfg = 0x0e00000b, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000004, + .McEmemArbTimingRp = 0x00000005, + .McEmemArbTimingRc = 0x00000013, + .McEmemArbTimingRas = 0x0000000c, + .McEmemArbTimingFaw = 0x0000000f, + .McEmemArbTimingRrd = 0x00000002, + .McEmemArbTimingRap2Pre = 0x00000003, + .McEmemArbTimingWap2Pre = 0x0000000c, + .McEmemArbTimingR2R = 0x00000002, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000006, + .McEmemArbTimingW2R = 0x00000008, + .McEmemArbDaTurns = 0x08060202, + .McEmemArbDaCovers = 0x00160d13, + .McEmemArbMisc0 = 0x734c2414, + .McEmemArbMisc1 = 0x70000f02, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000000b, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/nyan_blaze/bct/sdram-samsung-4GB-792.inc b/src/mainboard/google/nyan_blaze/bct/sdram-samsung-4GB-792.inc new file mode 100644 index 0000000..f8c3a5f --- /dev/null +++ b/src/mainboard/google/nyan_blaze/bct/sdram-samsung-4GB-792.inc @@ -0,0 +1,311 @@ +{ /* generated from Samsung_4GB_K4B8G1646Q_792MHz_release.cfg; do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x00000042, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x80000000, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xa1430707, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000001, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x00000025, + .EmcRfc = 0x00000114, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x0000001a, + .EmcRp = 0x00000009, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000008, + .EmcW2r = 0x0000000d, + .EmcR2p = 0x00000004, + .EmcW2p = 0x00000013, + .EmcRdRcd = 0x00000009, + .EmcWrRcd = 0x00000009, + .EmcRrd = 0x00000004, + .EmcRext = 0x00000002, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000006, + .EmcWdvMask = 0x00000006, + .EmcQUse = 0x0000000b, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000002, + .EmcEInputDuration = 0x0000000d, + .EmcPutermExtra = 0x00080000, + .EmcPutermWidth = 0x00000004, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000001, + .EmcQSafe = 0x00000014, + .EmcRdv = 0x00000018, + .EmcRdvMask = 0x0000001a, + .EmcQpop = 0x0000000f, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000004, + .EmcRefresh = 0x000017e2, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x000005f8, + .EmcPdEx2Wr = 0x00000003, + .EmcPdEx2Rd = 0x00000011, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x0000010d, + .EmcRw2Pden = 0x00000018, + .EmcTxsr = 0x0000011e, + .EmcTxsrDll = 0x00000200, + .EmcTcke = 0x00000005, + .EmcTckesr = 0x00000006, + .EmcTpd = 0x00000005, + .EmcTfaw = 0x0000001d, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x00000008, + .EmcTClkStop = 0x00000008, + .EmcTRefBw = 0x00001822, + .EmcFbioCfg5 = 0x104ab098, + .EmcFbioCfg6 = 0x00000000, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x00000d71, + .EmcEmrs = 0x00100002, + .EmcEmrs2 = 0x00200018, + .EmcEmrs3 = 0x00300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x006f000c, + .EmcMrsWaitCnt2 = 0x006f000c, + .EmcCfg = 0x73300000, + .EmcCfg2 = 0x0000089d, + .EmcCfgPipe = 0x00004080, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x80003012, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0xe00700b1, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000000, + .EmcSelDpdCtrl = 0x00040000, + .EmcDllXformDqs0 = 0x00000009, + .EmcDllXformDqs1 = 0x0000000a, + .EmcDllXformDqs2 = 0x00000009, + .EmcDllXformDqs3 = 0x0000000a, + .EmcDllXformDqs4 = 0x0000000b, + .EmcDllXformDqs5 = 0x0000000a, + .EmcDllXformDqs6 = 0x0000000b, + .EmcDllXformDqs7 = 0x00000008, + .EmcDllXformDqs8 = 0x00000009, + .EmcDllXformDqs9 = 0x0000000a, + .EmcDllXformDqs10 = 0x00000009, + .EmcDllXformDqs11 = 0x0000000a, + .EmcDllXformDqs12 = 0x0000000b, + .EmcDllXformDqs13 = 0x0000000a, + .EmcDllXformDqs14 = 0x0000000b, + .EmcDllXformDqs15 = 0x00000008, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x0002c000, + .EmcDllXformAddr1 = 0x0002c000, + .EmcDllXformAddr2 = 0x00000000, + .EmcDllXformAddr3 = 0x0002c000, + .EmcDllXformAddr4 = 0x0002c000, + .EmcDllXformAddr5 = 0x00000000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000008, + .EmcDliTrimTxDqs1 = 0x00000008, + .EmcDliTrimTxDqs2 = 0x00000005, + .EmcDliTrimTxDqs3 = 0x00000008, + .EmcDliTrimTxDqs4 = 0x0000000a, + .EmcDliTrimTxDqs5 = 0x00000008, + .EmcDliTrimTxDqs6 = 0x0000000a, + .EmcDliTrimTxDqs7 = 0x0000000a, + .EmcDliTrimTxDqs8 = 0x00000008, + .EmcDliTrimTxDqs9 = 0x00000008, + .EmcDliTrimTxDqs10 = 0x00000005, + .EmcDliTrimTxDqs11 = 0x00000008, + .EmcDliTrimTxDqs12 = 0x0000000a, + .EmcDliTrimTxDqs13 = 0x00000008, + .EmcDliTrimTxDqs14 = 0x0000000a, + .EmcDliTrimTxDqs15 = 0x0000000a, + .EmcDllXformDq0 = 0x0000000c, + .EmcDllXformDq1 = 0x0000000c, + .EmcDllXformDq2 = 0x0000000c, + .EmcDllXformDq3 = 0x0000000c, + .EmcDllXformDq4 = 0x0000000c, + .EmcDllXformDq5 = 0x0000000c, + .EmcDllXformDq6 = 0x0000000c, + .EmcDllXformDq7 = 0x0000000c, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x00000042, + .EmcZcalMrwCmd = 0x00000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x40000011, + .EmcZcalInitWait = 0x00000001, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000001, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x00000d71, + .EmcWarmBootMrsExtra = 0x00100002, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fffffff, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x100002a0, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0120113d, + .EmcXm2DqsPadCtrl3 = 0x61869a20, + .EmcXm2DqsPadCtrl4 = 0x00596596, + .EmcXm2DqsPadCtrl5 = 0x00596596, + .EmcXm2DqsPadCtrl6 = 0x69969900, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc085, + .EmcXm2ClkPadCtrl2 = 0x00000202, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x00000000, + .EmcXm2VttGenPadCtrl3 = 0x016eeeee, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x01643752, + .EmcSwizzleRank0Byte1 = 0x34675021, + .EmcSwizzleRank0Byte2 = 0x63170254, + .EmcSwizzleRank0Byte3 = 0x14065327, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x73541062, + .EmcSwizzleRank1Byte1 = 0x10637254, + .EmcSwizzleRank1Byte2 = 0x62043715, + .EmcSwizzleRank1Byte3 = 0x73015624, + .EmcDsrVttgenDrv = 0x0606003f, + .EmcTxdsrvttgen = 0x00000000, + .EmcBgbiasCtl0 = 0x00000000, + .McEmemAdrCfg = 0x00000001, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00001000, + .McEmemArbCfg = 0x0e00000b, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000004, + .McEmemArbTimingRp = 0x00000005, + .McEmemArbTimingRc = 0x00000013, + .McEmemArbTimingRas = 0x0000000c, + .McEmemArbTimingFaw = 0x0000000f, + .McEmemArbTimingRrd = 0x00000002, + .McEmemArbTimingRap2Pre = 0x00000003, + .McEmemArbTimingWap2Pre = 0x0000000c, + .McEmemArbTimingR2R = 0x00000002, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000006, + .McEmemArbTimingW2R = 0x00000008, + .McEmemArbDaTurns = 0x08060202, + .McEmemArbDaCovers = 0x00160d13, + .McEmemArbMisc0 = 0x746c2414, + .McEmemArbMisc1 = 0x70000f02, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000000b, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/nyan_blaze/sdram_configs.c b/src/mainboard/google/nyan_blaze/sdram_configs.c index 74f32fa..6fb517d 100644 --- a/src/mainboard/google/nyan_blaze/sdram_configs.c +++ b/src/mainboard/google/nyan_blaze/sdram_configs.c @@ -30,9 +30,9 @@ static struct sdram_params sdram_configs[] = { #include "bct/sdram-unused.inc" /* ram_code = 0101 */ #include "bct/sdram-unused.inc" /* ram_code = 0110 */ #include "bct/sdram-unused.inc" /* ram_code = 0111 */ -#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1000 */ -#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1001 */ -#include "bct/sdram-samsung-4GB-204.inc" /* ram_code = 1010 */ +#include "bct/sdram-hynix-4GB-792.inc" /* ram_code = 1000 */ +#include "bct/sdram-micron-4GB-792.inc" /* ram_code = 1001 */ +#include "bct/sdram-samsung-4GB-792.inc" /* ram_code = 1010 */ #include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1011 */ #include "bct/sdram-unused.inc" /* ram_code = 1100 */ #include "bct/sdram-unused.inc" /* ram_code = 1101 */

1 0

New patch to review for coreboot: 79624a8 samus: Update for board revision 1.9
by Marc Jones 31 Dec '14

31 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8007 -gerrit commit 79624a856f74ca8842c834e277993d24b394ac38 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu May 22 08:25:36 2014 -0700 samus: Update for board revision 1.9 - Update GPIO map - Update SPD for new memory and 4-bit table decode - Enable USB3 port 3 and 4 (shared with PCIe port 1) - Enable PCIe port 3 and disable port 1 - Enable SerialIO ACPI mode for devices - Disable S0ix for now to prevent use of C10 - Special handling for memory with broadwell CPU BUG=chrome-os-partner:28234 TEST=Boot on P1.9 Original-Change-Id: If6adcc2ea76f1af7613b715133483d7661e94dd8 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201083 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 35835eaed3e098597e46f602fbd646cfbb899355) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Icb03808da6d92705bbc411d155c25de57c4409c6 --- .../google/samus/acpi/haswell_pci_irqs.asl | 91 ----------- src/mainboard/google/samus/acpi/mainboard.asl | 169 ++++++++++++++++----- src/mainboard/google/samus/devicetree.cb | 15 +- src/mainboard/google/samus/gpio.h | 30 ++-- src/mainboard/google/samus/mainboard.c | 66 +------- src/mainboard/google/samus/onboard.h | 70 --------- src/mainboard/google/samus/pei_data.c | 22 +-- src/mainboard/google/samus/romstage.c | 18 ++- src/mainboard/google/samus/spd/Makefile.inc | 26 ++-- src/mainboard/google/samus/spd/hynix_4Gb.spd.hex | 18 +++ src/mainboard/google/samus/spd/hynix_8Gb.spd.hex | 18 +++ src/mainboard/google/samus/spd/spd.c | 11 +- src/mainboard/google/samus/spd/spd.h | 1 + 13 files changed, 246 insertions(+), 309 deletions(-) diff --git a/src/mainboard/google/samus/acpi/haswell_pci_irqs.asl b/src/mainboard/google/samus/acpi/haswell_pci_irqs.asl deleted file mode 100644 index 336a1ac..0000000 --- a/src/mainboard/google/samus/acpi/haswell_pci_irqs.asl +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for Haswell ULT */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // Audio DSP (Smart Sound) 0:13.0 - Package() { 0x0013ffff, 0, 0, 23 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 18 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 22 }, - Package() { 0x001fffff, 1, 0, 18 }, - Package() { 0x001fffff, 2, 0, 17 }, - Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, 0, 20 }, - Package() { 0x0015ffff, 1, 0, 21 }, - Package() { 0x0015ffff, 2, 0, 21 }, - Package() { 0x0015ffff, 3, 0, 21 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, 0, 23 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // Audio DSP (Smart Sound) 0:13.0 - Package() { 0x0013ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - }) - } -} diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl index 72bff6c..5a052b9 100644 --- a/src/mainboard/google/samus/acpi/mainboard.asl +++ b/src/mainboard/google/samus/acpi/mainboard.asl @@ -1,12 +1,11 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Google Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -15,21 +14,17 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <mainboard/google/samus/onboard.h> - Scope (\_SB) { Device (LID0) { - Name(_HID, EisaId("PNP0C0D")) - Method(_LID, 0) + Name (_HID, EisaId("PNP0C0D")) + Method (_LID, 0) { - Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) - Return (\LIDS) + Return (\_SB.PCI0.LPCB.EC0.LIDS) } // There is no GPIO for LID, the EC pulses WAKE# pin instead. @@ -44,49 +39,149 @@ Scope (\_SB) Device (TPAD) { - Name (_ADR, 0x0) + Name (_HID, EisaId("PNP0C0E")) Name (_UID, 1) + Name (_PRW, Package() { 13, 0x3 }) // GPIO13 + } - // Report as a Sleep Button device so Linux will - // automatically enable it as a wake source + Device (TSCR) + { Name (_HID, EisaId("PNP0C0E")) + Name (_UID, 2) + Name (_PRW, Package() { 14, 0x3 }) // GPIO14 + } +} + +Scope (\_SB.PCI0.I2C0) +{ + Device (ATPB) + { + Name (_HID, "ATML0000") + Name (_DDN, "Atmel Touchpad Bootloader") + Name (_UID, 1) + Name (_S0W, 4) + Name (ISTP, 1) /* Touchpad */ Name (_CRS, ResourceTemplate() { - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TRACKPAD_IRQ - } + I2cSerialBus ( + 0x25, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C0", // ResourceSource + ) - VendorShort (ADDR) - { - BOARD_TRACKPAD_I2C_ADDR - } + // GPIO13 is PIRQL + Interrupt (ResourceConsumer, Edge, ActiveLow) { 27 } }) - Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } } - Device (TSCR) + Device (ATPA) { - Name (_ADR, 0x0) + Name (_HID, "ATML0000") + Name (_DDN, "Atmel Touchpad") Name (_UID, 2) - - // Report as a Sleep Button device so Linux will - // automatically enable it as a wake source - Name (_HID, EisaId("PNP0C0E")) + Name (_S0W, 4) + Name (ISTP, 1) /* Touchpad */ Name (_CRS, ResourceTemplate() { - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TOUCHSCREEN_IRQ + I2cSerialBus ( + 0x4b, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C0", // ResourceSource + ) + + // GPIO13 is PIRQL + Interrupt (ResourceConsumer, Edge, ActiveLow) { 27 } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) } + } + } +} + +Scope (\_SB.PCI0.I2C1) +{ + Device (ATSB) + { + Name (_HID, "ATML0001") + Name (_DDN, "Atmel Touchscreen Bootloader") + Name (_UID, 4) + Name (_S0W, 4) + Name (ISTP, 0) /* TouchScreen */ - VendorShort (ADDR) - { - BOARD_TOUCHSCREEN_I2C_ADDR + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x25, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C1", // ResourceSource + ) + + // GPIO14 is PIRQM + Interrupt (ResourceConsumer, Edge, ActiveLow) { 28 } + }) + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) } + } + } + + Device (ATSA) + { + Name (_HID, "ATML0001") + Name (_DDN, "Atmel Touchscreen") + Name (_UID, 5) + Name (_S0W, 4) + Name (ISTP, 0) /* TouchScreen */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x4b, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C1", // ResourceSource + ) + + // GPIO14 is PIRQM + Interrupt (ResourceConsumer, Edge, ActiveLow) { 28 } }) + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } } } diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb index 3e87eca..8810c47 100644 --- a/src/mainboard/google/samus/devicetree.cb +++ b/src/mainboard/google/samus/devicetree.cb @@ -43,16 +43,17 @@ chip soc/intel/broadwell register "gpe0_en_4" = "0x00000000" register "sata_port_map" = "0x1" - register "sio_acpi_mode" = "0" + register "sio_acpi_mode" = "1" - # Force enable ASPM for PCIe Port 1 - register "pcie_port_force_aspm" = "0x01" + # Force enable ASPM for PCIe Port 3 + register "pcie_port_force_aspm" = "0x04" + register "pcie_port_coalesce" = "1" # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013e0000" + register "icc_clock_disable" = "0x013b0000" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" device cpu_cluster 0 on device lapic 0 on end @@ -77,9 +78,9 @@ chip soc/intel/broadwell device pci 17.0 off end # SDIO device pci 19.0 off end # GbE device pci 1b.0 off end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 + device pci 1c.0 off end # PCIe Port #1 device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 + device pci 1c.2 on end # PCIe Port #3 device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 diff --git a/src/mainboard/google/samus/gpio.h b/src/mainboard/google/samus/gpio.h index c98be4d..f68ecdf 100644 --- a/src/mainboard/google/samus/gpio.h +++ b/src/mainboard/google/samus/gpio.h @@ -34,7 +34,7 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ PCH_GPIO_ACPI_SCI, /* 8: PCH_LTE_WAKE_L */ - PCH_GPIO_IRQ_EDGE, /* 9: NFC_INT (GPIO IRQ) */ + PCH_GPIO_PIRQ, /* 9: NFC_INT (PIRQ) */ PCH_GPIO_ACPI_SCI, /* 10: PCH_WLAN_WAKE_L */ PCH_GPIO_UNUSED, /* 11: UNUSED */ PCH_GPIO_UNUSED, /* 12: UNUSED */ @@ -43,9 +43,9 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ PCH_GPIO_INPUT, /* 16: PCH_WP */ PCH_GPIO_UNUSED, /* 17: UNUSED */ - PCH_GPIO_NATIVE, /* 18: PCIE_WLAN_CLKREQ_L */ + PCH_GPIO_UNUSED, /* 18: UNUSED */ PCH_GPIO_UNUSED, /* 19: UNUSED */ - PCH_GPIO_UNUSED, /* 20: UNUSED */ + PCH_GPIO_NATIVE, /* 20: PCIE_WLAN_CLKREQ_L */ PCH_GPIO_OUT_HIGH, /* 21: PP3300_SSD_EN */ PCH_GPIO_UNUSED, /* 22: UNUSED */ PCH_GPIO_OUT_LOW, /* 23: PP3300_AUTOBAHN_EN */ @@ -69,12 +69,12 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_NATIVE, /* 41: NATIVE: PCH_USB2_OC_L */ PCH_GPIO_OUT_HIGH, /* 42: WLAN_DISABLE_L */ PCH_GPIO_OUT_HIGH, /* 43: PP1800_CODEC_EN */ - PCH_GPIO_OUT_HIGH, /* 44: CODEC_LDOENA */ - PCH_GPIO_PIRQ, /* 45: ACCEL_INT (PIRQW) */ - PCH_GPIO_PIRQ, /* 46: CODEC_INT_L (PIRQO) */ - PCH_GPIO_PIRQ, /* 47: ACCEL_GYRO_INT (PIRQP) */ + PCH_GPIO_UNUSED, /* 44: UNUSED */ + PCH_GPIO_PIRQ, /* 45: DSP_INT (PIRQN) */ + PCH_GPIO_PIRQ, /* 46: HOTWORD_DET_L (PIRQO) */ + PCH_GPIO_OUT_HIGH, /* 47: SSD_RESET_L */ PCH_GPIO_UNUSED, /* 48: UNUSED */ - PCH_GPIO_INPUT, /* 49: HDMI_CEC */ + PCH_GPIO_UNUSED, /* 49: UNUSED */ PCH_GPIO_UNUSED, /* 50: UNUSED */ PCH_GPIO_UNUSED, /* 51: UNUSED */ PCH_GPIO_INPUT, /* 52: SIM_DET */ @@ -88,10 +88,10 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 60: UNUSED */ PCH_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */ PCH_GPIO_NATIVE, /* 62: NATIVE: PCH_SUSCLK */ - PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SS5_L */ + PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ PCH_GPIO_OUT_LOW, /* 64: NFC_FW_UPDATE */ - PCH_GPIO_INPUT, /* 65: MINIDP_PWR_FLT_L */ - PCH_GPIO_OUT_HIGH, /* 66: MINIDP_PWR_EN */ + PCH_GPIO_UNUSED, /* 65: UNUSED */ + PCH_GPIO_INPUT, /* 66: RAM_ID3 */ PCH_GPIO_INPUT, /* 67: RAM_ID0 */ PCH_GPIO_INPUT, /* 68: RAM_ID1 */ PCH_GPIO_INPUT, /* 69: RAM_ID2 */ @@ -116,10 +116,10 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 88: UNUSED */ PCH_GPIO_OUT_HIGH, /* 89: PP3300_SD_EN */ PCH_GPIO_UNUSED, /* 90: UNUSED */ - PCH_GPIO_NATIVE, /* 91: NATIVE: UART0_PCHRX_BTTX */ - PCH_GPIO_NATIVE, /* 92: NATIVE: UART0_PCHTX_BTRX */ - PCH_GPIO_NATIVE, /* 93: NATIVE: UART0_PCHRTS_BTCTS_L */ - PCH_GPIO_NATIVE, /* 94: NATIVE: UART0_PCHCTS_BTRTS_L */ + PCH_GPIO_UNUSED, /* 91: UNUSED */ + PCH_GPIO_UNUSED, /* 92: UNUSED */ + PCH_GPIO_UNUSED, /* 93: UNUSED */ + PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; diff --git a/src/mainboard/google/samus/mainboard.c b/src/mainboard/google/samus/mainboard.c index fdc7d78..89303b9 100644 --- a/src/mainboard/google/samus/mainboard.c +++ b/src/mainboard/google/samus/mainboard.c @@ -33,73 +33,14 @@ #include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include "ec.h" -#include "onboard.h" -static void mainboard_init(device_t dev) +void mainboard_suspend_resume(void) { - mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, - unsigned long *current) +static void mainboard_init(device_t dev) { - int len = 0; - - len += smbios_write_type41( - current, handle, - BOARD_TRACKPAD_NAME, /* name */ - BOARD_TRACKPAD_IRQ, /* instance */ - BOARD_TRACKPAD_I2C_BUS, /* segment */ - BOARD_TRACKPAD_I2C_ADDR, /* bus */ - BOARD_TRACKPAD_IRQ_TYPE, /* device */ - 0); /* function */ - - len += smbios_write_type41( - current, handle, - BOARD_TOUCHSCREEN_NAME, /* name */ - BOARD_TOUCHSCREEN_IRQ, /* instance */ - BOARD_TOUCHSCREEN_I2C_BUS, /* segment */ - BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ - BOARD_TOUCHSCREEN_IRQ_TYPE, /* device */ - 0); /* function */ - - len += smbios_write_type41( - current, handle, - BOARD_CODEC_NAME, /* name */ - BOARD_CODEC_IRQ, /* instance */ - BOARD_CODEC_I2C_BUS, /* segment */ - BOARD_CODEC_I2C_ADDR, /* bus */ - BOARD_CODEC_IRQ_TYPE, /* device */ - 0); /* function */ - - len += smbios_write_type41( - current, handle, - BOARD_NFC_NAME, /* name */ - BOARD_NFC_IRQ, /* instance */ - BOARD_NFC_I2C_BUS, /* segment */ - BOARD_NFC_I2C_ADDR, /* bus */ - BOARD_NFC_IRQ_TYPE, /* device */ - 0); /* function */ - - len += smbios_write_type41( - current, handle, - BOARD_ACCEL_NAME, /* name */ - BOARD_ACCEL_IRQ, /* instance */ - BOARD_ACCEL_I2C_BUS, /* segment */ - BOARD_ACCEL_I2C_ADDR, /* bus */ - BOARD_ACCEL_IRQ_TYPE, /* device */ - 0); /* function */ - - len += smbios_write_type41( - current, handle, - BOARD_ACCEL_GYRO_NAME, /* name */ - BOARD_ACCEL_GYRO_IRQ, /* instance */ - BOARD_ACCEL_GYRO_I2C_BUS, /* segment */ - BOARD_ACCEL_GYRO_I2C_ADDR, /* bus */ - BOARD_ACCEL_GYRO_IRQ_TYPE, /* device */ - 0); /* function */ - - return len; + mainboard_ec_init(); } // mainboard_enable is executed as first thing after @@ -108,7 +49,6 @@ static int mainboard_smbios_data(device_t dev, int *handle, static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; - dev->ops->get_smbios_data = mainboard_smbios_data; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/samus/onboard.h b/src/mainboard/google/samus/onboard.h deleted file mode 100644 index d47d3c9..0000000 --- a/src/mainboard/google/samus/onboard.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef ONBOARD_H -#define ONBOARD_H - -#define BOARD_PIRQ_INTERRUPT 0 -#define BOARD_GPIO_INTERRUPT 1 -#define BOARD_GPIO_OFFSET 162 -#define GPIO_INTERRUPT(x) (BOARD_GPIO_OFFSET + (x)) - -#define BOARD_TRACKPAD_NAME "trackpad" -#define BOARD_TRACKPAD_IRQ 27 /* PIRQL */ -#define BOARD_TRACKPAD_IRQ_TYPE BOARD_PIRQ_INTERRUPT -#define BOARD_TRACKPAD_WAKE_GPIO 13 /* GPIO13 */ -#define BOARD_TRACKPAD_I2C_BUS 1 /* I2C0 */ -#define BOARD_TRACKPAD_I2C_ADDR 0x4b - -#define BOARD_TOUCHSCREEN_NAME "touchscreen" -#define BOARD_TOUCHSCREEN_IRQ 28 /* PIRQM */ -#define BOARD_TOUCHSCREEN_IRQ_TYPE BOARD_PIRQ_INTERRUPT -#define BOARD_TOUCHSCREEN_WAKE_GPIO 14 /* GPIO14 */ -#define BOARD_TOUCHSCREEN_I2C_BUS 2 /* I2C1 */ -#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4b - -#define BOARD_CODEC_NAME "codec" -#define BOARD_CODEC_IRQ 30 /* PIRQO */ -#define BOARD_CODEC_IRQ_TYPE BOARD_PIRQ_INTERRUPT -#define BOARD_CODEC_WAKE_GPIO 46 /* GPIO46 */ -#define BOARD_CODEC_I2C_BUS 1 /* I2C0 */ -#define BOARD_CODEC_I2C_ADDR 0x1a - -#define BOARD_NFC_NAME "nfc" -#define BOARD_NFC_IRQ GPIO_INTERRUPT(9) -#define BOARD_NFC_IRQ_TYPE BOARD_GPIO_INTERRUPT -#define BOARD_NFC_WAKE_GPIO 9 /* GPIO9 */ -#define BOARD_NFC_I2C_BUS 1 /* I2C0 */ -#define BOARD_NFC_I2C_ADDR 0x28 - -#define BOARD_ACCEL_NAME "accel" -#define BOARD_ACCEL_IRQ 29 /* PIRQN */ -#define BOARD_ACCEL_IRQ_TYPE BOARD_PIRQ_INTERRUPT -#define BOARD_ACCEL_WAKE_GPIO 45 /* GPIO45 */ -#define BOARD_ACCEL_I2C_BUS 2 /* I2C1 */ -#define BOARD_ACCEL_I2C_ADDR 0x0e - -#define BOARD_ACCEL_GYRO_NAME "accel_gyro" -#define BOARD_ACCEL_GYRO_IRQ 31 /* PIRQP */ -#define BOARD_ACCEL_GYRO_IRQ_TYPE BOARD_PIRQ_INTERRUPT -#define BOARD_ACCEL_GYRO_WAKE_GPIO 47 /* GPIO47 */ -#define BOARD_ACCEL_GYRO_I2C_BUS 2 /* I2C1 */ -#define BOARD_ACCEL_GYRO_I2C_ADDR 0x6b - -#endif diff --git a/src/mainboard/google/samus/pei_data.c b/src/mainboard/google/samus/pei_data.c index c4e9c0b..04b86e0 100644 --- a/src/mainboard/google/samus/pei_data.c +++ b/src/mainboard/google/samus/pei_data.c @@ -51,15 +51,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* P1: HOST PORT */ pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1, USB_PORT_BACK_PANEL); - /* P2: EMPTY */ - pei_data_usb2_port(pei_data, 2, 0x0000, 0, USB_OC_PIN_SKIP, - USB_PORT_SKIP); + /* P2: RAIDEN */ + pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); /* P3: SD CARD */ - pei_data_usb2_port(pei_data, 3, 0x0040, 0, USB_OC_PIN_SKIP, + pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); - /* P4: EMPTY */ - pei_data_usb2_port(pei_data, 4, 0x0000, 0, USB_OC_PIN_SKIP, - USB_PORT_SKIP); + /* P4: RAIDEN */ + pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); /* P5: WWAN */ pei_data_usb2_port(pei_data, 5, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); @@ -74,8 +74,8 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) pei_data_usb3_port(pei_data, 0, 1, 0, 0); /* P2: HOST PORT */ pei_data_usb3_port(pei_data, 1, 1, 1, 0); - /* P3: EMPTY */ - pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0); - /* P4: SD CARD */ - pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0); + /* P3: RAIDEN */ + pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); + /* P4: RAIDEN */ + pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); } diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c index 9af4ffb..9594287 100644 --- a/src/mainboard/google/samus/romstage.c +++ b/src/mainboard/google/samus/romstage.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,12 +22,13 @@ #include <console/console.h> #include <string.h> #include <ec/google/chromeec/ec.h> +#include <broadwell/cpu.h> //#include <broadwell/gpio.h> #include <broadwell/pei_data.h> #include <broadwell/pei_wrapper.h> #include <broadwell/romstage.h> #include <mainboard/google/samus/spd/spd.h> -#include "gpio.h" +#include <mainboard/google/samus/gpio.h> void mainboard_romstage_entry(struct romstage_params *rp) { @@ -35,6 +36,9 @@ void mainboard_romstage_entry(struct romstage_params *rp) post_code(0x32); + printk(BIOS_INFO, "MLB: board version %d\n", + google_chromeec_get_board_version()); + /* Ensure the EC is in the right mode for recovery */ google_chromeec_early_init(); @@ -47,6 +51,16 @@ void mainboard_romstage_entry(struct romstage_params *rp) mainboard_fill_spd_data(&pei_data); rp->pei_data = &pei_data; + /* + * http://crosbug.com/p/29117 + * Limit Broadwell SKU to 1333MHz and disable channel 1 + */ + if (cpu_family_model() == BROADWELL_FAMILY_ULT) { + pei_data.max_ddr3_freq = 1333; + pei_data.dimm_channel1_disabled = 3; + memset(pei_data.spd_data[1][0], 0, SPD_LEN); + } + romstage_common(rp); /* diff --git a/src/mainboard/google/samus/spd/Makefile.inc b/src/mainboard/google/samus/spd/Makefile.inc index 657a09d..ccce912 100644 --- a/src/mainboard/google/samus/spd/Makefile.inc +++ b/src/mainboard/google/samus/spd/Makefile.inc @@ -21,15 +21,23 @@ romstage-y += spd.c SPD_BIN = $(obj)/spd.bin -# { GPIO69, GPIO68, GPIO67 } -SPD_SOURCES = empty # 0: { 0, 0, 0 } -SPD_SOURCES += elpida_4Gb # 1: { 0, 0, 1 } -SPD_SOURCES += empty # 2: { 0, 1, 0 } -SPD_SOURCES += elpida_8Gb # 3: { 0, 1, 1 } -SPD_SOURCES += empty # 4: { 1, 0, 0 } -SPD_SOURCES += samsung_8Gb # 5: { 1, 0, 1 } -SPD_SOURCES += samsung_4Gb # 6: { 1, 1, 0 } -SPD_SOURCES += empty # 7: { 1, 1, 1 } +# { GPIO66, GPIO69, GPIO68, GPIO67 } +SPD_SOURCES = empty # 0b0000 +SPD_SOURCES += empty # 0b0001 +SPD_SOURCES += empty # 0b0010 +SPD_SOURCES += empty # 0b0011 +SPD_SOURCES += empty # 0b0100 +SPD_SOURCES += empty # 0b0101 +SPD_SOURCES += samsung_4Gb # 0b0110 +SPD_SOURCES += empty # 0b0111 +SPD_SOURCES += hynix_4Gb # 0b1000 +SPD_SOURCES += empty # 0b1001 +SPD_SOURCES += samsung_8Gb # 0b1010 +SPD_SOURCES += empty # 0b1011 +SPD_SOURCES += hynix_8Gb # 0b1100 +SPD_SOURCES += empty # 0b1101 +SPD_SOURCES += empty # 0b1110 +SPD_SOURCES += empty # 0b1111 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/samus/spd/hynix_4Gb.spd.hex b/src/mainboard/google/samus/spd/hynix_4Gb.spd.hex new file mode 100644 index 0000000..c63c303 --- /dev/null +++ b/src/mainboard/google/samus/spd/hynix_4Gb.spd.hex @@ -0,0 +1,18 @@ +# Hynix H9CCNNNBLTMLAR-NTM LPDDR3-S8B 8Gb(x32, 2CS) +# banks 8, ranks 2, rows 14, columns 10, density 4096 Mb, x32 +92 11 F1 03 04 11 02 0B 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 00 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E +54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex b/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex new file mode 100644 index 0000000..14002c1 --- /dev/null +++ b/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex @@ -0,0 +1,18 @@ +# Hynix H9CCNNN8JTMLAR-NTM LPDDR3-S8B 16Gb(x32, 2CS) +# banks 8, ranks 2, rows 15, columns 10, density 8192 Mb, x32 +92 11 F1 03 05 19 02 0B 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 00 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 38 4A 54 4D 4C 41 52 2D 4E +54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/spd.c b/src/mainboard/google/samus/spd/spd.c index 331fc6d..0409302 100644 --- a/src/mainboard/google/samus/spd/spd.c +++ b/src/mainboard/google/samus/spd/spd.c @@ -80,7 +80,7 @@ static void mainboard_print_spd_info(uint8_t spd[]) /* Copy SPD data for on-board memory */ void mainboard_fill_spd_data(struct pei_data *pei_data) { - int spd_gpio[3]; + int spd_gpio[4]; int spd_index; int spd_file_len; struct cbfs_file *spd_file; @@ -88,11 +88,14 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) spd_gpio[0] = get_gpio(SPD_GPIO_BIT0); spd_gpio[1] = get_gpio(SPD_GPIO_BIT1); spd_gpio[2] = get_gpio(SPD_GPIO_BIT2); + spd_gpio[3] = get_gpio(SPD_GPIO_BIT3); - spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0]; + spd_index = (spd_gpio[3] << 3) | (spd_gpio[2] << 2) | + (spd_gpio[1] << 1) | spd_gpio[0]; - printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n", - spd_index, + printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d " + "GPIO%d=%d GPIO%d=%d)\n", spd_index, + SPD_GPIO_BIT3, spd_gpio[3], SPD_GPIO_BIT2, spd_gpio[2], SPD_GPIO_BIT1, spd_gpio[1], SPD_GPIO_BIT0, spd_gpio[0]); diff --git a/src/mainboard/google/samus/spd/spd.h b/src/mainboard/google/samus/spd/spd.h index 98180fa..77540af 100644 --- a/src/mainboard/google/samus/spd/spd.h +++ b/src/mainboard/google/samus/spd/spd.h @@ -36,6 +36,7 @@ #define SPD_GPIO_BIT0 67 #define SPD_GPIO_BIT1 68 #define SPD_GPIO_BIT2 69 +#define SPD_GPIO_BIT3 66 struct pei_data; void mainboard_fill_spd_data(struct pei_data *pei_data);

1 0

New patch to review for coreboot: 6ec5990 samus: Move SPD related information to spd directory
by Marc Jones 31 Dec '14

31 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8006 -gerrit commit 6ec5990ea97704034ba0655ebb2823103c48ad4e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu May 22 08:22:51 2014 -0700 samus: Move SPD related information to spd directory Put all the SPD related information in one place including the onboard SPD sources and the board specific parsing. BUG=chrome-os-partner:28234 TEST=Build and boot on samus Original-Change-Id: If5cd826ecc9cc856008b7c29aa3cfade5ae7f685 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201082 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit f40e447cee84ebd04ab8a57250d0f56f508d52f2) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I9c10b08c3e640642e3c75696a233051bb34a2123 --- src/mainboard/google/samus/Makefile.inc | 31 +----- src/mainboard/google/samus/elpida_4Gb.spd.hex | 16 --- src/mainboard/google/samus/elpida_8Gb.spd.hex | 16 --- src/mainboard/google/samus/empty.spd.hex | 16 --- src/mainboard/google/samus/romstage.c | 2 +- src/mainboard/google/samus/samsung_4Gb.spd.hex | 16 --- src/mainboard/google/samus/samsung_8Gb.spd.hex | 16 --- src/mainboard/google/samus/spd.c | 121 --------------------- src/mainboard/google/samus/spd.h | 43 -------- src/mainboard/google/samus/spd/Makefile.inc | 46 ++++++++ src/mainboard/google/samus/spd/elpida_4Gb.spd.hex | 16 +++ src/mainboard/google/samus/spd/elpida_8Gb.spd.hex | 16 +++ src/mainboard/google/samus/spd/empty.spd.hex | 16 +++ src/mainboard/google/samus/spd/samsung_4Gb.spd.hex | 16 +++ src/mainboard/google/samus/spd/samsung_8Gb.spd.hex | 16 +++ src/mainboard/google/samus/spd/spd.c | 121 +++++++++++++++++++++ src/mainboard/google/samus/spd/spd.h | 43 ++++++++ 17 files changed, 293 insertions(+), 274 deletions(-) diff --git a/src/mainboard/google/samus/Makefile.inc b/src/mainboard/google/samus/Makefile.inc index f23352f..502204e 100644 --- a/src/mainboard/google/samus/Makefile.inc +++ b/src/mainboard/google/samus/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +subdirs-y += spd + ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c romstage-y += chromeos.c @@ -26,32 +28,3 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += pei_data.c ramstage-y += pei_data.c - -## DIMM SPD for on-board memory -romstage-y += spd.c -SPD_BIN = $(obj)/spd.bin - -# Order of names in SPD_SOURCES is important! -# { GPIO69, GPIO68, GPIO67 } -SPD_SOURCES = empty # 0: { 0, 0, 0 } -SPD_SOURCES += elpida_4Gb # 1: { 0, 0, 1 } -SPD_SOURCES += empty # 2: { 0, 1, 0 } -SPD_SOURCES += elpida_8Gb # 3: { 0, 1, 1 } -SPD_SOURCES += empty # 4: { 1, 0, 0 } -SPD_SOURCES += samsung_8Gb # 5: { 1, 0, 1 } -SPD_SOURCES += samsung_4Gb # 6: { 1, 1, 0 } -SPD_SOURCES += empty # 7: { 1, 1, 1 } - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do echo -e -n "\\x$$c"; \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := 0xab diff --git a/src/mainboard/google/samus/elpida_4Gb.spd.hex b/src/mainboard/google/samus/elpida_4Gb.spd.hex deleted file mode 100644 index e73ba62..0000000 --- a/src/mainboard/google/samus/elpida_4Gb.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -92 11 F1 03 04 11 02 0B 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 -45 44 46 38 31 33 32 41 33 4D 41 2D 47 44 2D 46 -20 20 32 2E 30 20 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/elpida_8Gb.spd.hex b/src/mainboard/google/samus/elpida_8Gb.spd.hex deleted file mode 100644 index b790943..0000000 --- a/src/mainboard/google/samus/elpida_8Gb.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -92 11 F1 03 04 12 02 0A 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 -45 44 46 41 32 33 32 41 32 4D 41 2D 47 44 2D 46 -20 20 32 2E 30 20 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/empty.spd.hex b/src/mainboard/google/samus/empty.spd.hex deleted file mode 100644 index 9ec39f1..0000000 --- a/src/mainboard/google/samus/empty.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c index f0609c8..9af4ffb 100644 --- a/src/mainboard/google/samus/romstage.c +++ b/src/mainboard/google/samus/romstage.c @@ -26,7 +26,7 @@ #include <broadwell/pei_data.h> #include <broadwell/pei_wrapper.h> #include <broadwell/romstage.h> -#include "spd.h" +#include <mainboard/google/samus/spd/spd.h> #include "gpio.h" void mainboard_romstage_entry(struct romstage_params *rp) diff --git a/src/mainboard/google/samus/samsung_4Gb.spd.hex b/src/mainboard/google/samus/samsung_4Gb.spd.hex deleted file mode 100644 index 8821050..0000000 --- a/src/mainboard/google/samus/samsung_4Gb.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -92 11 F1 03 04 11 02 0B 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 F0 0A 3C 3C 01 40 83 01 -00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 CE 01 00 00 00 00 00 00 00 00 -4B 34 45 38 45 33 30 34 45 44 2D 45 47 43 45 20 -20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/samsung_8Gb.spd.hex b/src/mainboard/google/samus/samsung_8Gb.spd.hex deleted file mode 100644 index a7a1409..0000000 --- a/src/mainboard/google/samus/samsung_8Gb.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -92 11 F1 03 04 12 02 0A 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 F0 0A 3C 3C 01 40 83 01 -00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 CE 01 00 00 00 00 00 00 00 00 -4B 34 45 36 45 33 30 34 45 44 2D 45 47 43 45 20 -20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd.c b/src/mainboard/google/samus/spd.c deleted file mode 100644 index 4371da9..0000000 --- a/src/mainboard/google/samus/spd.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/byteorder.h> -#include <cbfs.h> -#include <console/console.h> -#include <string.h> -#include <broadwell/gpio.h> -#include <broadwell/pei_data.h> -#include <broadwell/romstage.h> -#include "gpio.h" -#include "spd.h" - -static void mainboard_print_spd_info(uint8_t spd[]) -{ - const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; - const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; - const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; - const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; - const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; - const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; - - int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; - int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; - int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; - - /* Module type */ - printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: - printk(BIOS_INFO, "DDR3\n"); - break; - case SPD_DRAM_LPDDR3: - printk(BIOS_INFO, "LPDDR3\n"); - break; - default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); - break; - } - - /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; - printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); - - printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, " - "density %d Mb\n", banks, ranks, rows, cols, capmb); - printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", - devw, busw); - - if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { - /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ - printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", - capmb / 8 * busw / devw * ranks); - } -} - -/* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *pei_data) -{ - int spd_gpio[3]; - int spd_index; - int spd_file_len; - struct cbfs_file *spd_file; - - spd_gpio[0] = get_gpio(SPD_GPIO_BIT0); - spd_gpio[1] = get_gpio(SPD_GPIO_BIT1); - spd_gpio[2] = get_gpio(SPD_GPIO_BIT2); - - spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0]; - - printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n", - spd_index, - SPD_GPIO_BIT2, spd_gpio[2], - SPD_GPIO_BIT1, spd_gpio[1], - SPD_GPIO_BIT0, spd_gpio[0]); - - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); - if (!spd_file) - die("SPD data not found."); - spd_file_len = ntohl(spd_file->len); - - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } - - if (spd_file_len < SPD_LEN) - die("Missing SPD data."); - - /* Assume same memory in both channels */ - spd_index *= SPD_LEN; - memcpy(pei_data->spd_data[0][0], - ((char*)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN); - memcpy(pei_data->spd_data[1][0], - ((char*)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN); - - mainboard_print_spd_info(pei_data->spd_data[0][0]); -} diff --git a/src/mainboard/google/samus/spd.h b/src/mainboard/google/samus/spd.h deleted file mode 100644 index 98180fa..0000000 --- a/src/mainboard/google/samus/spd.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 - -/* Samus board memory configuration GPIOs */ -#define SPD_GPIO_BIT0 67 -#define SPD_GPIO_BIT1 68 -#define SPD_GPIO_BIT2 69 - -struct pei_data; -void mainboard_fill_spd_data(struct pei_data *pei_data); - -#endif diff --git a/src/mainboard/google/samus/spd/Makefile.inc b/src/mainboard/google/samus/spd/Makefile.inc new file mode 100644 index 0000000..657a09d --- /dev/null +++ b/src/mainboard/google/samus/spd/Makefile.inc @@ -0,0 +1,46 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-y += spd.c + +SPD_BIN = $(obj)/spd.bin + +# { GPIO69, GPIO68, GPIO67 } +SPD_SOURCES = empty # 0: { 0, 0, 0 } +SPD_SOURCES += elpida_4Gb # 1: { 0, 0, 1 } +SPD_SOURCES += empty # 2: { 0, 1, 0 } +SPD_SOURCES += elpida_8Gb # 3: { 0, 1, 1 } +SPD_SOURCES += empty # 4: { 1, 0, 0 } +SPD_SOURCES += samsung_8Gb # 5: { 1, 0, 1 } +SPD_SOURCES += samsung_4Gb # 6: { 1, 1, 0 } +SPD_SOURCES += empty # 7: { 1, 1, 1 } + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do echo -e -n "\\x$$c"; \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := 0xab diff --git a/src/mainboard/google/samus/spd/elpida_4Gb.spd.hex b/src/mainboard/google/samus/spd/elpida_4Gb.spd.hex new file mode 100644 index 0000000..e73ba62 --- /dev/null +++ b/src/mainboard/google/samus/spd/elpida_4Gb.spd.hex @@ -0,0 +1,16 @@ +92 11 F1 03 04 11 02 0B 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 +45 44 46 38 31 33 32 41 33 4D 41 2D 47 44 2D 46 +20 20 32 2E 30 20 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/elpida_8Gb.spd.hex b/src/mainboard/google/samus/spd/elpida_8Gb.spd.hex new file mode 100644 index 0000000..b790943 --- /dev/null +++ b/src/mainboard/google/samus/spd/elpida_8Gb.spd.hex @@ -0,0 +1,16 @@ +92 11 F1 03 04 12 02 0A 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 +45 44 46 41 32 33 32 41 32 4D 41 2D 47 44 2D 46 +20 20 32 2E 30 20 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/empty.spd.hex b/src/mainboard/google/samus/spd/empty.spd.hex new file mode 100644 index 0000000..9ec39f1 --- /dev/null +++ b/src/mainboard/google/samus/spd/empty.spd.hex @@ -0,0 +1,16 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/samsung_4Gb.spd.hex b/src/mainboard/google/samus/spd/samsung_4Gb.spd.hex new file mode 100644 index 0000000..8821050 --- /dev/null +++ b/src/mainboard/google/samus/spd/samsung_4Gb.spd.hex @@ -0,0 +1,16 @@ +92 11 F1 03 04 11 02 0B 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 F0 0A 3C 3C 01 40 83 01 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 00 00 00 00 00 00 +4B 34 45 38 45 33 30 34 45 44 2D 45 47 43 45 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/samsung_8Gb.spd.hex b/src/mainboard/google/samus/spd/samsung_8Gb.spd.hex new file mode 100644 index 0000000..a7a1409 --- /dev/null +++ b/src/mainboard/google/samus/spd/samsung_8Gb.spd.hex @@ -0,0 +1,16 @@ +92 11 F1 03 04 12 02 0A 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 F0 0A 3C 3C 01 40 83 01 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 00 00 00 00 00 00 +4B 34 45 36 45 33 30 34 45 44 2D 45 47 43 45 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/spd.c b/src/mainboard/google/samus/spd/spd.c new file mode 100644 index 0000000..331fc6d --- /dev/null +++ b/src/mainboard/google/samus/spd/spd.c @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <string.h> +#include <broadwell/gpio.h> +#include <broadwell/pei_data.h> +#include <broadwell/romstage.h> +#include <mainboard/google/samus/gpio.h> +#include <mainboard/google/samus/spd/spd.h> + +static void mainboard_print_spd_info(uint8_t spd[]) +{ + const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; + const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; + const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; + const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; + const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; + const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + char spd_name[SPD_PART_LEN+1] = { 0 }; + + int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; + int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; + int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; + int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; + int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; + int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; + + /* Module type */ + printk(BIOS_INFO, "SPD: module type is "); + switch (spd[SPD_DRAM_TYPE]) { + case SPD_DRAM_DDR3: + printk(BIOS_INFO, "DDR3\n"); + break; + case SPD_DRAM_LPDDR3: + printk(BIOS_INFO, "LPDDR3\n"); + break; + default: + printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); + break; + } + + /* Module Part Number */ + memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); + spd_name[SPD_PART_LEN] = 0; + printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); + + printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, " + "density %d Mb\n", banks, ranks, rows, cols, capmb); + printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", + devw, busw); + + if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { + /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ + printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", + capmb / 8 * busw / devw * ranks); + } +} + +/* Copy SPD data for on-board memory */ +void mainboard_fill_spd_data(struct pei_data *pei_data) +{ + int spd_gpio[3]; + int spd_index; + int spd_file_len; + struct cbfs_file *spd_file; + + spd_gpio[0] = get_gpio(SPD_GPIO_BIT0); + spd_gpio[1] = get_gpio(SPD_GPIO_BIT1); + spd_gpio[2] = get_gpio(SPD_GPIO_BIT2); + + spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0]; + + printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n", + spd_index, + SPD_GPIO_BIT2, spd_gpio[2], + SPD_GPIO_BIT1, spd_gpio[1], + SPD_GPIO_BIT0, spd_gpio[0]); + + spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + if (!spd_file) + die("SPD data not found."); + spd_file_len = ntohl(spd_file->len); + + if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + if (spd_file_len < SPD_LEN) + die("Missing SPD data."); + + /* Assume same memory in both channels */ + spd_index *= SPD_LEN; + memcpy(pei_data->spd_data[0][0], + ((char*)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN); + memcpy(pei_data->spd_data[1][0], + ((char*)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN); + + mainboard_print_spd_info(pei_data->spd_data[0][0]); +} diff --git a/src/mainboard/google/samus/spd/spd.h b/src/mainboard/google/samus/spd/spd.h new file mode 100644 index 0000000..98180fa --- /dev/null +++ b/src/mainboard/google/samus/spd/spd.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define SPD_LEN 256 + +#define SPD_DRAM_TYPE 2 +#define SPD_DRAM_DDR3 0x0b +#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DENSITY_BANKS 4 +#define SPD_ADDRESSING 5 +#define SPD_ORGANIZATION 7 +#define SPD_BUS_DEV_WIDTH 8 +#define SPD_PART_OFF 128 +#define SPD_PART_LEN 18 + +/* Samus board memory configuration GPIOs */ +#define SPD_GPIO_BIT0 67 +#define SPD_GPIO_BIT1 68 +#define SPD_GPIO_BIT2 69 + +struct pei_data; +void mainboard_fill_spd_data(struct pei_data *pei_data); + +#endif

1 0

New patch to review for coreboot: 98e9029 util/cbfstool: Fix byte-ordering for payload type field.
by Marc Jones 31 Dec '14

31 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8005 -gerrit commit 98e90292535a594f63f8cc72eb501ed2a367bb76 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Fri May 16 10:14:05 2014 +0800 util/cbfstool: Fix byte-ordering for payload type field. In https://chromium-review.googlesource.com/181272 the payload->type has been changed to big-endian (network ordering) but the cbfs_image is still parsing type as host ordering, which caused printing cbfs image verbosely (cbfstool imge print -v) would fail to find entry field and print numerous garbage output. Payload fields should be always parsed in big-endian (network ordering). BUG=none TEST=make; cbfstool image.bin print -v -v -v # see payloads correctly Original-Change-Id: If1ac355b8847fb54988069f694bd2f317ce49a1a Original-Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/200158 Original-Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> (cherry picked from commit 423f7dd28f8b071692d57401e144232d5ee2e479) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I5a4694e887c7ff48d8d0713bb5808c29256141a9 --- util/cbfstool/cbfs_image.c | 64 +++++++++++++++++++++++++++------------------- 1 file changed, 38 insertions(+), 26 deletions(-) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 1a522bd..6775b06 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -153,6 +153,22 @@ void cbfs_put_header(void *dest, const struct cbfs_header *header) xdr_be.put32(&outheader, header->architecture); } +static void cbfs_decode_payload_segment(struct cbfs_payload_segment *output, + struct cbfs_payload_segment *input) +{ + struct buffer seg = { + .data = (void *)input, + .size = sizeof(*input), + }; + output->type = xdr_be.get32(&seg); + output->compression = xdr_be.get32(&seg); + output->offset = xdr_be.get32(&seg); + output->load_addr = xdr_be.get64(&seg); + output->len = xdr_be.get32(&seg); + output->mem_len = xdr_be.get32(&seg); + assert(seg.size == 0); +} + void cbfs_get_header(struct cbfs_header *header, const void *src) { struct buffer outheader; @@ -596,40 +612,35 @@ static int cbfs_print_stage_info(struct cbfs_stage *stage, FILE* fp) return 0; } -/* Return 1 when segment is of type PAYLOAD_SEGMENT_ENTRY. */ -static int cbfs_print_payload_segment_info(struct cbfs_payload_segment *seg_be, - FILE *fp) +static int cbfs_print_decoded_payload_segment_info( + struct cbfs_payload_segment *seg, FILE *fp) { - struct cbfs_payload_segment payload; - - xdr_get_seg(&payload, seg_be); - - switch(payload.type) { + /* The input (seg) must be already decoded by + * cbfs_decode_payload_segment. + */ + switch (seg->type) { case PAYLOAD_SEGMENT_CODE: case PAYLOAD_SEGMENT_DATA: fprintf(fp, " %s (%s compression, offset: 0x%x, " "load: 0x%" PRIx64 ", length: %d/%d)\n", - (payload.type == PAYLOAD_SEGMENT_CODE ? + (seg->type == PAYLOAD_SEGMENT_CODE ? "code " : "data"), lookup_name_by_type(types_cbfs_compression, - payload.compression, + seg->compression, "(unknown)"), - payload.offset, - payload.load_addr, - payload.len, payload.mem_len); + seg->offset, seg->load_addr, seg->len, + seg->mem_len); break; case PAYLOAD_SEGMENT_ENTRY: fprintf(fp, " entry (0x%" PRIx64 ")\n", - payload.load_addr); - return 1; + seg->load_addr); break; case PAYLOAD_SEGMENT_BSS: fprintf(fp, " BSS (address 0x%016" PRIx64 ", " "length 0x%x)\n", - payload.load_addr, - payload.len); + seg->load_addr, seg->len); break; case PAYLOAD_SEGMENT_PARAMS: @@ -639,14 +650,12 @@ static int cbfs_print_payload_segment_info(struct cbfs_payload_segment *seg_be, default: fprintf(fp, " 0x%x (%s compression, offset: 0x%x, " "load: 0x%" PRIx64 ", length: %d/%d\n", - payload.type, + seg->type, lookup_name_by_type(types_cbfs_compression, - payload.compression, + seg->compression, "(unknown)"), - payload.offset, - payload.load_addr, - payload.len, - payload.mem_len); + seg->offset, seg->load_addr, seg->len, + seg->mem_len); break; } return 0; @@ -692,10 +701,13 @@ int cbfs_print_entry_info(struct cbfs_image *image, struct cbfs_file *entry, payload = (struct cbfs_payload_segment *) CBFS_SUBHEADER(entry); while (payload) { - /* Stop when PAYLOAD_SEGMENT_ENTRY seen. */ - if (cbfs_print_payload_segment_info(payload, - fp)) + struct cbfs_payload_segment seg; + cbfs_decode_payload_segment(&seg, payload); + cbfs_print_decoded_payload_segment_info( + &seg, fp); + if (seg.type == PAYLOAD_SEGMENT_ENTRY) break; + else payload ++; } break;

1 0

New patch to review for coreboot: cd28a58 ipq8064: work around for slow timer clock
by Marc Jones 31 Dec '14

31 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8004 -gerrit commit cd28a5861897325b5852de5cd2fc64210595d523 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri May 23 14:18:35 2014 -0700 ipq8064: work around for slow timer clock Libpayload libc requires timer clock frequency to be at least 1MHz. Ipq8064 code presently provides a single option of 32kHz. Pretend to be running at 1 MHz without additional accuracy. This is a hack which will be reverted as soon as the SOC is configured to supply a faster running clock. BUG=chrome-os-partner:27784, chrome-os-partner:28880 TEST=with other changes depthcharge boots to the CLI console Original-Change-Id: I80ec6652bc5693a549668cd6e824e9cf5c26b182 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201342 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 466a59967b13986099106f8b44924648c1e6e6cd) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I113689191db70710e7a45ccd02d672f482343e35 --- payloads/libpayload/drivers/timer/ipq806x.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/timer/ipq806x.c b/payloads/libpayload/drivers/timer/ipq806x.c index 4edbf8e..0d70a86 100644 --- a/payloads/libpayload/drivers/timer/ipq806x.c +++ b/payloads/libpayload/drivers/timer/ipq806x.c @@ -29,13 +29,31 @@ #include <libpayload.h> +/* + * TODO(vbendeb): reverted this hack once proper timer code is in place (see + * http://crosbug.com/p/28880 for details. + */ +#define MIN_TIMER_FREQ 1000000 + uint64_t timer_hz(void) { - return CONFIG_LP_IPQ806X_TIMER_FREQ; + return (CONFIG_LP_IPQ806X_TIMER_FREQ >= MIN_TIMER_FREQ) ? + CONFIG_LP_IPQ806X_TIMER_FREQ : MIN_TIMER_FREQ; } uint64_t timer_raw_value(void) { - return readl((void *)CONFIG_LP_IPQ806X_TIMER_REG); + uint64_t rawv = readl((void *)CONFIG_LP_IPQ806X_TIMER_REG); + + /* + * This is extremely crude, but it kicks in only for the case when the + * timer clock frequency is below 1MHz, which should never be the case + * on a properly configured system. The compiler will eliminate the + * check as long as config value exceeds 1MHz. + */ + if (CONFIG_LP_IPQ806X_TIMER_FREQ < MIN_TIMER_FREQ) + rawv *= (MIN_TIMER_FREQ / CONFIG_LP_IPQ806X_TIMER_FREQ); + + return rawv; }

1 0

New patch to review for coreboot: 1b9b270 libpayload: Provide selfboot() external declaration in a common file
by Marc Jones 31 Dec '14

31 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8003 -gerrit commit 1b9b270792a89ca72286da8721feb0e40c7eafce Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri May 23 14:37:10 2014 -0700 libpayload: Provide selfboot() external declaration in a common file The earlier compilation warning fix (7e4aa17) incorrectly assumed that selfboot() is a function defined in the cbfs driver. This is a commonly available function, it should not come from cbfs.h. BUG=none TEST=the following build command succeeds: rambi storm nyan_big Original-Change-Id: I3ef49d849168ad9dc24589cbd9ce7382052345bd Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201386 (cherry picked from commit d5090e8410530f41b9fd33e2caa1d8aa25438105) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I8404fb52112b391982f954a6d06fe4b451dfcb8a --- payloads/libpayload/include/cbfs.h | 3 --- payloads/libpayload/include/libpayload.h | 6 +++--- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/payloads/libpayload/include/cbfs.h b/payloads/libpayload/include/cbfs.h index c5c811c..1b5c51a 100644 --- a/payloads/libpayload/include/cbfs.h +++ b/payloads/libpayload/include/cbfs.h @@ -81,9 +81,6 @@ void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, // Utility functions int run_address(void *f); -/* Defined in src/lib/selfboot.c */ -void selfboot(void *entry); - /* Defined in individual arch / board implementation. */ int init_default_cbfs_media(struct cbfs_media *media); diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 1d4d0da..9781c9e 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -60,9 +60,6 @@ #ifdef CONFIG_LP_LAR #include <lar.h> #endif -#ifdef CONFIG_LP_CBFS -#include <cbfs.h> -#endif #define MIN(a,b) ((a) < (b) ? (a) : (b)) #define MAX(a,b) ((a) > (b) ? (a) : (b)) @@ -445,4 +442,7 @@ char *readline(const char *prompt); int getline(char *buffer, int len); /** @} */ +/* Defined in arch/${ARCH}/selfboot.c */ +void selfboot(void *entry); + #endif

1 0

New patch to review for coreboot: 0d1767c libpayload: ipq8064: Add rudimentary timer driver
by Marc Jones 31 Dec '14

31 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8002 -gerrit commit 0d1767c75ba0b8d30742f0f95c93082eaffeae16 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed May 21 16:28:57 2014 -0700 libpayload: ipq8064: Add rudimentary timer driver This is still using the 32kHz timer coreboot uses. A finer granularity timer implementation for 806x is in the works. BUG=chrome-os-partner:27784,chrome-os-partner:28880 TEST=none yet. Original-Change-Id: Iae206749000d45040090df48199c8d86d76bbae5 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/198021 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 8f49f752ab8f84b7c5dc189238732360e8d2aae2) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ia150c974e5b66939de0b007cf7c1308c187f3289 --- payloads/libpayload/Config.in | 18 +++++++++++++ payloads/libpayload/drivers/Makefile.inc | 1 + payloads/libpayload/drivers/timer/ipq806x.c | 41 +++++++++++++++++++++++++++++ 3 files changed, 60 insertions(+) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index bef0e05..3c5c342 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -354,6 +354,9 @@ config TIMER_MCT config TIMER_TEGRA_1US bool "Tegra 1us" +config TIMER_IPQ806X + bool "Timer for ipq806x platforms" + endchoice config TIMER_MCT_HZ @@ -371,6 +374,21 @@ config TIMER_TEGRA_1US_ADDRESS depends on TIMER_TEGRA_1US default 0x60005010 +config IPQ806X_TIMER_FREQ + int "Hardware timer frequency" + default 32000 + depends on TIMER_IPQ806X + help + IPQ hardware presently provides a single timer running at 32KHz, a + finer granulariry timer is available but is not yet enabled. + +config IPQ806X_TIMER_REG + hex "Timer register address" + default 0x0200A008 + depends on TIMER_IPQ806X + help + Address of the register to read a free running timer value. + config USB bool "USB Support" default n diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index 7212389..d46bb11 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -48,6 +48,7 @@ libc-$(CONFIG_LP_NVRAM) += options.c libc-$(CONFIG_LP_TIMER_MCT) += timer/mct.c libc-$(CONFIG_LP_TIMER_RDTSC) += timer/rdtsc.c libc-$(CONFIG_LP_TIMER_TEGRA_1US) += timer/tegra_1us.c +libc-$(CONFIG_LP_TIMER_IPQ806X) += timer/ipq806x.c # Video console drivers libc-$(CONFIG_LP_VIDEO_CONSOLE) += video/video.c diff --git a/payloads/libpayload/drivers/timer/ipq806x.c b/payloads/libpayload/drivers/timer/ipq806x.c new file mode 100644 index 0000000..4edbf8e --- /dev/null +++ b/payloads/libpayload/drivers/timer/ipq806x.c @@ -0,0 +1,41 @@ +/* + * This file is part of the depthcharge project. + * + * Copyright (C) 2014 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload.h> + +uint64_t timer_hz(void) +{ + return CONFIG_LP_IPQ806X_TIMER_FREQ; +} + +uint64_t timer_raw_value(void) +{ + return readl((void *)CONFIG_LP_IPQ806X_TIMER_REG); +} +

1 0

Patch set updated for coreboot: 88d947a bpayload: Do not tolerate compilation warnings when building
by Marc Jones 31 Dec '14

31 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7911 -gerrit commit 88d947a8e5b28b3af3906d13d81514486ddfff8c Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu May 15 14:12:54 2014 -0700 bpayload: Do not tolerate compilation warnings when building Make sure the build breaks in case of warnings. BUG=none TEST= All builds succeed with the restored patch and fail when a compilation warning is thrown. Original-Change-Id: I9bdcd8938f59913e4ba86df5e4921b3f821ef920 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/200110 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 16dde875950d6806cc770cdbee4d3ff456ed6f02) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I86988f8d3f1acaa6ceeabdcbfa3cede1e67c28fe --- payloads/libpayload/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index ffe8371..dd83f88 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -57,7 +57,7 @@ CFLAGS = $(EXTRA_CFLAGS) $(INCLUDES) -Os -pipe -nostdinc -ggdb3 CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -CFLAGS += -Wstrict-aliasing -Wshadow +CFLAGS += -Wstrict-aliasing -Wshadow -Werror $(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER) cmp $@ $< 2>/dev/null || cp $< $@

1 0

Patch set updated for coreboot: 71e1b29 libpayload: Fix pointer related casts
by Marc Jones 31 Dec '14

31 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7905 -gerrit commit 71e1b2957895b9afb82caacd99b4594bcebb40cf Author: Furquan Shaikh <furquan(a)google.com> Date: Tue May 13 13:47:32 2014 -0700 libpayload: Fix pointer related casts Fix pointer related casts since this can create a problem for 64-bit systems. BUG=None BRANCH=None TEST=Compiled successfully for link, nyan using emerge-* libpayload Original-Change-Id: I4cbd2d9f1efaaac87c3eba69204337fd6893ed66 Original-Reviewed-on: https://chromium-review.googlesource.com/199564 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 914b118a64b0691aeca463dff24252db9c24109e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I11f070ed5d3eddd8b9be30c428cb24c8439e617b --- payloads/libpayload/drivers/usb/xhci.c | 2 +- payloads/libpayload/include/usb/usb.h | 3 ++- payloads/libpayload/libc/malloc.c | 9 +++++---- payloads/libpayload/libcbfs/cbfs.c | 11 +++++------ 4 files changed, 13 insertions(+), 12 deletions(-) diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 714c9ce..33009bc 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -168,7 +168,7 @@ xhci_init (unsigned long physical_bar) controller->poll_intr_queue = xhci_poll_intr_queue; controller->pcidev = 0; - controller->reg_base = (u32)physical_bar; + controller->reg_base = (uintptr_t)physical_bar; controller->instance = xzalloc(sizeof(xhci_t)); xhci_t *const xhci = (xhci_t *)controller->instance; diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h index ec9912a..4d8b2c2 100644 --- a/payloads/libpayload/include/usb/usb.h +++ b/payloads/libpayload/include/usb/usb.h @@ -31,6 +31,7 @@ #define __USB_H #include <libpayload.h> #include <pci/pci.h> +#include <stdint.h> typedef enum { host_to_device = 0, device_to_host = 1 } dev_req_dir; typedef enum { standard_type = 0, class_type = 1, vendor_type = @@ -210,7 +211,7 @@ typedef enum { OHCI = 0, UHCI = 1, EHCI = 2, XHCI = 3} hc_type; struct usbdev_hc { hci_t *next; - u32 reg_base; + uintptr_t reg_base; pcidev_t pcidev; // 0 if not used (eg on ARM) hc_type type; int latest_address; diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c index 0f2845d..1d99a9c 100644 --- a/payloads/libpayload/libc/malloc.c +++ b/payloads/libpayload/libc/malloc.c @@ -41,6 +41,7 @@ #define IN_MALLOC_C #include <libpayload.h> +#include <stdint.h> struct memory_type { void *start; @@ -158,7 +159,7 @@ static void *alloc(int len, struct memory_type *type) if (header & FLAG_FREE) { if (len <= size) { - hdrtype_t volatile *nptr = (hdrtype_t volatile *)((int)ptr + HDRSIZE + len); + hdrtype_t volatile *nptr = (hdrtype_t volatile *)((uintptr_t)ptr + HDRSIZE + len); int nsize = size - (HDRSIZE + len); /* If there is still room in this block, @@ -177,11 +178,11 @@ static void *alloc(int len, struct memory_type *type) *ptr = USED_BLOCK(size); } - return (void *)((int)ptr + HDRSIZE); + return (void *)((uintptr_t)ptr + HDRSIZE); } } - ptr = (hdrtype_t volatile *)((int)ptr + HDRSIZE + size); + ptr = (hdrtype_t volatile *)((uintptr_t)ptr + HDRSIZE + size); } while (ptr < (hdrtype_t *) type->end); @@ -353,7 +354,7 @@ static struct align_region_t *allocate_region(int alignment, int num_elements, s free(new_region); return NULL; } - new_region->start_data = (void*)((u32)(new_region->start + num_elements + alignment - 1) & (~(alignment-1))); + new_region->start_data = (void*)((uintptr_t)(new_region->start + num_elements + alignment - 1) & (~(alignment-1))); new_region->size = num_elements * alignment; new_region->free = num_elements; new_region->next = type->align_regions; diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c index 5610555..5ab7ffa 100644 --- a/payloads/libpayload/libcbfs/cbfs.c +++ b/payloads/libpayload/libcbfs/cbfs.c @@ -135,21 +135,21 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL); /* this is a mess. There is no ntohll. */ /* for now, assume compatible byte order until we solve this. */ - uint32_t entry; + uintptr_t entry; uint32_t final_size; if (stage == NULL) return (void *) -1; - LOG("loading stage %s @ 0x%x (%d bytes), entry @ 0x%llx\n", + LOG("loading stage %s @ 0x%p (%d bytes), entry @ 0x%llx\n", name, - (uint32_t) stage->load, stage->memlen, + (void*)(uintptr_t) stage->load, stage->memlen, stage->entry); final_size = cbfs_decompress(stage->compression, ((unsigned char *) stage) + sizeof(struct cbfs_stage), - (void *) (uint32_t) stage->load, + (void *) (uintptr_t) stage->load, stage->len); if (!final_size) return (void *) -1; @@ -179,8 +179,7 @@ int cbfs_execute_stage(struct cbfs_media *media, const char *name) return 1; } - /* FIXME: This isn't right */ - LOG("run @ %p\n", (void *) ntohl((uint32_t) stage->entry)); + LOG("run @ %p\n", (void *) (uintptr_t)ntohll(stage->entry)); return run_address((void *)(uintptr_t)ntohll(stage->entry)); }

1 0

← Newer
1
2
3
4
5
6
7
8
...
135
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2014