coreboot-gerrit December 2014

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Patch set updated for coreboot: 309d305 rtc: Add an RTC driver for the AS3722 PMIC.
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7890 -gerrit commit 309d3050d389576e51836c88d389957cade27a34 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Apr 30 21:37:14 2014 -0700 rtc: Add an RTC driver for the AS3722 PMIC. The AS3722 PMIC, like many PMICs, has an RTC built into it. This change adds a driver for it which implements the new RTC API. BUG=None TEST=Built and booted with the event log code modified to use this interface. Verified that events had accurate timestamps. BRANCH=nyan Original-Change-Id: I400adccbf84221dcba8d520276bb91b389f72268 Original-Signed-off-by: Gabe Black <gabeblack(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197796 Original-Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Original-Tested-by: Gabe Black <gabeblack(a)chromium.org> Original-Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 011e49beba3a99abbd122866891e3c20bf1188d2) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ibc1d342062c7853a30d195496c077e37a02b35b0 --- src/drivers/Kconfig | 1 + src/drivers/Makefile.inc | 1 + src/drivers/ams/Kconfig | 11 ++++++ src/drivers/ams/Makefile.inc | 1 + src/drivers/ams/as3722rtc.c | 91 ++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 105 insertions(+) diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index 12f9a79..08de415 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -17,6 +17,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +source src/drivers/ams/Kconfig source src/drivers/ati/Kconfig source src/drivers/dec/Kconfig source src/drivers/elog/Kconfig diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index 7ae3eb2..151e3f7 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -17,6 +17,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +subdirs-y += ams subdirs-y += ati subdirs-y += dec subdirs-y += emulation diff --git a/src/drivers/ams/Kconfig b/src/drivers/ams/Kconfig new file mode 100644 index 0000000..44b89c5 --- /dev/null +++ b/src/drivers/ams/Kconfig @@ -0,0 +1,11 @@ +config DRIVERS_AS3722_RTC + bool "AS3722 RTC support" + default n + +config DRIVERS_AS3722_RTC_BUS + int "AS3722 RTC bus" + depends on DRIVERS_AS3722_RTC + +config DRIVERS_AS3722_RTC_ADDR + hex "AS3722 RTC chip address" + depends on DRIVERS_AS3722_RTC diff --git a/src/drivers/ams/Makefile.inc b/src/drivers/ams/Makefile.inc new file mode 100644 index 0000000..cf51831 --- /dev/null +++ b/src/drivers/ams/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_AS3722_RTC) += as3722rtc.c diff --git a/src/drivers/ams/as3722rtc.c b/src/drivers/ams/as3722rtc.c new file mode 100644 index 0000000..8fe5748 --- /dev/null +++ b/src/drivers/ams/as3722rtc.c @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <bcd.h> +#include <console/console.h> +#include <device/i2c.h> +#include <rtc.h> +#include <stdint.h> + +enum AS3722_RTC_REG +{ + AS3722_RTC_CONTROL = 0x60, + AS3722_RTC_SECOND = 0x61, + AS3722_RTC_MINUTE = 0x62, + AS3722_RTC_HOUR = 0x63, + AS3722_RTC_DAY = 0x64, + AS3722_RTC_MONTH = 0x65, + AS3722_RTC_YEAR = 0x66 +}; + +enum { + AS3722_RTC_CONTROL_ON = 0x1 << 2 +}; + +static uint8_t as3722_read(enum AS3722_RTC_REG reg) +{ + uint8_t val; + i2c_readb(CONFIG_DRIVERS_AS3722_RTC_BUS, + CONFIG_DRIVERS_AS3722_RTC_ADDR, reg, &val); + return val; +} + +static void as3722_write(enum AS3722_RTC_REG reg, uint8_t val) +{ + i2c_writeb(CONFIG_DRIVERS_AS3722_RTC_BUS, + CONFIG_DRIVERS_AS3722_RTC_ADDR, reg, val); +} + +static void as3722rtc_init(void) +{ + static int initialized; + if (initialized) + return; + + uint8_t control = as3722_read(AS3722_RTC_CONTROL); + as3722_write(AS3722_RTC_CONTROL, control | AS3722_RTC_CONTROL_ON); + + initialized = 1; +} + +int rtc_set(const struct rtc_time *time) +{ + as3722rtc_init(); + + as3722_write(AS3722_RTC_SECOND, bin2bcd(time->sec)); + as3722_write(AS3722_RTC_MINUTE, bin2bcd(time->min)); + as3722_write(AS3722_RTC_HOUR, bin2bcd(time->hour)); + as3722_write(AS3722_RTC_DAY, bin2bcd(time->mday)); + as3722_write(AS3722_RTC_MONTH, bin2bcd(time->mon + 1)); + as3722_write(AS3722_RTC_YEAR, bin2bcd(time->year)); + return 0; +} + +int rtc_get(struct rtc_time *time) +{ + as3722rtc_init(); + + time->sec = bcd2bin(as3722_read(AS3722_RTC_SECOND) & 0x7f); + time->min = bcd2bin(as3722_read(AS3722_RTC_MINUTE) & 0x7f); + time->hour = bcd2bin(as3722_read(AS3722_RTC_HOUR) & 0x3f); + time->mday = bcd2bin(as3722_read(AS3722_RTC_DAY) & 0x3f); + time->mon = bcd2bin(as3722_read(AS3722_RTC_MONTH) & 0x1f) - 1; + time->year = bcd2bin(as3722_read(AS3722_RTC_YEAR) & 0x7f); + return 0; +}

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Patch set updated for coreboot: 618142d elog: Use the RTC driver interface instead of reading CMOS directly.
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7891 -gerrit commit 618142df46ffea5685b153368311b65f4d146960 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Apr 30 21:41:23 2014 -0700 elog: Use the RTC driver interface instead of reading CMOS directly. Use the RTC driver interface to find the timestamp for events instead of reading the CMOS based RTC directly on x86 or punting on ARM. This makes timestamps available on both architectures, assuming an RTC driver is available. BUG=None TEST=Built and booted on nyan_big and link and verified that the timestamps in the event log were accurate. BRANCH=nyan Original-Change-Id: Id45da53bc7ddfac8dd0978e7f2a3b8bc2c7ea753 Original-Signed-off-by: Gabe Black <gabeblack(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197798 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: Gabe Black <gabeblack(a)chromium.org> Original-Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 493b05e06dd461532c9366fb09025efb3568a975) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I4fad296ecfeff8987e4a18054661190239245f32 --- src/drivers/elog/elog.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 92d5af3..85198e2 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -25,6 +25,8 @@ #if CONFIG_ARCH_X86 #include <pc80/mc146818rtc.h> #endif +#include <bcd.h> +#include <rtc.h> #include <smbios.h> #include <spi-generic.h> #include <spi_flash.h> @@ -637,20 +639,15 @@ int elog_init(void) */ static void elog_fill_timestamp(struct event_header *event) { -#if CONFIG_ARCH_X86 - event->second = cmos_read(RTC_CLK_SECOND); - event->minute = cmos_read(RTC_CLK_MINUTE); - event->hour = cmos_read(RTC_CLK_HOUR); - event->day = cmos_read(RTC_CLK_DAYOFMONTH); - event->month = cmos_read(RTC_CLK_MONTH); - event->year = cmos_read(RTC_CLK_YEAR); -#else - /* - * FIXME: We need to abstract the CMOS stuff on non-x86 platforms. - * Until then, use bogus data here to force the values to 0. - */ - event->month = 0xff; -#endif + struct rtc_time time; + + rtc_get(&time); + event->second = bin2bcd(time.sec); + event->minute = bin2bcd(time.min); + event->hour = bin2bcd(time.hour); + event->day = bin2bcd(time.mday); + event->month = bin2bcd(time.mon); + event->year = bin2bcd(time.year) & 0xff; /* Basic sanity check of expected ranges */ if (event->month > 0x12 || event->day > 0x31 || event->hour > 0x23 ||

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Patch set updated for coreboot: 683b9d7 rtc: Add an RTC API, and implement it for x86.
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7889 -gerrit commit 683b9d739854f90d5e8b1c6ce3fdfa84668fc6ff Author: Marc Jones <marc.jones(a)se-eng.com> Date: Mon Dec 29 21:31:44 2014 -0700 rtc: Add an RTC API, and implement it for x86. This CL adds an API for RTC drivers, and implements its two functions, rtc_get and rtc_set, for x86's RTC. The function which resets the clock when the CMOS as lost state now uses the RTC driver instead of accessing the those registers directly. BUG=None TEST=Built and booted on Link with the event log code modified to use the RTC interface. Verified that the event times were accurate. BRANCH=nyan Original-Change-Id: Ifa807898e583254e57167fd44932ea86627a02ee Original-Signed-off-by: Gabe Black <gabeblack(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197795 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: Gabe Black <gabeblack(a)chromium.org> Original-Commit-Queue: Gabe Black <gabeblack(a)chromium.org> This is the first half of the patch. (cherry picked from commit 9e0fd75142d29afe34f6c6b9ce0099f478ca5a93) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I159f9b4872a0bb932961b4168b180c087dfb1883 --- src/drivers/pc80/Kconfig | 4 ++ src/drivers/pc80/Makefile.inc | 9 +++-- src/drivers/pc80/mc146818rtc.c | 87 ++++++++++++++++++++++++++++++++---------- src/include/bcd.h | 35 +++++++++++++++++ src/include/rtc.h | 37 ++++++++++++++++++ 5 files changed, 149 insertions(+), 23 deletions(-) diff --git a/src/drivers/pc80/Kconfig b/src/drivers/pc80/Kconfig index 5fad3a5..f8ac5c5 100644 --- a/src/drivers/pc80/Kconfig +++ b/src/drivers/pc80/Kconfig @@ -22,3 +22,7 @@ config LPC_TPM Enable this option to enable TPM support in coreboot. If unsure, say N. + +config DRIVERS_MC146818 + bool + default y if ARCH_X86 diff --git a/src/drivers/pc80/Makefile.inc b/src/drivers/pc80/Makefile.inc index fe6d11f..1d28152 100644 --- a/src/drivers/pc80/Makefile.inc +++ b/src/drivers/pc80/Makefile.inc @@ -1,5 +1,5 @@ -romstage-y += mc146818rtc.c -ramstage-y += mc146818rtc.c +romstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c +ramstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c ramstage-y += isa-dma.c ramstage-y += i8254.c ramstage-y += i8259.c @@ -7,7 +7,10 @@ ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c ramstage-y += keyboard.c ramstage-$(CONFIG_SPKMODEM) += spkmodem.c +ifeq ($(CONFIG_DRIVERS_MC146818),y) romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c +endif + romstage-$(CONFIG_LPC_TPM) += tpm.c romstage-$(CONFIG_SPKMODEM) += spkmodem.c @@ -17,4 +20,4 @@ cbfs-files-$(CONFIG_HAVE_CMOS_DEFAULT) += cmos.default cmos.default-file = $(CONFIG_CMOS_DEFAULT_FILE):nvramtool cmos.default-type = 0xaa -smm-y += mc146818rtc.c +smm-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index 014a8c9..84abd43 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -1,28 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <bcd.h> #include <stdint.h> #include <version.h> #include <console/console.h> #include <pc80/mc146818rtc.h> #include <boot/coreboot_tables.h> +#include <rtc.h> #include <string.h> #if CONFIG_USE_OPTION_TABLE #include "option_table.h" #include <cbfs.h> #endif -#include <arch/acpi.h> -static void cmos_update_date(u8 has_century) +static void cmos_reset_date(u8 has_century) { /* Now setup a default date equals to the build date */ - cmos_write(0, RTC_CLK_SECOND); - cmos_write(0, RTC_CLK_MINUTE); - cmos_write(1, RTC_CLK_HOUR); - cmos_write(coreboot_build_date.weekday + 1, RTC_CLK_DAYOFWEEK); - cmos_write(coreboot_build_date.day, RTC_CLK_DAYOFMONTH); - cmos_write(coreboot_build_date.month, RTC_CLK_MONTH); - cmos_write(coreboot_build_date.year, RTC_CLK_YEAR); - if (has_century) - cmos_write(coreboot_build_date.century, RTC_CLK_ALTCENTURY); + struct rtc_time time = { + .sec = 0, + .min = 0, + .hour = 1, + .mday = bcd2bin(coreboot_build_date.day), + .mon = bcd2bin(coreboot_build_date.month), + .year = (bcd2bin(coreboot_build_date.century) * 100) + + bcd2bin(coreboot_build_date.year), + .wday = bcd2bin(coreboot_build_date.weekday) + }; + rtc_set(&time, has_century); } #if CONFIG_USE_OPTION_TABLE @@ -50,15 +73,8 @@ static void cmos_set_checksum(int range_start, int range_end, int cks_loc) } #endif -#if CONFIG_ARCH_X86 #define RTC_CONTROL_DEFAULT (RTC_24H) #define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ) -#else -#if CONFIG_ARCH_ALPHA -#define RTC_CONTROL_DEFAULT (RTC_SQWE | RTC_24H) -#define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ) -#endif -#endif #ifndef __SMM__ void cmos_init(int invalid) @@ -107,7 +123,7 @@ void cmos_init(int invalid) cmos_write(0, i); #endif if (cmos_invalid) - cmos_update_date(RTC_HAS_NO_ALTCENTURY); + cmos_reset_date(RTC_HAS_NO_ALTCENTURY); printk(BIOS_WARNING, "RTC:%s%s%s%s\n", invalid?" Clear requested":"", @@ -323,5 +339,36 @@ void cmos_check_update_date(u8 has_century) * if the date is valid. */ if (century > 0x99 || year > 0x99) /* Invalid date */ - cmos_update_date(has_century); + cmos_reset_date(has_century); +} + +int rtc_set(const struct rtc_time *time, u8 has_century) +{ + cmos_write(bin2bcd(time->sec), RTC_CLK_SECOND); + cmos_write(bin2bcd(time->min), RTC_CLK_MINUTE); + cmos_write(bin2bcd(time->hour), RTC_CLK_HOUR); + cmos_write(bin2bcd(time->mday), RTC_CLK_DAYOFMONTH); + cmos_write(bin2bcd(time->mon), RTC_CLK_MONTH); + cmos_write(bin2bcd(time->year % 100), RTC_CLK_YEAR); + if (has_century) + cmos_write(bin2bcd(time->year / 100), + RTC_CLK_ALTCENTURY); + cmos_write(bin2bcd(time->wday + 1), RTC_CLK_DAYOFWEEK); + return 0; +} + +int rtc_get(struct rtc_time *time, u8 has_century) +{ + time->sec = bcd2bin(cmos_read(RTC_CLK_SECOND)); + time->min = bcd2bin(cmos_read(RTC_CLK_MINUTE)); + time->hour = bcd2bin(cmos_read(RTC_CLK_HOUR)); + time->mday = bcd2bin(cmos_read(RTC_CLK_DAYOFMONTH)); + time->mon = bcd2bin(cmos_read(RTC_CLK_MONTH)); + time->year = bcd2bin(cmos_read(RTC_CLK_YEAR)); + if (has_century) + time->year += bcd2bin(cmos_read(RTC_CLK_ALTCENTURY)) * 100; + else + time->year += 2000; + time->wday = bcd2bin(cmos_read(RTC_CLK_DAYOFWEEK)) - 1; + return 0; } diff --git a/src/include/bcd.h b/src/include/bcd.h new file mode 100644 index 0000000..a085027 --- /dev/null +++ b/src/include/bcd.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef _BCD_H_ +#define _BCD_H_ + +#include <stdint.h> + +static inline uint8_t bcd2bin(uint8_t val) +{ + return ((val >> 4) & 0xf) * 10 + (val & 0xf); +} + +static inline uint8_t bin2bcd(uint8_t val) +{ + return ((val / 10) << 4) | (val % 10); +} + +#endif /* _BCD_H_ */ diff --git a/src/include/rtc.h b/src/include/rtc.h new file mode 100644 index 0000000..ed32b69 --- /dev/null +++ b/src/include/rtc.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef _RTC_H_ +#define _RTC_H_ + +struct rtc_time +{ + int sec; + int min; + int hour; + int mday; + int mon; + int year; + int wday; +}; + +int rtc_set(const struct rtc_time *time, u8 has_century); +int rtc_get(struct rtc_time *time, u8 has_century); + +#endif /* _RTC_H_ */

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New patch to review for coreboot: 9cde084 southbridge/intel/*/lpc.c: Use 'BIOS_CNTL' define over 0xdc magic
by Edward O'Callaghan 30 Dec '14

30 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7989 -gerrit commit 9cde0840ab57caddaa44e67892952fbe09f77eec Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Dec 31 00:17:56 2014 +1100 southbridge/intel/*/lpc.c: Use 'BIOS_CNTL' define over 0xdc magic We define BIOS_CNTL - BIOS Control Register (LPC I/F-D31:F0) in headers, so lets make use of it in code over the raw magic value. Change-Id: If9b94a0f20c06fa4a8f156c11a794a61767ec7cd Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/soc/intel/broadwell/broadwell/lpc.h | 2 +- src/southbridge/intel/bd82x6x/lpc.c | 16 ++++++++-------- src/southbridge/intel/fsp_bd82x6x/lpc.c | 16 ++++++++-------- src/southbridge/intel/fsp_rangeley/lpc.c | 4 ++-- src/southbridge/intel/i82801gx/lpc.c | 12 ++++++------ src/southbridge/intel/i82801ix/lpc.c | 12 ++++++------ src/southbridge/intel/ibexpeak/lpc.c | 16 ++++++++-------- 7 files changed, 39 insertions(+), 39 deletions(-) diff --git a/src/soc/intel/broadwell/broadwell/lpc.h b/src/soc/intel/broadwell/broadwell/lpc.h index 180e527..8dd7f10 100644 --- a/src/soc/intel/broadwell/broadwell/lpc.h +++ b/src/soc/intel/broadwell/broadwell/lpc.h @@ -34,7 +34,7 @@ #define SCIS_IRQ22 6 #define SCIS_IRQ23 7 #define GPIOBASE 0x48 -#define BIOS_CNTL 0xdc +#define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ #define GPIO_EN (1 << 4) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 11b765a..e5b5595 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -454,15 +454,15 @@ static void pch_lock_smm(struct device *dev) #if TEST_SMM_FLASH_LOCKDOWN /* Now try this: */ printk(BIOS_DEBUG, "Locking BIOS to RO... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); reg8 &= ~(1 << 0); /* clear BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); reg8 |= (1 << 1); /* set BLE */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); printk(BIOS_DEBUG, "ok.\n"); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); @@ -470,9 +470,9 @@ static void pch_lock_smm(struct device *dev) *(volatile u8 *)0xfff00000 = 0x00; printk(BIOS_DEBUG, "Testing:\n"); reg8 |= (1 << 0); /* set BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); printk(BIOS_DEBUG, "Done.\n"); @@ -485,9 +485,9 @@ static void pch_disable_smm_only_flashing(struct device *dev) u8 reg8; printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */ reg8 &= ~(1 << 5); - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); } static void pch_fixups(struct device *dev) diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index f9961f9..2b7ae84 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -432,15 +432,15 @@ static void pch_lock_smm(struct device *dev) #if TEST_SMM_FLASH_LOCKDOWN /* Now try this: */ printk(BIOS_DEBUG, "Locking BIOS to RO... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); reg8 &= ~(1 << 0); /* clear BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); reg8 |= (1 << 1); /* set BLE */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); printk(BIOS_DEBUG, "ok.\n"); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); @@ -448,9 +448,9 @@ static void pch_lock_smm(struct device *dev) *(volatile u8 *)0xfff00000 = 0x00; printk(BIOS_DEBUG, "Testing:\n"); reg8 |= (1 << 0); /* set BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); printk(BIOS_DEBUG, "Done.\n"); @@ -463,9 +463,9 @@ static void pch_disable_smm_only_flashing(struct device *dev) u8 reg8; printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */ reg8 &= ~(1 << 5); - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); } static void pch_fixups(struct device *dev) diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 9644067..7b79dd3 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -304,9 +304,9 @@ static void soc_disable_smm_only_flashing(struct device *dev) u8 reg8; printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */ reg8 &= ~(1 << 5); - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); } static void lpc_init(struct device *dev) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 6b9d11e..b4f7066 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -356,15 +356,15 @@ static void i82801gx_lock_smm(struct device *dev) #if TEST_SMM_FLASH_LOCKDOWN /* Now try this: */ printk(BIOS_DEBUG, "Locking BIOS to RO... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); reg8 &= ~(1 << 0); /* clear BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); reg8 |= (1 << 1); /* set BLE */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); printk(BIOS_DEBUG, "ok.\n"); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); @@ -372,9 +372,9 @@ static void i82801gx_lock_smm(struct device *dev) *(volatile u8 *)0xfff00000 = 0x00; printk(BIOS_DEBUG, "Testing:\n"); reg8 |= (1 << 0); /* set BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); printk(BIOS_DEBUG, "Done.\n"); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 6038eff..815cab1 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -401,15 +401,15 @@ static void i82801ix_lock_smm(struct device *dev) #if TEST_SMM_FLASH_LOCKDOWN /* Now try this: */ printk(BIOS_DEBUG, "Locking BIOS to RO... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); reg8 &= ~(1 << 0); /* clear BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); reg8 |= (1 << 1); /* set BLE */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); printk(BIOS_DEBUG, "ok.\n"); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); @@ -417,9 +417,9 @@ static void i82801ix_lock_smm(struct device *dev) *(volatile u8 *)0xfff00000 = 0x00; printk(BIOS_DEBUG, "Testing:\n"); reg8 |= (1 << 0); /* set BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); printk(BIOS_DEBUG, "Done.\n"); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 2124711..0b87bd2 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -460,15 +460,15 @@ static void pch_lock_smm(struct device *dev) #if TEST_SMM_FLASH_LOCKDOWN /* Now try this: */ printk(BIOS_DEBUG, "Locking BIOS to RO... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); reg8 &= ~(1 << 0); /* clear BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); reg8 |= (1 << 1); /* set BLE */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); printk(BIOS_DEBUG, "ok.\n"); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); @@ -476,9 +476,9 @@ static void pch_lock_smm(struct device *dev) *(volatile u8 *)0xfff00000 = 0x00; printk(BIOS_DEBUG, "Testing:\n"); reg8 |= (1 << 0); /* set BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */ printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); printk(BIOS_DEBUG, "Done.\n"); @@ -491,9 +491,9 @@ static void pch_disable_smm_only_flashing(struct device *dev) u8 reg8; printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); /* BIOS_CNTL */ reg8 &= ~(1 << 5); - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); } static void pch_fixups(struct device *dev)

1 0

Patch set updated for coreboot: c55f3a8 macbook21: Add CST entries
by Mono Moosbart 30 Dec '14

30 Dec '14

Mono Moosbart (mono(a)posteo.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7923 -gerrit commit c55f3a8946a4ad91d1d284bd323c3d48dbb37c0b Author: Mono <mono(a)posteo.de> Date: Thu Dec 25 08:11:54 2014 +0100 macbook21: Add CST entries Enable c1 and c2 state. Change-Id: I6b2173df1dc09300329b61b51b79f4b9f4a8fb13 Signed-off-by: Axel Holewa <mono(a)posteo.de> --- src/mainboard/apple/macbook21/mainboard.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index 99527c1..7d8ffd9 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -36,9 +36,15 @@ #include <drivers/intel/gma/int15.h> #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT +static acpi_cstate_t cst_entries[] = { + { 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 0, 0 } }, + { 2, 1, 500, { 0x7f, 1, 2, { 0 }, 0x10, 0 } }, +}; + int get_cst_entries(acpi_cstate_t **entries) { - return 0; + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); } static void mainboard_init(device_t dev)

1 0

Patch merged into coreboot/master: 773485b intel CAR: Fix DCACHE_RAM_BASE for old sockets
by gerrit＠coreboot.org 30 Dec '14

30 Dec '14

the following patch was just integrated into master: commit 773485b8920145443da8b09712553c10c954fed1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 22 16:33:24 2014 +0200 intel CAR: Fix DCACHE_RAM_BASE for old sockets When using fixed MTRRs for CAR setup, CONFIG_DCACHE_RAM_BASE is ignored and was not correctly set on affected sockets and boards. It was still referenced in romstage linker script. This was discovered by clang builds failing for cases where DCACHE_RAM_BASE = 0, while gcc builds passed. The actual DCACHE_RAM_BASE programming is base = 0xd0000 - size, as taken from intel/cpu/cache_as_ram.inc. Change-Id: Ied5ab2e9683f12990f1aad48ee15eaf91133121c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/7887 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/7887 for details. -gerrit

1 0

Patch merged into coreboot/master: 2b98146 Intel FSP: Fix GPI status output
by gerrit＠coreboot.org 30 Dec '14

30 Dec '14

the following patch was just integrated into master: commit 2b9814629b4b7d96340033fc38c5003e6a8db93e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 29 11:31:59 2014 +0200 Intel FSP: Fix GPI status output Propagate commit 07c3fc089 to Intel FSP. Change-Id: Ie3e05df7fc06cb0ed6142edfedafab0cde74a68c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/7966 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/7966 for details. -gerrit

1 0

Patch set updated for coreboot: 72a0701 src/Kconfig: 's/NO_UART_ON_SUPERIO/NO_SUPERIO_CHIP/'
by Edward O'Callaghan 30 Dec '14

30 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7988 -gerrit commit 72a070106fcf016c38232aa8edb151ea8e2e4133 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Dec 30 19:30:46 2014 +1100 src/Kconfig: 's/NO_UART_ON_SUPERIO/NO_SUPERIO_CHIP/' Fashion a more intuitive name for when no Super I/O hardware is found on a given board. Change-Id: Ic026133bcb5045e9dd8e5ee4e002cde3743d2a94 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/drivers/uart/Kconfig | 4 ++-- src/mainboard/hp/pavilion_m6_1035dx/Kconfig | 2 +- src/mainboard/lenovo/g505s/Kconfig | 2 +- src/mainboard/lenovo/t520/Kconfig | 2 +- src/mainboard/lenovo/t530/Kconfig | 2 +- src/mainboard/lenovo/x200/Kconfig | 2 +- src/mainboard/lenovo/x201/Kconfig | 2 +- src/mainboard/lenovo/x220/Kconfig | 2 +- src/mainboard/lenovo/x230/Kconfig | 2 +- 9 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index fef745e..c961e32 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -6,11 +6,11 @@ config DRIVERS_UART config DRIVERS_UART_8250IO bool "Serial port on SuperIO" depends on !ARCH_ARM - default n if NO_UART_ON_SUPERIO + default n if NO_SUPERIO_CHIP default y if ARCH_X86 # Select this for mainboard without SuperIO serial port. -config NO_UART_ON_SUPERIO +config NO_SUPERIO_CHIP def_bool n config DRIVERS_UART_8250MEM diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index eba58f2..8a4d5e7 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -36,7 +36,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select GFXUMA select UDELAY_LAPIC select USBDEBUG_IN_ROMSTAGE - select NO_UART_ON_SUPERIO + select NO_SUPERIO_CHIP config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 4d2c1c2..156629d 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -34,7 +34,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_4096 select GFXUMA select UDELAY_LAPIC - select NO_UART_ON_SUPERIO + select NO_SUPERIO_CHIP config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 98355d4..e94c1a5 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select NO_UART_ON_SUPERIO + select NO_SUPERIO_CHIP select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 2dcfa90..f121e3b 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select NO_UART_ON_SUPERIO + select NO_SUPERIO_CHIP select BOARD_ROMSIZE_KB_12288 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 67fc388..c3b7eaf 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82801IX select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select NO_UART_ON_SUPERIO + select NO_SUPERIO_CHIP select DRIVERS_ICS_954309 select BOARD_ROMSIZE_KB_8192 select DRIVERS_GENERIC_IOAPIC diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 93bfb02..ee34fc0 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_IBEXPEAK select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select NO_UART_ON_SUPERIO + select NO_SUPERIO_CHIP select DRIVERS_ICS_954309 select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index c1aa046..0077710 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select NO_UART_ON_SUPERIO + select NO_SUPERIO_CHIP select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 5da62db..60bfab5 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select NO_UART_ON_SUPERIO + select NO_SUPERIO_CHIP select BOARD_ROMSIZE_KB_12288 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE

1 0

New patch to review for coreboot: b0540a2 src/Kconfig: 's/NO_UART_ON_SUPERIO/NO_SUPERIO_CHIP/'
by Edward O'Callaghan 30 Dec '14

30 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7988 -gerrit commit b0540a259189b66f9b5a57cda59d3b4d890e5810 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Dec 30 19:30:46 2014 +1100 src/Kconfig: 's/NO_UART_ON_SUPERIO/NO_SUPERIO_CHIP/' Fashion a more intuative name for when no Super I/O hardware is found on a given board. Change-Id: Ic026133bcb5045e9dd8e5ee4e002cde3743d2a94 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/drivers/uart/Kconfig | 4 ++-- src/mainboard/hp/pavilion_m6_1035dx/Kconfig | 2 +- src/mainboard/lenovo/g505s/Kconfig | 2 +- src/mainboard/lenovo/t520/Kconfig | 2 +- src/mainboard/lenovo/t530/Kconfig | 2 +- src/mainboard/lenovo/x200/Kconfig | 2 +- src/mainboard/lenovo/x201/Kconfig | 2 +- src/mainboard/lenovo/x220/Kconfig | 2 +- src/mainboard/lenovo/x230/Kconfig | 2 +- 9 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index fef745e..c961e32 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -6,11 +6,11 @@ config DRIVERS_UART config DRIVERS_UART_8250IO bool "Serial port on SuperIO" depends on !ARCH_ARM - default n if NO_UART_ON_SUPERIO + default n if NO_SUPERIO_CHIP default y if ARCH_X86 # Select this for mainboard without SuperIO serial port. -config NO_UART_ON_SUPERIO +config NO_SUPERIO_CHIP def_bool n config DRIVERS_UART_8250MEM diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index eba58f2..8a4d5e7 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -36,7 +36,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select GFXUMA select UDELAY_LAPIC select USBDEBUG_IN_ROMSTAGE - select NO_UART_ON_SUPERIO + select NO_SUPERIO_CHIP config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 4d2c1c2..156629d 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -34,7 +34,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_4096 select GFXUMA select UDELAY_LAPIC - select NO_UART_ON_SUPERIO + select NO_SUPERIO_CHIP config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 98355d4..e94c1a5 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select NO_UART_ON_SUPERIO + select NO_SUPERIO_CHIP select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 2dcfa90..f121e3b 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select NO_UART_ON_SUPERIO + select NO_SUPERIO_CHIP select BOARD_ROMSIZE_KB_12288 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 67fc388..c3b7eaf 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82801IX select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select NO_UART_ON_SUPERIO + select NO_SUPERIO_CHIP select DRIVERS_ICS_954309 select BOARD_ROMSIZE_KB_8192 select DRIVERS_GENERIC_IOAPIC diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 93bfb02..ee34fc0 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_IBEXPEAK select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select NO_UART_ON_SUPERIO + select NO_SUPERIO_CHIP select DRIVERS_ICS_954309 select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index c1aa046..0077710 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select NO_UART_ON_SUPERIO + select NO_SUPERIO_CHIP select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 5da62db..60bfab5 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -8,7 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select NO_UART_ON_SUPERIO + select NO_SUPERIO_CHIP select BOARD_ROMSIZE_KB_12288 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE

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Patch set updated for coreboot: 2719549 mainboard/lenovo/?/Kconfig: select NO_UART_ON_SUPERIO
by Edward O'Callaghan 30 Dec '14

30 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7986 -gerrit commit 2719549717d6a09ab182e5dbcdf829fef271afca Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Dec 30 15:54:47 2014 +1100 mainboard/lenovo/?/Kconfig: select NO_UART_ON_SUPERIO These boards don't have Super I/O's, rather they use Embedded Controllers instead. No need to confuse with Super I/O related stuff showing up in menuconfig. Change-Id: I4922319daf7920bf5331b5bce05ded0d9a31a69b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t520/Kconfig | 1 + src/mainboard/lenovo/x200/Kconfig | 1 + src/mainboard/lenovo/x201/Kconfig | 1 + src/mainboard/lenovo/x220/Kconfig | 1 + src/mainboard/lenovo/x230/Kconfig | 1 + 5 files changed, 5 insertions(+) diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index d91ed67..98355d4 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 + select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 15e55c7..67fc388 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82801IX select EC_LENOVO_PMH7 select EC_LENOVO_H8 + select NO_UART_ON_SUPERIO select DRIVERS_ICS_954309 select BOARD_ROMSIZE_KB_8192 select DRIVERS_GENERIC_IOAPIC diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index b1ca2f5..93bfb02 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_IBEXPEAK select EC_LENOVO_PMH7 select EC_LENOVO_H8 + select NO_UART_ON_SUPERIO select DRIVERS_ICS_954309 select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 20e9527..c1aa046 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 + select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 1a1e018..5da62db 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 + select NO_UART_ON_SUPERIO select BOARD_ROMSIZE_KB_12288 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE

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coreboot-gerrit December 2014