coreboot-gerrit December 2014

coreboot-gerrit@coreboot.org

1 participants
1346 discussions

Patch merged into coreboot/master: 019bacb libpayload: Remove PC Keyboard from ARM build
by gerrit＠coreboot.org 30 Dec '14

30 Dec '14

the following patch was just integrated into master: commit 019bacb41a01f9d26ccd6040641402131af0f602 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue Dec 23 15:22:30 2014 -0700 libpayload: Remove PC Keyboard from ARM build The keyboard.c uses IO cycles to access the legacy PC keyboard device. ARM can't do IO cycles, so remove the option for ARM configs. Change-Id: Ifc6c2368563f27867f4babad5afdde0e78f4cf78 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7922 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/7922 for details. -gerrit

1 0

Patch merged into coreboot/master: 86127c7 libpayload: Clean up USB build warnings
by gerrit＠coreboot.org 30 Dec '14

30 Dec '14

the following patch was just integrated into master: commit 86127c7bfe14e8b3f9e45de66d503102eafa654f Author: Marc Jones <marc.jones(a)se-eng.com> Date: Mon Dec 29 22:07:04 2014 -0700 libpayload: Clean up USB build warnings There were a few build warnings in the USB driver to clean up before -Werror may be enabled. Change-Id: I220cfcf0ee926912a184a91d3ced3ba61259130e Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7921 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/7921 for details. -gerrit

1 0

Patch merged into coreboot/master: b4fbee9 libpayload: video: Make cursor fixup independent of visibility
by gerrit＠coreboot.org 30 Dec '14

30 Dec '14

the following patch was just integrated into master: commit b4fbee9a415296b706c9f4f4dcb3e4d1e3ea3110 Author: Julius Werner <jwerner(a)chromium.org> Date: Tue Apr 22 13:06:13 2014 -0700 libpayload: video: Make cursor fixup independent of visibility The video console runs a video_console_fixup_cursor() function after every printed character to make sure the cursor is still in the output window and avoid overflows. For some crazy reason, this function does not run when cursor_enabled is false... however, that variable is only about cursor *visibility*, and it's imperative that we still do proper bounds checking for our output even if the cursor itself doesn't get displayed (otherwise we can end up overwriting malloc cookies that cause a panic on the next free() and other fun things like that). In fact, there seems to be no reason at all to even keep track of the cursor visibility state in the generic video console framework (the specific backends already do it, too), so let's remove that code entirely. Also set the default cursor visibilty in the corebootfb backend to 0 since that's consistent with what the other backends do. BUG=None TEST=Turn on video console on Big, generate enough output to make it scroll, make sure it does not crash. Original-Change-Id: I1201a5bccb4711b6ecfc4cf47a8ace16331501b4 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196323 Original-Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Original-Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit 1f880bca06ed0a3f2c75abab399d32a2e51ed10e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I6c67a9efb00d96fcd67f7bc1ab55a23e78fc479e Reviewed-on: http://review.coreboot.org/7908 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/7908 for details. -gerrit

1 0

Patch set updated for coreboot: f1fc815 libpayload: Provide selfboot function.
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7907 -gerrit commit f1fc8154843002d84c12357c410f55d83c991faf Author: Hung-Te Lin <hungte(a)chromium.org> Date: Tue May 13 22:33:12 2014 +0800 libpayload: Provide selfboot function. The calling convention of payload entry function is different by architecture. For example, X86 takes no arguments and ARM needs first param to be a cb_header_ptr*. To help payloads load and execute other payloads easily and correctly, we should provide the selfboot() function in libpayload, using same prototype as defined in coreboot environment. BUG=none TEST=emerge-nyan libpayload # pass BRANCH=none Original-Change-Id: I8f1cb2c0df788794b2f6f7f5500a3910328a4f84 Original-Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199503 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit 1e916cf021ce68886eb9668982c392eadedc7b7e) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I7279ef27f49ef581d25a455dd8f1f2f7f1ba58cb --- payloads/libpayload/arch/arm/Makefile.inc | 1 + payloads/libpayload/arch/arm/selfboot.c | 35 +++++++++++++++++++++++++++++++ payloads/libpayload/arch/x86/Makefile.inc | 1 + payloads/libpayload/arch/x86/selfboot.c | 28 +++++++++++++++++++++++++ payloads/libpayload/include/cbfs.h | 3 +-- 5 files changed, 66 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/arch/arm/Makefile.inc b/payloads/libpayload/arch/arm/Makefile.inc index 5c22ea8..7009884 100644 --- a/payloads/libpayload/arch/arm/Makefile.inc +++ b/payloads/libpayload/arch/arm/Makefile.inc @@ -38,6 +38,7 @@ libc-y += virtual.c libc-y += memcpy.S memset.S memmove.S libc-y += exception_asm.S exception.c libc-y += cache.c cpu.S +libc-y += selfboot.c libcbfs-$(CONFIG_LP_CBFS) += dummy_media.c # Add other classes here when you put assembly files into them! diff --git a/payloads/libpayload/arch/arm/selfboot.c b/payloads/libpayload/arch/arm/selfboot.c new file mode 100644 index 0000000..cbb7ef1 --- /dev/null +++ b/payloads/libpayload/arch/arm/selfboot.c @@ -0,0 +1,35 @@ +/* + * Copyright 2014 Google Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <libpayload.h> + +extern void *cb_header_ptr; + +void selfboot(void *entry) +{ + __asm__ __volatile__( + "mov r0, %[cb_header_ptr]\n" + "bx %[entry]\n" + :: [cb_header_ptr]"r"(cb_header_ptr), [entry]"r"(entry) + : "r0" + ); +} diff --git a/payloads/libpayload/arch/x86/Makefile.inc b/payloads/libpayload/arch/x86/Makefile.inc index 549a630..d9cc19e 100644 --- a/payloads/libpayload/arch/x86/Makefile.inc +++ b/payloads/libpayload/arch/x86/Makefile.inc @@ -31,6 +31,7 @@ head.o-y += head.S libc-y += main.c sysinfo.c libc-y += timer.c coreboot.c util.S libc-y += exec.S virtual.c +libc-y += selfboot.c libc-y += string.c libc-y += exception_asm.S exception.c diff --git a/payloads/libpayload/arch/x86/selfboot.c b/payloads/libpayload/arch/x86/selfboot.c new file mode 100644 index 0000000..fc89859 --- /dev/null +++ b/payloads/libpayload/arch/x86/selfboot.c @@ -0,0 +1,28 @@ +/* + * Copyright 2014 Google Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <libpayload.h> + +void selfboot(void *entry) +{ + void (*entry_func)(void) = entry; + entry_func(); +} diff --git a/payloads/libpayload/include/cbfs.h b/payloads/libpayload/include/cbfs.h index df3bb1c..c5c811c 100644 --- a/payloads/libpayload/include/cbfs.h +++ b/payloads/libpayload/include/cbfs.h @@ -82,8 +82,7 @@ void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, int run_address(void *f); /* Defined in src/lib/selfboot.c */ -struct lb_memory; -int selfboot(struct lb_memory *mem, struct cbfs_payload *payload); +void selfboot(void *entry); /* Defined in individual arch / board implementation. */ int init_default_cbfs_media(struct cbfs_media *media);

1 0

Patch merged into coreboot/master: d6b001e libpayload: arm: Add EABI compatible utility functions.
by gerrit＠coreboot.org 30 Dec '14

30 Dec '14

the following patch was just integrated into master: commit d6b001e36d2371345ca1b9de99981d0389807868 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed May 14 12:43:57 2014 +0800 libpayload: arm: Add EABI compatible utility functions. Some EABI conformant toolchains like GCC need additional functions like raise. To prevent payloads adding arch-specific implementations everywhere, we should provide the default version in libpayload. BUG=none TEST=emerge-nyan libpayload # pass BRANCH=none Original-Change-Id: Id1e3c29590aa5881aefd944a7551949ce9a47b8f Original-Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199686 (cherry picked from commit 395810c4b744dbb720050f79a2c1a30e81464554) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I2e1d8c8cb519f8e788c22d081132d23b49b8f822 Reviewed-on: http://review.coreboot.org/7906 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/7906 for details. -gerrit

1 0

Patch merged into coreboot/master: e30e4e7 libpayload: usbmsc: Implement limited LUN support
by gerrit＠coreboot.org 30 Dec '14

30 Dec '14

the following patch was just integrated into master: commit e30e4e7efa8c56b134e85f235c8f315a6a2b583b Author: Julius Werner <jwerner(a)chromium.org> Date: Fri May 2 16:35:50 2014 -0700 libpayload: usbmsc: Implement limited LUN support I always thought the support for multiple logical SCSI units in the USB mass storage class was a dead feature. Turns out that it's actually used by SD card readers that provide multiple slots (e.g. one regular sized and one micro-SD). Implementing perfect support for that would require a major redesign of the whole MSC stack, since the one device -> one disk assumption is deeply embedded in our data structures. Instead, this patch implements a poor man's LUN support that will just cycle through all available LUNs (in multiple calls to usb_msc_poll()) until it finds a connected device. This should be reasonable enough to allow these card readers to be usable while only requiring superficial changes. Also removes the unused 'protocol' attribute of usb_msc_inst_t. BRANCH=rambi?,nyan BUG=chrome-os-partner:28437 TEST=Alternatively plug an SD or micro-SD card (or both) into my card reader, confirm that one of them is correctly detected at all times. Original-Change-Id: I3df4ca88afe2dcf7928b823aa2a73c2b0f599cf2 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/198101 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 960534a20e4334772c29355bb0d310b3f41b31ee) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I39909fc96e32c9a5d76651d91c2b5c16c89ace9e Reviewed-on: http://review.coreboot.org/7904 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/7904 for details. -gerrit

1 0

Patch merged into coreboot/master: 7124788 libpayload: usbmsc: Set correct allocation length for REQUEST SENSE
by gerrit＠coreboot.org 30 Dec '14

30 Dec '14

the following patch was just integrated into master: commit 7124788b335b88c913b04802ddd84db0c438ccc0 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri May 2 14:51:03 2014 -0700 libpayload: usbmsc: Set correct allocation length for REQUEST SENSE So I was debugging this faulty USB SD card reader that would just fail it's REQUEST SENSE response for some reason (sending the CSW immediately without the data), cursing those damn device vendors for building non-compliant crap like I always do... when I noticed that we do not actually set the Allocation Length field in our REQUEST SENSE command block at all! We set a length in the CBW, but the SCSI command still has its own length field and the SCSI spec specifically says that the device has to return the exact amount of bytes listed there (even if it's 0). I don't know what's more suprising: that we had such a blatant bug in this stack for so long, or that this card reader is really the first device to actually be spec compliant in that regard. This patch fixes the bug and changes the command block structures to be a little easier to read (why that field was called 'lun' before is beyond me... LUN is a transport level thing and should never appear in the command block at all, for any command). It also fixes a memcpy() in wrap_cbw() to avoid a read buffer overflow that might expose stack frame data to the device. BRANCH=rambi?,nyan BUG=chrome-os-partner:28437 TEST=The card reader works now (for it's first LUN at least). Original-Change-Id: I86fdcae2ea4d2e2939e3676d31d8b6a4e797873b Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/198100 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 88943d9715994a14c50e74170f2453cceca0983b) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I3097c223248c07c866a33d4ab8f3db1a7082a815 Reviewed-on: http://review.coreboot.org/7903 Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/7903 for details. -gerrit

1 0

Patch set updated for coreboot: daaf8ac libpayload: video: Check for 'console' pointer before dereferencing it
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7910 -gerrit commit daaf8acbc2d099d1086e10f8353c0f4e6aa0f9d2 Author: Julius Werner <jwerner(a)chromium.org> Date: Tue May 20 17:56:25 2014 -0700 libpayload: video: Check for 'console' pointer before dereferencing it Seems that the 'if (cursor_enabled)' check in video_console_fixup_cursor() that was removed in chromium.org 1f880bca0 really meant to check for 'if (console)'. Looks like the whole video console driver is built extra robust to not fail no matter how screwed up the console is, so let's add this missing check here as well. Also fixed up a few other missing 'if (!console)' checks while I'm at it. However, what payloads should really be doing is check the return value of video_(console_)init() and not call the other video functions if that failed. This also adapts video_console_init() to correctly pass through the return value for that purpose (something that seems to have been overlooked in the dd9e4e58 refactoring). BUG=chrome-os-partner:28494 TEST=None. I don't know what Dave did to trigger this in the first place, but it's pretty straight-forward. Original-Change-Id: I1b9f09d49dc70dacf20621b19e081c754d4814f7 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/200688 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 3f01d1dc0974774f0b3ba5fc4e069978f266f2fc) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I98c1d8360539b457e6df07cbcf799acaf6c4631b --- payloads/libpayload/drivers/video/video.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/payloads/libpayload/drivers/video/video.c b/payloads/libpayload/drivers/video/video.c index 318548b..5f76a30 100644 --- a/payloads/libpayload/drivers/video/video.c +++ b/payloads/libpayload/drivers/video/video.c @@ -73,6 +73,9 @@ void video_get_rows_cols(unsigned int *rows, unsigned int *cols) static void video_console_fixup_cursor(void) { + if (!console) + return; + if (cursorx < 0) cursorx = 0; @@ -89,7 +92,7 @@ static void video_console_fixup_cursor(void) cursory--; } - if (console && console->set_cursor) + if (console->set_cursor) console->set_cursor(cursorx, cursory); } @@ -119,6 +122,9 @@ void video_console_putc(u8 row, u8 col, unsigned int ch) void video_console_putchar(unsigned int ch) { + if (!console) + return; + /* replace black-on-black with light-gray-on-black. * do it here, instead of in libc/console.c */ @@ -145,16 +151,11 @@ void video_console_putchar(unsigned int ch) break; case '\t': - while(cursorx % 8 && cursorx < console->columns) { - if (console) - console->putc(cursory, cursorx, (ch & 0xFF00) | ' '); - - cursorx++; - } + while(cursorx % 8 && cursorx < console->columns) + console->putc(cursory, cursorx++, (ch & 0xFF00) | ' '); break; default: - if (console) - console->putc(cursory, cursorx++, ch); + console->putc(cursory, cursorx++, ch); break; } @@ -167,7 +168,7 @@ void video_console_get_cursor(unsigned int *x, unsigned int *y, unsigned int *en *y=0; *en=0; - if (console->get_cursor) + if (console && console->get_cursor) console->get_cursor(x, y, en); *x = cursorx; @@ -214,9 +215,10 @@ int video_init(void) int video_console_init(void) { - video_init(); - if (console) - console_add_output_driver(&cons); + int ret = video_init(); + if (ret) + return ret; + console_add_output_driver(&cons); return 0; }

1 0

Patch merged into coreboot/master: 87acccc CBMEM: Always build for x86 romstage
by gerrit＠coreboot.org 30 Dec '14

30 Dec '14

the following patch was just integrated into master: commit 87accccdc2dda421dee967badbdbc701fea0753e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 19 09:19:29 2014 +0200 CBMEM: Always build for x86 romstage Always build CBMEM for romstage, even for boards that will not use it. We further restrict car_migrate_variables() runs to non-ROMCC boards without BROKEN_CAR_MIGRATE. This fixes regression of commit 71b21455 that broke CBMEM console support for boards with a combination of !EARLY_CBMEM_INIT && !HAVE_ACPI_RESUME. Change-Id: Ife91d7baebdc9bd1e086896400059a165d3aa90f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/7877 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/7877 for details. -gerrit

1 0

Patch set updated for coreboot: 8fdfcde rtc: make ALTCENTURY a KCONFIG option.
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7987 -gerrit commit 8fdfcdeb6990e5dab38a931245faf2175488f6df Author: Gabe Black <gabeblack(a)google.com> Date: Wed Apr 30 21:31:44 2014 -0700 rtc: make ALTCENTURY a KCONFIG option. The availability of "ALTCENTURY" is now set through a kconfig variable so it can be available to the RTC driver without having to have a specialized interface. BUG=None TEST=Built and booted on Link with the event log code modified to use the RTC interface. Verified that the event times were accurate. BRANCH=nyan Original-Change-Id: Ifa807898e583254e57167fd44932ea86627a02ee Original-Signed-off-by: Gabe Black <gabeblack(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197795 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: Gabe Black <gabeblack(a)chromium.org> Original-Commit-Queue: Gabe Black <gabeblack(a)chromium.org> This is the second half the following patch. (cherry picked from commit 9e0fd75142d29afe34f6c6b9ce0099f478ca5a93) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I8e871f31c3d4be7676abf9454ca90808d1ddca03 --- src/drivers/pc80/Kconfig | 5 +++++ src/drivers/pc80/mc146818rtc.c | 22 +++++++++++----------- src/include/pc80/mc146818rtc.h | 5 +---- src/include/rtc.h | 4 ++-- src/southbridge/amd/agesa/hudson/lpc.c | 2 +- src/southbridge/amd/cimx/sb700/late.c | 2 +- src/southbridge/amd/cimx/sb800/late.c | 2 +- src/southbridge/amd/cimx/sb900/late.c | 2 +- src/southbridge/amd/pi/avalon/lpc.c | 2 +- src/southbridge/amd/sb600/lpc.c | 2 +- src/southbridge/amd/sb700/lpc.c | 2 +- src/southbridge/amd/sb800/lpc.c | 2 +- 12 files changed, 27 insertions(+), 25 deletions(-) diff --git a/src/drivers/pc80/Kconfig b/src/drivers/pc80/Kconfig index f8ac5c5..1344390 100644 --- a/src/drivers/pc80/Kconfig +++ b/src/drivers/pc80/Kconfig @@ -26,3 +26,8 @@ config LPC_TPM config DRIVERS_MC146818 bool default y if ARCH_X86 + +config DRIVERS_RTC_HAS_ALTCENTURY + bool "The RTC supports alt century" + depends on DRIVERS_MC146818 + default y diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index 84abd43..03018e4 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -32,7 +32,7 @@ #endif -static void cmos_reset_date(u8 has_century) +static void cmos_reset_date(void) { /* Now setup a default date equals to the build date */ struct rtc_time time = { @@ -45,7 +45,7 @@ static void cmos_reset_date(u8 has_century) bcd2bin(coreboot_build_date.year), .wday = bcd2bin(coreboot_build_date.weekday) }; - rtc_set(&time, has_century); + rtc_set(&time); } #if CONFIG_USE_OPTION_TABLE @@ -123,7 +123,7 @@ void cmos_init(int invalid) cmos_write(0, i); #endif if (cmos_invalid) - cmos_reset_date(RTC_HAS_NO_ALTCENTURY); + cmos_reset_date(); printk(BIOS_WARNING, "RTC:%s%s%s%s\n", invalid?" Clear requested":"", @@ -325,12 +325,13 @@ enum cb_err set_option(const char *name, void *value) * hurts some OSes. Even if we don't set USE_OPTION_TABLE, we need * to make sure the date is valid. */ -void cmos_check_update_date(u8 has_century) +void cmos_check_update_date() { u8 year, century; /* Note: Need to check if the hardware supports RTC_CLK_ALTCENTURY. */ - century = has_century ? cmos_read(RTC_CLK_ALTCENTURY) : 0; + century = CONFIG_DRIVERS_RTC_HAS_ALTCENTURY ? + cmos_read(RTC_CLK_ALTCENTURY) : 0; year = cmos_read(RTC_CLK_YEAR); /* @@ -339,25 +340,24 @@ void cmos_check_update_date(u8 has_century) * if the date is valid. */ if (century > 0x99 || year > 0x99) /* Invalid date */ - cmos_reset_date(has_century); + cmos_reset_date(); } -int rtc_set(const struct rtc_time *time, u8 has_century) -{ +int rtc_set(const struct rtc_time *time){ cmos_write(bin2bcd(time->sec), RTC_CLK_SECOND); cmos_write(bin2bcd(time->min), RTC_CLK_MINUTE); cmos_write(bin2bcd(time->hour), RTC_CLK_HOUR); cmos_write(bin2bcd(time->mday), RTC_CLK_DAYOFMONTH); cmos_write(bin2bcd(time->mon), RTC_CLK_MONTH); cmos_write(bin2bcd(time->year % 100), RTC_CLK_YEAR); - if (has_century) + if (CONFIG_DRIVERS_RTC_HAS_ALTCENTURY) cmos_write(bin2bcd(time->year / 100), RTC_CLK_ALTCENTURY); cmos_write(bin2bcd(time->wday + 1), RTC_CLK_DAYOFWEEK); return 0; } -int rtc_get(struct rtc_time *time, u8 has_century) +int rtc_get(struct rtc_time *time) { time->sec = bcd2bin(cmos_read(RTC_CLK_SECOND)); time->min = bcd2bin(cmos_read(RTC_CLK_MINUTE)); @@ -365,7 +365,7 @@ int rtc_get(struct rtc_time *time, u8 has_century) time->mday = bcd2bin(cmos_read(RTC_CLK_DAYOFMONTH)); time->mon = bcd2bin(cmos_read(RTC_CLK_MONTH)); time->year = bcd2bin(cmos_read(RTC_CLK_YEAR)); - if (has_century) + if (CONFIG_DRIVERS_RTC_HAS_ALTCENTURY) time->year += bcd2bin(cmos_read(RTC_CLK_ALTCENTURY)) * 100; else time->year += 2000; diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 3d65909..90ae7ae 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -94,9 +94,6 @@ #define RTC_CLK_YEAR 9 #define RTC_CLK_ALTCENTURY 0x32 -#define RTC_HAS_ALTCENTURY 1 -#define RTC_HAS_NO_ALTCENTURY 0 - /* On PCs, the checksum is built only over bytes 16..45 */ #define PC_CKS_RANGE_START 16 #define PC_CKS_RANGE_END 45 @@ -173,7 +170,7 @@ static inline void cmos_write32(u8 offset, u32 value) #if !defined(__ROMCC__) void cmos_init(int invalid); -void cmos_check_update_date(u8 has_century); +void cmos_check_update_date(void); #if CONFIG_USE_OPTION_TABLE enum cb_err set_option(const char *name, void *val); enum cb_err get_option(void *dest, const char *name); diff --git a/src/include/rtc.h b/src/include/rtc.h index ed32b69..ba9a9c3 100644 --- a/src/include/rtc.h +++ b/src/include/rtc.h @@ -31,7 +31,7 @@ struct rtc_time int wday; }; -int rtc_set(const struct rtc_time *time, u8 has_century); -int rtc_get(struct rtc_time *time, u8 has_century); +int rtc_set(const struct rtc_time *time); +int rtc_get(struct rtc_time *time); #endif /* _RTC_H_ */ diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 836966e..b784fc4 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -71,7 +71,7 @@ static void lpc_init(device_t dev) byte |= 1 << 0 | 1 << 3; pci_write_config8(dev, 0xBB, byte); - cmos_check_update_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(); /* Initialize the real time clock. * The 0 argument tells cmos_init not to diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c index 9c70482..3fa6940 100644 --- a/src/southbridge/amd/cimx/sb700/late.c +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -81,7 +81,7 @@ static void lpc_init(device_t dev) { printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - Start.\n"); - cmos_check_update_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(); /* Initialize the real time clock. * The 0 argument tells cmos_init not to diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 9c4047f..d7f22d3 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -132,7 +132,7 @@ static void lpc_init(device_t dev) { printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n"); - cmos_check_update_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(); /* Initialize the real time clock. * The 0 argument tells cmos_init not to diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index 6f6a501..e9f5ad6 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -103,7 +103,7 @@ static void lpc_init(device_t dev) printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n"); /* SB Configure HPET base and enable bit */ //- hpetInit(sb_config, &(sb_config->BuildParameters)); - cmos_check_update_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(); /* Initialize the real time clock. * The 0 argument tells cmos_init not to diff --git a/src/southbridge/amd/pi/avalon/lpc.c b/src/southbridge/amd/pi/avalon/lpc.c index 1f60bc4..7b54cc3 100644 --- a/src/southbridge/amd/pi/avalon/lpc.c +++ b/src/southbridge/amd/pi/avalon/lpc.c @@ -70,7 +70,7 @@ static void lpc_init(device_t dev) byte |= 1 << 0 | 1 << 3; pci_write_config8(dev, 0xBB, byte); - cmos_check_update_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(); /* Initialize the real time clock. * The 0 argument tells cmos_init not to diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index acee69d..dc2f31b 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -63,7 +63,7 @@ static void lpc_init(device_t dev) byte &= ~(1 << 1); pci_write_config8(dev, 0x78, byte); - cmos_check_update_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(); } static void sb600_lpc_read_resources(device_t dev) diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 26478b7..8ebc765 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -90,7 +90,7 @@ static void lpc_init(device_t dev) } #endif - cmos_check_update_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(); } void backup_top_of_ram(uint64_t ramtop) diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index f862a97..87c09a2 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -74,7 +74,7 @@ static void lpc_init(device_t dev) byte |= 1 << 0 | 1 << 3; pci_write_config8(dev, 0xBB, byte); - cmos_check_update_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(); } static void sb800_lpc_read_resources(device_t dev)

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2014