coreboot-gerrit December 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 37b06ea mainboard/lenovo/t530/Kconfig: Enable VMX by default
by Edward O'Callaghan 30 Dec '14

30 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7984 -gerrit commit 37b06ea9978d0caf14b31d5d064b56a71d66b1a6 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Dec 30 15:30:29 2014 +1100 mainboard/lenovo/t530/Kconfig: Enable VMX by default Fix a trivial tab/space indent inconsistency while here. Change-Id: I819d85293e1a070817cd13349a220ba85ba89951 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/Kconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 2103c35..2dcfa90 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select IVYBRIDGE_LVDS select MAINBOARD_DO_NATIVE_VGA_INIT # default to native vga init + select ENABLE_VMX # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE @@ -50,8 +51,8 @@ config MAX_CPUS default 8 config USBDEBUG_HCD_INDEX - int - default 2 + int + default 2 config DRAM_RESET_GATE_GPIO int

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Patch merged into coreboot/master: dfc1ca7 mainboard/lenovo/t530/Kconfig: No Super I/O on this board
by gerrit＠coreboot.org 30 Dec '14

30 Dec '14

the following patch was just integrated into master: commit dfc1ca73530b9a92748612255d17bd8e10b5d5fe Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Dec 30 15:34:43 2014 +1100 mainboard/lenovo/t530/Kconfig: No Super I/O on this board Disable Super I/O related topics showing in menuconfig. Change-Id: I246bc935147baf6ff2dfcb306079cc2d4c7cb153 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/7985 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/7985 for details. -gerrit

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Patch set updated for coreboot: 31ee74b Provide a common CBFS wrapper for SPI storage
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7932 -gerrit commit 31ee74bb590bc251163730751f3507dc8ef4076f Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu May 1 12:23:09 2014 -0700 Provide a common CBFS wrapper for SPI storage Coreboot has all necessary infrastructure to use the proper SPI flash interface in bootblock for CBFS. This patch creates a common CBFS wrapper which can be enabled on different platforms as required. COMMON_CBFS_SPI_WRAPPER, a new configuration option, enables the common CBFS interface and prevents default inclusion of all SPI chip drivers, only explicitly configured ones will be included when the new feature is enabled. Since the wrapper uses the same driver at all stages, enabling the new feature will also make it necessary to include the SPI chip drivers in bootblock and romstage images. init_default_cbfs_media() can now be common for different platforms, and as such is defined in the library. BUG=none TEST=manual . with this change and the rest of the patches coreboot on AP148 comes up all the way to attempting to boot the payload (reading earlier stages from the SPI flash along the way). Original-Change-Id: Ia887bb7f386a0e23a110e38001d86f9d43fadf2c Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197800 Original-Tested-by: Vadim Bendebury <vbendeb(a)google.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 60eb16ebe624f9420c6191afa6ba239b8e83a6e6) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I7b0bf3dda915c227659ab62743e405312dedaf41 --- src/Kconfig | 8 ++++ src/drivers/spi/Kconfig | 20 +++++----- src/drivers/spi/Makefile.inc | 23 +++++++++++ src/lib/Makefile.inc | 4 ++ src/lib/cbfs_spi.c | 95 ++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 140 insertions(+), 10 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 0fb88da..bb8bf05 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -47,6 +47,14 @@ config CBFS_PREFIX Select the prefix to all files put into the image. It's "fallback" by default, "normal" is a common alternative. +config COMMON_CBFS_SPI_WRAPPER + bool + default n + depends on SPI_FLASH + depends on !ARCH_X86 + help + Use common wrapper to interface CBFS to SPI bootrom. + choice prompt "Compiler to use" default COMPILER_GCC diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index cc8703f..3a1950f 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -59,70 +59,70 @@ config SPI_FLASH_NO_FAST_READ config SPI_FLASH_ADESTO bool - default y + default y if !COMMON_CBFS_SPI_WRAPPER help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Adesto Technologies. config SPI_FLASH_AMIC bool - default y + default y if !COMMON_CBFS_SPI_WRAPPER help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by AMIC. config SPI_FLASH_ATMEL bool - default y + default y if !COMMON_CBFS_SPI_WRAPPER help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Atmel. config SPI_FLASH_EON bool - default y + default y if !COMMON_CBFS_SPI_WRAPPER help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by EON. config SPI_FLASH_GIGADEVICE bool - default y + default y if !COMMON_CBFS_SPI_WRAPPER help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Gigadevice. config SPI_FLASH_MACRONIX bool - default y + default y if !COMMON_CBFS_SPI_WRAPPER help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Macronix. config SPI_FLASH_SPANSION bool - default y + default y if !COMMON_CBFS_SPI_WRAPPER help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Spansion. config SPI_FLASH_SST bool - default y + default y if !COMMON_CBFS_SPI_WRAPPER help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by SST. config SPI_FLASH_STMICRO bool - default y + default y if !COMMON_CBFS_SPI_WRAPPER help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by ST MICRO. config SPI_FLASH_WINBOND bool - default y + default y if !COMMON_CBFS_SPI_WRAPPER help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Winbond. diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc index 934743e..1bada79 100644 --- a/src/drivers/spi/Makefile.inc +++ b/src/drivers/spi/Makefile.inc @@ -1,4 +1,27 @@ # SPI flash driver interface + +ifeq ($(CONFIG_COMMON_CBFS_SPI_WRAPPER),y) +bootblock-y += spi_flash.c +bootblock-$(CONFIG_SPI_FLASH_EON) += eon.c +bootblock-$(CONFIG_SPI_FLASH_GIGADEVICE) += gigadevice.c +bootblock-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.c +bootblock-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c +bootblock-$(CONFIG_SPI_FLASH_SST) += sst.c +bootblock-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c +bootblock-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c +bootblock-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c + +romstage-$(CONFIG_SPI_FLASH) += spi_flash.c +romstage-$(CONFIG_SPI_FLASH_EON) += eon.c +romstage-$(CONFIG_SPI_FLASH_GIGADEVICE) += gigadevice.c +romstage-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.c +romstage-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c +romstage-$(CONFIG_SPI_FLASH_SST) += sst.c +romstage-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c +romstage-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c +romstage-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c +endif + ramstage-$(CONFIG_SPI_FLASH) += spi_flash.c # drivers diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 327c9f2..2dbf905 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -19,6 +19,8 @@ subdirs-y += loaders bootblock-y += cbfs.c cbfs_core.c +bootblock-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c + bootblock-y += memchr.c bootblock-y += memcmp.c @@ -29,6 +31,7 @@ $(foreach arch,$(ARCH_SUPPORTED),\ romstage-$(CONFIG_I2C_TPM) += delay.c romstage-y += cbfs.c cbfs_core.c +romstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c romstage-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c lzmadecode.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c @@ -55,6 +58,7 @@ ramstage-y += delay.c ramstage-y += fallback_boot.c ramstage-y += compute_ip_checksum.c ramstage-y += cbfs.c cbfs_core.c +ramstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c ramstage-y += lzma.c lzmadecode.c ramstage-y += stack.c ramstage-y += clog2.c diff --git a/src/lib/cbfs_spi.c b/src/lib/cbfs_spi.c new file mode 100644 index 0000000..4471532 --- /dev/null +++ b/src/lib/cbfs_spi.c @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * This file provides a common CBFS wrapper for SPI storage. SPI driver + * context is expanded with the buffer descriptor used to store data read from + * SPI. + */ + +#include <cbfs.h> +#include <spi_flash.h> + +/* SPI flash as CBFS media. */ +struct cbfs_spi_context { + struct spi_flash *spi_flash_info; + struct cbfs_simple_buffer buffer; +}; + +static struct cbfs_spi_context spi_context; + +static int cbfs_media_open(struct cbfs_media *media) +{ + return 0; +} + +static int cbfs_media_close(struct cbfs_media *media) +{ + return 0; +} + +static size_t cbfs_media_read(struct cbfs_media *media, + void *dest, size_t offset, + size_t count) +{ + struct cbfs_spi_context *context = media->context; + + return context->spi_flash_info->read + (context->spi_flash_info, offset, count, dest) ? 0 : count; +} + +static void *cbfs_media_map(struct cbfs_media *media, + size_t offset, size_t count) +{ + struct cbfs_spi_context *context = media->context; + + return cbfs_simple_buffer_map(&context->buffer, media, offset, count); +} + +static void *cbfs_media_unmap(struct cbfs_media *media, + const void *address) +{ + struct cbfs_spi_context *context = media->context; + + return cbfs_simple_buffer_unmap(&context->buffer, address); +} + +int init_default_cbfs_media(struct cbfs_media *media) +{ + if (spi_context.buffer.buffer) + return 0; /* It has been already initialized. */ + + spi_context.spi_flash_info = spi_flash_probe + (CONFIG_BOOT_MEDIA_SPI_BUS, 0); + if (!spi_context.spi_flash_info) + return -1; + + spi_context.buffer.buffer = (void *)CONFIG_CBFS_CACHE_ADDRESS; + spi_context.buffer.size = CONFIG_CBFS_CACHE_SIZE; + + media->context = &spi_context; + + media->open = cbfs_media_open; + media->close = cbfs_media_close; + media->read = cbfs_media_read; + media->map = cbfs_media_map; + media->unmap = cbfs_media_unmap; + + return 0; +}

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Patch set updated for coreboot: 4262dc9 drivers/spi: Prepare Spansion driver for use in CBFS wrapper
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7933 -gerrit commit 4262dc95b83d1f392bc8a4bd75160f8faa959372 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu May 1 19:30:46 2014 -0700 drivers/spi: Prepare Spansion driver for use in CBFS wrapper Since the same driver is going to be used at all coreboot stages, it can not use malloc() anymore. Replace it with static allocation of the driver container structure. The read interface is changed to spi_flash_cmd_read_slow(), because of the problems with spi_flash_cmd_read_fast() implementation. In fact there is no performance difference in the way the two interface functions are implemented. BUG=chrome-os-partner:27784 TEST=manual . with all patches applied coreboot proceeds to attempting to load the payload. Original-Change-Id: I1c7beedce7747bc89ab865fd844b568ad50d2dae Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197931 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 57ee2fd875c689706c70338e073acefb806787e7) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I9d9e7e343148519580ed4986800dc6c6b9a5f5d2 --- src/drivers/spi/spansion.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index e17f890..c7e31fe 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -208,6 +208,8 @@ static int spansion_erase(struct spi_flash *flash, u32 offset, size_t len) return spi_flash_cmd_erase(flash, CMD_S25FLXX_SE, offset, len); } +static struct spansion_spi_flash spsn_flash; + struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) { const struct spansion_spi_flash_params *params; @@ -231,11 +233,7 @@ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) return NULL; } - spsn = malloc(sizeof(struct spansion_spi_flash)); - if (!spsn) { - printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); - return NULL; - } + spsn = &spsn_flash; spsn->params = params; spsn->flash.spi = spi; @@ -243,7 +241,7 @@ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) spsn->flash.write = spansion_write; spsn->flash.erase = spansion_erase; - spsn->flash.read = spi_flash_cmd_read_fast; + spsn->flash.read = spi_flash_cmd_read_slow; spsn->flash.sector_size = params->page_size * params->pages_per_sector; spsn->flash.size = spsn->flash.sector_size * params->nr_sectors;

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Patch set updated for coreboot: adb7a24 SPI: Fix Eon support
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7934 -gerrit commit adb7a241b1da0893e4fa8f193b9ff22db30b658e Author: Marc Jones <marc.jones(a)se-eng.com> Date: Thu May 1 14:53:24 2014 -0600 SPI: Fix Eon support The Eon SPI25 code had a number of issues: - fix page write calculation - fix erase segment - fix id check - fix sector size - make commands EN25 generic This makes the code similar to other SPI25 devices used in coreboot. BUG=chrome-os-partner:25907 BRANCH=baytrail(rambi) TEST=Read and write MRC and ELOG on Glimmer with Eon device. Original-Change-Id: I7667eab28b850790d92a591c869788d51c26a56c Original-Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Original-Reviewed-on: https://chromium-review.googlesource.com/198323 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Commit-Queue: Marc Jones <marc.jones(a)se-eng.com> Original-Tested-by: Marc Jones <marc.jones(a)se-eng.com> (cherry picked from commit 2ee0da695bf6a6c6aedc0dd2b3a3b7c9c3165bca) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I8917e778cd62f3745189336d23c0c6118887d893 --- src/drivers/spi/eon.c | 90 +++++++++++++++++++++++++++------------------------ 1 file changed, 47 insertions(+), 43 deletions(-) diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 69869e9..2e5fa8c 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -1,5 +1,7 @@ /* * (C) Copyright 2010, ucRobotics Inc. + * Copyright (c) 2014, Sage Electronic Engineering, LLC + * . * Author: Chong Huang <chuang(a)ucrobotics.com> * Licensed under the GPL-2 or later. */ @@ -9,24 +11,24 @@ #include "spi_flash_internal.h" -/* EN25Q128-specific commands */ -#define CMD_EN25Q128_WREN 0x06 /* Write Enable */ -#define CMD_EN25Q128_WRDI 0x04 /* Write Disable */ -#define CMD_EN25Q128_RDSR 0x05 /* Read Status Register */ -#define CMD_EN25Q128_WRSR 0x01 /* Write Status Register */ -#define CMD_EN25Q128_READ 0x03 /* Read Data Bytes */ -#define CMD_EN25Q128_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_EN25Q128_PP 0x02 /* Page Program */ -#define CMD_EN25Q128_SE 0x20 /* Sector Erase */ -#define CMD_EN25Q128_BE 0xd8 /* Block Erase */ -#define CMD_EN25Q128_DP 0xb9 /* Deep Power-down */ -#define CMD_EN25Q128_RES 0xab /* Release from DP, and Read Signature */ - -#define EON_ID_EN25Q64 0x17 -#define EON_ID_EN25Q128 0x18 +/* EN25*-specific commands */ +#define CMD_EN25_WREN 0x06 /* Write Enable */ +#define CMD_EN25_WRDI 0x04 /* Write Disable */ +#define CMD_EN25_RDSR 0x05 /* Read Status Register */ +#define CMD_EN25_WRSR 0x01 /* Write Status Register */ +#define CMD_EN25_READ 0x03 /* Read Data Bytes */ +#define CMD_EN25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_EN25_PP 0x02 /* Page Program */ +#define CMD_EN25_SE 0x20 /* Sector Erase */ +#define CMD_EN25_BE 0xd8 /* Block Erase */ +#define CMD_EN25_DP 0xb9 /* Deep Power-down */ +#define CMD_EN25_RES 0xab /* Release from DP, and Read Signature */ + +#define EON_ID_EN25Q128 0x3018 +#define EON_ID_EN25Q64 0x3017 struct eon_spi_flash_params { - u8 idcode1; + u16 id; u16 page_size; u16 pages_per_sector; u16 sectors_per_block; @@ -47,7 +49,7 @@ static inline struct eon_spi_flash *to_eon_spi_flash(struct spi_flash *flash) static const struct eon_spi_flash_params eon_spi_flash_table[] = { { - .idcode1 = EON_ID_EN25Q128, + .id = EON_ID_EN25Q128, .page_size = 256, .pages_per_sector = 16, .sectors_per_block = 16, @@ -55,7 +57,7 @@ static const struct eon_spi_flash_params eon_spi_flash_table[] = { .name = "EN25Q128", }, { - .idcode1 = EON_ID_EN25Q64, + .id = EON_ID_EN25Q64, .page_size = 256, .pages_per_sector = 16, .sectors_per_block = 16, @@ -68,7 +70,6 @@ static int eon_write(struct spi_flash *flash, u32 offset, size_t len, const void *buf) { struct eon_spi_flash *eon = to_eon_spi_flash(flash); - unsigned long page_addr; unsigned long byte_addr; unsigned long page_size; size_t chunk_len; @@ -76,19 +77,25 @@ static int eon_write(struct spi_flash *flash, int ret = 0; u8 cmd[4]; - page_size = eon->params->page_size; - page_addr = offset / page_size; + page_size = 1 << eon->params->page_size; byte_addr = offset % page_size; flash->spi->rw = SPI_WRITE_FLAG; for (actual = 0; actual < len; actual += chunk_len) { chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = spi_crop_chunk(sizeof(cmd), chunk_len); - cmd[0] = CMD_EN25Q128_PP; - cmd[1] = page_addr >> 8; - cmd[2] = page_addr; - cmd[3] = byte_addr; + ret = spi_flash_cmd(flash->spi, CMD_EN25_WREN, NULL, 0); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + goto out; + } + + cmd[0] = CMD_EN25_PP; + cmd[1] = (offset >> 16) & 0xff; + cmd[2] = (offset >> 8) & 0xff; + cmd[3] = offset & 0xff; #if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, @@ -96,38 +103,35 @@ static int eon_write(struct spi_flash *flash, buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0); - if (ret < 0) { - printk(BIOS_WARNING, "SF: Enabling Write failed\n"); - break; - } - - ret = spi_flash_cmd_write(flash->spi, cmd, 4, + ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: EON Page Program failed\n"); - break; + goto out; } ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); - if (ret) - break; + if (ret) { + printk(BIOS_WARNING, "SF: EON Page Program timeout\n"); + goto out; + } - page_addr++; + offset += chunk_len; byte_addr = 0; } #if CONFIG_DEBUG_SPI_FLASH - printk(BIOS_SPEW, "SF: EON: Successfully programmed %zu bytes @ 0x%x\n", - len, offset); + printk(BIOS_SPEW, "SF: EON: Successfully programmed %zu bytes @ %#x\n", + len, (unsigned int)(offset - len)); #endif +out: return ret; } static int eon_erase(struct spi_flash *flash, u32 offset, size_t len) { - return spi_flash_cmd_erase(flash, CMD_EN25Q128_BE, offset, len); + return spi_flash_cmd_erase(flash, CMD_EN25_SE, offset, len); } struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode) @@ -138,12 +142,13 @@ struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode) for (i = 0; i < ARRAY_SIZE(eon_spi_flash_table); ++i) { params = &eon_spi_flash_table[i]; - if (params->idcode1 == idcode[2]) + if (params->id == ((idcode[1] << 8) | idcode[2])) break; } if (i == ARRAY_SIZE(eon_spi_flash_table)) { - printk(BIOS_WARNING, "SF: Unsupported EON ID %02x\n", idcode[1]); + printk(BIOS_WARNING, "SF: Unsupported EON ID %#02x%02x\n", + idcode[1], idcode[2]); return NULL; } @@ -160,8 +165,7 @@ struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode) eon->flash.write = eon_write; eon->flash.erase = eon_erase; eon->flash.read = spi_flash_cmd_read_fast; - eon->flash.sector_size = params->page_size * params->pages_per_sector - * params->sectors_per_block; + eon->flash.sector_size = params->page_size * params->pages_per_sector; eon->flash.size = params->page_size * params->pages_per_sector * params->nr_sectors;

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Patch set updated for coreboot: 67b4fdd SPI: Add Eon EN25S64 support.
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7935 -gerrit commit 67b4fddd515dc9fd8cd1021f5cedf6dcf1f66aef Author: Marc Jones <marc.jones(a)se-eng.com> Date: Thu May 1 14:54:11 2014 -0600 SPI: Add Eon EN25S64 support. BUG=chrome-os-partner:25907 BRANCH=baytrail(rambi) TEST=Read and write MRC and ELOG on Glimmer with Eon device. Original-Change-Id: If883ff6eb14dd49a06f57a01ca61661854ded78d Original-Reviewed-on: https://chromium-review.googlesource.com/198324 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Commit-Queue: Marc Jones <marc.jones(a)se-eng.com> Original-Tested-by: Marc Jones <marc.jones(a)se-eng.com> (cherry picked from commit 536c34c2d92178f4e62b8ca7cfffceaf80a305f6) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I199451ed2b29c55bfb5e1487afa8cf3b9978e63e --- src/drivers/spi/eon.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 2e5fa8c..684fb2e 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -26,6 +26,7 @@ #define EON_ID_EN25Q128 0x3018 #define EON_ID_EN25Q64 0x3017 +#define EON_ID_EN25S64 0x3817 struct eon_spi_flash_params { u16 id; @@ -64,6 +65,14 @@ static const struct eon_spi_flash_params eon_spi_flash_table[] = { .nr_sectors = 2048, .name = "EN25Q64", }, + { + .id = EON_ID_EN25S64, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_sectors = 2048, + .name = "EN25S64", + }, }; static int eon_write(struct spi_flash *flash,

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Patch set updated for coreboot: 0b3de36 drivers/spi: add support for another Spansion chip
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7931 -gerrit commit 0b3de36b6471270537133f3a0f106cf4b91c1633 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu May 1 15:50:43 2014 -0700 drivers/spi: add support for another Spansion chip Add the device ID definitions and properties for the SPI chip used on the AP148 board (Google Storm). BUG=chrome-os-partner:27784 TEST=manual . with the rest of the patches applied AP148 boots all the way to trying to read the payload. Original-Change-Id: I5a0e5c9d3cc9ea81bc5227c0fbc1d0a5fc7bec27 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197895 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit a7c69981b18ac6b1158273596b94df0def65963d) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I14e2f4f8f691a7db6ed596a3440914e08680867b --- src/drivers/spi/spansion.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index fba816a..e17f890 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -48,10 +48,12 @@ #define SPSN_ID_S25FL016A 0x0214 #define SPSN_ID_S25FL032A 0x0215 #define SPSN_ID_S25FL064A 0x0216 +#define SPSN_ID_S25FL128S 0x0219 #define SPSN_ID_S25FL128P 0x2018 #define SPSN_EXT_ID_S25FL128P_256KB 0x0300 #define SPSN_EXT_ID_S25FL128P_64KB 0x0301 #define SPSN_EXT_ID_S25FL032P 0x4d00 +#define SPSN_EXT_ID_S25FLXXS_64KB 0x4d01 struct spansion_spi_flash_params { u16 idcode1; @@ -123,6 +125,14 @@ static const struct spansion_spi_flash_params spansion_spi_flash_table[] = { .name = "S25FL128P_256K", }, { + .idcode1 = SPSN_ID_S25FL128S, + .idcode2 = SPSN_EXT_ID_S25FLXXS_64KB, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 512, + .name = "S25FL128S_256K", + }, + { .idcode1 = SPSN_ID_S25FL032A, .idcode2 = SPSN_EXT_ID_S25FL032P, .page_size = 256,

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Patch set updated for coreboot: 949ea07 drivers/spi: add support for another Spansion chip
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7931 -gerrit commit 949ea07b2a30ddfa82f9372956733f2fc78e3409 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu May 1 15:50:43 2014 -0700 drivers/spi: add support for another Spansion chip Add the device ID definitions and properties for the SPI chip used on the AP148 board (Google Storm). BUG=chrome-os-partner:27784 TEST=manual . with the rest of the patches applied AP148 boots all the way to trying to read the payload. Original-Change-Id: I5a0e5c9d3cc9ea81bc5227c0fbc1d0a5fc7bec27 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197895 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit a7c69981b18ac6b1158273596b94df0def65963d) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I14e2f4f8f691a7db6ed596a3440914e08680867b --- src/drivers/spi/spansion.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index fba816a..e17f890 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -48,10 +48,12 @@ #define SPSN_ID_S25FL016A 0x0214 #define SPSN_ID_S25FL032A 0x0215 #define SPSN_ID_S25FL064A 0x0216 +#define SPSN_ID_S25FL128S 0x0219 #define SPSN_ID_S25FL128P 0x2018 #define SPSN_EXT_ID_S25FL128P_256KB 0x0300 #define SPSN_EXT_ID_S25FL128P_64KB 0x0301 #define SPSN_EXT_ID_S25FL032P 0x4d00 +#define SPSN_EXT_ID_S25FLXXS_64KB 0x4d01 struct spansion_spi_flash_params { u16 idcode1; @@ -123,6 +125,14 @@ static const struct spansion_spi_flash_params spansion_spi_flash_table[] = { .name = "S25FL128P_256K", }, { + .idcode1 = SPSN_ID_S25FL128S, + .idcode2 = SPSN_EXT_ID_S25FLXXS_64KB, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 512, + .name = "S25FL128S_256K", + }, + { .idcode1 = SPSN_ID_S25FL032A, .idcode2 = SPSN_EXT_ID_S25FL032P, .page_size = 256,

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Patch set updated for coreboot: b7e487e drivers/spi: add support for another Spansion chip
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7931 -gerrit commit b7e487e7c352f7c5087650c46b62e83756e65f17 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu May 1 15:50:43 2014 -0700 drivers/spi: add support for another Spansion chip Add the device ID definitions and properties for the SPI chip used on the AP148 board. BUG=chrome-os-partner:27784 TEST=manual . with the rest of the patches applied AP148 boots all the way to trying to read the payload. Original-Change-Id: I5a0e5c9d3cc9ea81bc5227c0fbc1d0a5fc7bec27 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197895 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit a7c69981b18ac6b1158273596b94df0def65963d) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I14e2f4f8f691a7db6ed596a3440914e08680867b --- src/drivers/spi/spansion.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index fba816a..e17f890 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -48,10 +48,12 @@ #define SPSN_ID_S25FL016A 0x0214 #define SPSN_ID_S25FL032A 0x0215 #define SPSN_ID_S25FL064A 0x0216 +#define SPSN_ID_S25FL128S 0x0219 #define SPSN_ID_S25FL128P 0x2018 #define SPSN_EXT_ID_S25FL128P_256KB 0x0300 #define SPSN_EXT_ID_S25FL128P_64KB 0x0301 #define SPSN_EXT_ID_S25FL032P 0x4d00 +#define SPSN_EXT_ID_S25FLXXS_64KB 0x4d01 struct spansion_spi_flash_params { u16 idcode1; @@ -123,6 +125,14 @@ static const struct spansion_spi_flash_params spansion_spi_flash_table[] = { .name = "S25FL128P_256K", }, { + .idcode1 = SPSN_ID_S25FL128S, + .idcode2 = SPSN_EXT_ID_S25FLXXS_64KB, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 512, + .name = "S25FL128S_256K", + }, + { .idcode1 = SPSN_ID_S25FL032A, .idcode2 = SPSN_EXT_ID_S25FL032P, .page_size = 256,

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Patch set updated for coreboot: 97c9f34 rtc: make ALTCENTURY a KCONFIG option.
by Marc Jones 30 Dec '14

30 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7987 -gerrit commit 97c9f346da52c00a58cddc1e14664c1e9be18ae8 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Apr 30 21:31:44 2014 -0700 rtc: make ALTCENTURY a KCONFIG option. The availability of "ALTCENTURY" is now set through a kconfig variable so it can be available to the RTC driver without having to have a specialized interface. BUG=None TEST=Built and booted on Link with the event log code modified to use the RTC interface. Verified that the event times were accurate. BRANCH=nyan Original-Change-Id: Ifa807898e583254e57167fd44932ea86627a02ee Original-Signed-off-by: Gabe Black <gabeblack(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197795 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: Gabe Black <gabeblack(a)chromium.org> Original-Commit-Queue: Gabe Black <gabeblack(a)chromium.org> This is the second half the following patch. (cherry picked from commit 9e0fd75142d29afe34f6c6b9ce0099f478ca5a93) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I8e871f31c3d4be7676abf9454ca90808d1ddca03 --- src/drivers/pc80/Kconfig | 5 +++++ src/drivers/pc80/mc146818rtc.c | 22 +++++++++++----------- src/include/pc80/mc146818rtc.h | 5 +---- src/include/rtc.h | 4 ++-- src/southbridge/amd/agesa/hudson/lpc.c | 2 +- src/southbridge/amd/cimx/sb700/late.c | 2 +- src/southbridge/amd/cimx/sb800/late.c | 2 +- src/southbridge/amd/cimx/sb900/late.c | 2 +- src/southbridge/amd/pi/avalon/lpc.c | 2 +- src/southbridge/amd/sb600/lpc.c | 2 +- src/southbridge/amd/sb700/lpc.c | 2 +- src/southbridge/amd/sb800/lpc.c | 2 +- 12 files changed, 27 insertions(+), 25 deletions(-) diff --git a/src/drivers/pc80/Kconfig b/src/drivers/pc80/Kconfig index 5b05f46..928fae4 100644 --- a/src/drivers/pc80/Kconfig +++ b/src/drivers/pc80/Kconfig @@ -27,3 +27,8 @@ config DRIVERS_MC146818 bool default y if ARCH_X86 default n if !ARCH_X86 + +config DRIVERS_RTC_HAS_ALTCENTURY + bool "The RTC supports alt century" + depends on DRIVERS_MC146818 + default y diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index 9111ac8..2b8337a 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -32,7 +32,7 @@ #endif -static void cmos_reset_date(u8 has_century) +static void cmos_reset_date(void) { /* Now setup a default date equals to the build date */ struct rtc_time time = { @@ -44,7 +44,7 @@ static void cmos_reset_date(u8 has_century) .year = 2000 + bcd2bin(coreboot_build_date.year), .wday = bcd2bin(coreboot_build_date.weekday) }; - rtc_set(&time, has_century); + rtc_set(&time); } #if CONFIG_USE_OPTION_TABLE @@ -122,7 +122,7 @@ void cmos_init(int invalid) cmos_write(0, i); #endif if (cmos_invalid) - cmos_reset_date(RTC_HAS_NO_ALTCENTURY); + cmos_reset_date(); printk(BIOS_WARNING, "RTC:%s%s%s%s\n", invalid?" Clear requested":"", @@ -325,12 +325,13 @@ enum cb_err set_option(const char *name, void *value) * hurts some OSes. Even if we don't set USE_OPTION_TABLE, we need * to make sure the date is valid. */ -void cmos_check_update_date(u8 has_century) +void cmos_check_update_date() { u8 year, century; /* Note: Need to check if the hardware supports RTC_CLK_ALTCENTURY. */ - century = has_century ? cmos_read(RTC_CLK_ALTCENTURY) : 0; + century = CONFIG_DRIVERS_RTC_HAS_ALTCENTURY ? + cmos_read(RTC_CLK_ALTCENTURY) : 0; year = cmos_read(RTC_CLK_YEAR); /* @@ -339,25 +340,24 @@ void cmos_check_update_date(u8 has_century) * if the date is valid. */ if (century > 0x99 || year > 0x99) /* Invalid date */ - cmos_reset_date(has_century); + cmos_reset_date(); } -int rtc_set(const struct rtc_time *time, u8 has_century) -{ +int rtc_set(const struct rtc_time *time){ cmos_write(bin2bcd(time->sec), RTC_CLK_SECOND); cmos_write(bin2bcd(time->min), RTC_CLK_MINUTE); cmos_write(bin2bcd(time->hour), RTC_CLK_HOUR); cmos_write(bin2bcd(time->mday), RTC_CLK_DAYOFMONTH); cmos_write(bin2bcd(time->mon), RTC_CLK_MONTH); cmos_write(bin2bcd(time->year % 100), RTC_CLK_YEAR); - if (has_century) + if (CONFIG_DRIVERS_RTC_HAS_ALTCENTURY) cmos_write(bin2bcd(time->year / 100), RTC_CLK_ALTCENTURY); cmos_write(bin2bcd(time->wday + 1), RTC_CLK_DAYOFWEEK); return 0; } -int rtc_get(struct rtc_time *time, u8 has_century) +int rtc_get(struct rtc_time *time) { time->sec = bcd2bin(cmos_read(RTC_CLK_SECOND)); time->min = bcd2bin(cmos_read(RTC_CLK_MINUTE)); @@ -365,7 +365,7 @@ int rtc_get(struct rtc_time *time, u8 has_century) time->mday = bcd2bin(cmos_read(RTC_CLK_DAYOFMONTH)); time->mon = bcd2bin(cmos_read(RTC_CLK_MONTH)); time->year = bcd2bin(cmos_read(RTC_CLK_YEAR)); - if (has_century) + if (CONFIG_DRIVERS_RTC_HAS_ALTCENTURY) time->year += bcd2bin(cmos_read(RTC_CLK_ALTCENTURY)) * 100; else time->year += 2000; diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 3d65909..90ae7ae 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -94,9 +94,6 @@ #define RTC_CLK_YEAR 9 #define RTC_CLK_ALTCENTURY 0x32 -#define RTC_HAS_ALTCENTURY 1 -#define RTC_HAS_NO_ALTCENTURY 0 - /* On PCs, the checksum is built only over bytes 16..45 */ #define PC_CKS_RANGE_START 16 #define PC_CKS_RANGE_END 45 @@ -173,7 +170,7 @@ static inline void cmos_write32(u8 offset, u32 value) #if !defined(__ROMCC__) void cmos_init(int invalid); -void cmos_check_update_date(u8 has_century); +void cmos_check_update_date(void); #if CONFIG_USE_OPTION_TABLE enum cb_err set_option(const char *name, void *val); enum cb_err get_option(void *dest, const char *name); diff --git a/src/include/rtc.h b/src/include/rtc.h index ed32b69..ba9a9c3 100644 --- a/src/include/rtc.h +++ b/src/include/rtc.h @@ -31,7 +31,7 @@ struct rtc_time int wday; }; -int rtc_set(const struct rtc_time *time, u8 has_century); -int rtc_get(struct rtc_time *time, u8 has_century); +int rtc_set(const struct rtc_time *time); +int rtc_get(struct rtc_time *time); #endif /* _RTC_H_ */ diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 836966e..b784fc4 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -71,7 +71,7 @@ static void lpc_init(device_t dev) byte |= 1 << 0 | 1 << 3; pci_write_config8(dev, 0xBB, byte); - cmos_check_update_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(); /* Initialize the real time clock. * The 0 argument tells cmos_init not to diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c index 9c70482..3fa6940 100644 --- a/src/southbridge/amd/cimx/sb700/late.c +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -81,7 +81,7 @@ static void lpc_init(device_t dev) { printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - Start.\n"); - cmos_check_update_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(); /* Initialize the real time clock. * The 0 argument tells cmos_init not to diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 9c4047f..d7f22d3 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -132,7 +132,7 @@ static void lpc_init(device_t dev) { printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n"); - cmos_check_update_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(); /* Initialize the real time clock. * The 0 argument tells cmos_init not to diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index 6f6a501..e9f5ad6 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -103,7 +103,7 @@ static void lpc_init(device_t dev) printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n"); /* SB Configure HPET base and enable bit */ //- hpetInit(sb_config, &(sb_config->BuildParameters)); - cmos_check_update_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(); /* Initialize the real time clock. * The 0 argument tells cmos_init not to diff --git a/src/southbridge/amd/pi/avalon/lpc.c b/src/southbridge/amd/pi/avalon/lpc.c index 1f60bc4..7b54cc3 100644 --- a/src/southbridge/amd/pi/avalon/lpc.c +++ b/src/southbridge/amd/pi/avalon/lpc.c @@ -70,7 +70,7 @@ static void lpc_init(device_t dev) byte |= 1 << 0 | 1 << 3; pci_write_config8(dev, 0xBB, byte); - cmos_check_update_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(); /* Initialize the real time clock. * The 0 argument tells cmos_init not to diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index acee69d..dc2f31b 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -63,7 +63,7 @@ static void lpc_init(device_t dev) byte &= ~(1 << 1); pci_write_config8(dev, 0x78, byte); - cmos_check_update_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(); } static void sb600_lpc_read_resources(device_t dev) diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 26478b7..8ebc765 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -90,7 +90,7 @@ static void lpc_init(device_t dev) } #endif - cmos_check_update_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(); } void backup_top_of_ram(uint64_t ramtop) diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index f862a97..87c09a2 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -74,7 +74,7 @@ static void lpc_init(device_t dev) byte |= 1 << 0 | 1 << 3; pci_write_config8(dev, 0xBB, byte); - cmos_check_update_date(RTC_HAS_ALTCENTURY); + cmos_check_update_date(); } static void sb800_lpc_read_resources(device_t dev)

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coreboot-gerrit December 2014