Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4914
-gerrit
commit e38d47de5ab17ce0ce92bb639fd628eb6c8edd49
Author: Shawn Nematbakhsh <shawnn(a)chromium.org>
Date: Mon Oct 28 16:43:17 2013 -0700
rambi: Enable SATA port
Enable first SATA port in Rambi device tree.
BUG=chrome-os-partner:23643
TEST=TEST=Manual, in dev mode. Verify on rambi that SATA disk is
detected, and kernel is found + booted.
Change-Id: Ic0cb5f9ff17ca0f6cc7941f203b9338df200811d
Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174916
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/rambi/devicetree.cb | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index 3086ebf..e7f86ce 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -1,4 +1,10 @@
chip soc/intel/baytrail
+
+ # SATA port enable mask (2 ports)
+ register "sata_port_map" = "0x1"
+ register "sata_ahci" = "0x1"
+ register "ide_legacy_combined" = "0x0"
+
device cpu_cluster 0 on
device lapic 0 on end
end
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4912
-gerrit
commit 911034d50e2f16a19b68aa2155d1b9eb73e0f4a3
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Oct 29 17:00:07 2013 -0500
rambi: add all on-board devices
Add the on-board devices in the SoC to the device tree.
Also, disable the unused devices aside from TXE and HDA.
Those particular devices cause the system to shut down
when they are disabled.
BUG=chrome-os-partner:22871
BRANCH=None
TEST=Built and booted through depthcharge. Noted the calls to the
southcluster disable function.
Change-Id: I482c1c9609833054aeb2948144af54b57d3df086
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174645
Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
---
src/mainboard/google/rambi/devicetree.cb | 34 +++++++++++++++++++++++++++++---
1 file changed, 31 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index c6ea97c..3086ebf 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -3,8 +3,36 @@ chip soc/intel/baytrail
device lapic 0 on end
end
device domain 0 on
- device pci 00.0 on end # SoC router
- device pci 02.0 on end # GFX
- device pci 1f.0 on end # LPC Bridge
+ device pci 00.0 on end # SoC router
+ device pci 02.0 on end # GFX
+ device pci 11.0 off end # SDIO
+ device pci 12.0 on end # SD
+ device pci 13.0 on end # SATA
+ device pci 14.0 on end # XHCI
+ device pci 15.0 on end # LPE
+ device pci 17.0 on end # MMC
+ device pci 18.0 on end # SIO_DMA1
+ device pci 18.1 on end # I2C1
+ device pci 18.2 on end # I2C2
+ device pci 18.3 off end # I2C3
+ device pci 18.4 off end # I2C4
+ device pci 18.5 on end # I2C5
+ device pci 18.6 on end # I2C6
+ device pci 18.7 off end # I2C7
+ device pci 1a.0 on end # TXE
+ device pci 1b.0 on end # HDA
+ device pci 1c.0 on end # PCIE_PORT1
+ device pci 1c.1 on end # PCIE_PORT2
+ device pci 1c.2 off end # PCIE_PORT3
+ device pci 1c.3 off end # PCIE_PORT4
+ device pci 1d.0 on end # EHCI
+ device pci 1e.0 on end # SIO_DMA2
+ device pci 1e.1 off end # PWM1
+ device pci 1e.2 off end # PWM2
+ device pci 1e.3 off end # HSUART1
+ device pci 1e.4 on end # HSUART2
+ device pci 1e.5 on end # SPI
+ device pci 1f.0 on end # LPC Bridge
+ device pci 1f.3 off end # SMBus
end
end
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4917
-gerrit
commit accff7872adbf3580b048d76642c94ce4d124d98
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Oct 30 14:36:11 2013 -0500
baytrail: fix uninitialized acpi structures
The callers of the following functions assume the storage
area provided by the pointers is initialized. That's not the
case as these were just place holders.
- void acpi_create_intel_hpet(acpi_hpet_t * hpet);
- void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
To fix this properly initialize the hpet entry, and just remove
the serialio_ssdt function entirely.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted through depthcharge on rambi. Noted no more
ACPI errors relating to invalid length.
Change-Id: If56ab033562ef2d755e9c9de42f507c95d291aba
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174716
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/mainboard/google/rambi/acpi_tables.c | 7 ----
src/soc/intel/baytrail/Makefile.inc | 1 +
src/soc/intel/baytrail/acpi.c | 59 ++++++++++++++++++++++++++++++++
src/soc/intel/baytrail/baytrail/acpi.h | 1 -
src/soc/intel/baytrail/baytrail/iomap.h | 1 +
src/soc/intel/baytrail/placeholders.c | 4 ---
6 files changed, 61 insertions(+), 12 deletions(-)
diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c
index 3723021..0b96228 100644
--- a/src/mainboard/google/rambi/acpi_tables.c
+++ b/src/mainboard/google/rambi/acpi_tables.c
@@ -274,13 +274,6 @@ unsigned long write_acpi_tables(unsigned long start)
acpi_add_table(rsdp, ssdt);
ALIGN_CURRENT;
- printk(BIOS_DEBUG, "ACPI: * SSDT2\n");
- ssdt = (acpi_header_t *)current;
- acpi_create_serialio_ssdt(ssdt);
- current += ssdt->length;
- acpi_add_table(rsdp, ssdt);
- ALIGN_CURRENT;
-
printk(BIOS_DEBUG, "current = %lx\n", current);
printk(BIOS_INFO, "ACPI: done.\n");
return current;
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 91fbc64..ed2764c 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -34,6 +34,7 @@ ramstage-y += smm.c
ramstage-y += southcluster.c
ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c
ramstage-y += sata.c
+ramstage-y += acpi.c
# Remove as ramstage gets fleshed out
ramstage-y += placeholders.c
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
new file mode 100644
index 0000000..a865a49
--- /dev/null
+++ b/src/soc/intel/baytrail/acpi.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <types.h>
+#include <string.h>
+
+#include <baytrail/acpi.h>
+#include <baytrail/iomap.h>
+
+void acpi_create_intel_hpet(acpi_hpet_t * hpet)
+{
+ acpi_header_t *header = &(hpet->header);
+ acpi_addr_t *addr = &(hpet->addr);
+
+ memset((void *) hpet, 0, sizeof(acpi_hpet_t));
+
+ /* fill out header fields */
+ memcpy(header->signature, "HPET", 4);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+
+ header->length = sizeof(acpi_hpet_t);
+ header->revision = 1;
+
+ /* fill out HPET address */
+ addr->space_id = 0; /* Memory */
+ addr->bit_width = 64;
+ addr->bit_offset = 0;
+ addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff;
+ addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32;
+
+ hpet->id = 0x8086a201; /* Intel */
+ hpet->number = 0x00;
+ hpet->min_tick = 0x0080;
+
+ header->checksum =
+ acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
+}
+
diff --git a/src/soc/intel/baytrail/baytrail/acpi.h b/src/soc/intel/baytrail/baytrail/acpi.h
index 917eb26..b269e44 100644
--- a/src/soc/intel/baytrail/baytrail/acpi.h
+++ b/src/soc/intel/baytrail/baytrail/acpi.h
@@ -23,7 +23,6 @@
#include <arch/acpi.h>
void acpi_create_intel_hpet(acpi_hpet_t * hpet);
-void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
#endif /* _BAYTRAIL_ACPI_H_ */
diff --git a/src/soc/intel/baytrail/baytrail/iomap.h b/src/soc/intel/baytrail/baytrail/iomap.h
index 9fc8da7..fa34105 100644
--- a/src/soc/intel/baytrail/baytrail/iomap.h
+++ b/src/soc/intel/baytrail/baytrail/iomap.h
@@ -30,6 +30,7 @@
#define MPHY_BASE_ADDRESS 0xfef00000
#define PUNIT_BASE_ADDRESS 0xfed05000
#define RCBA_BASE_ADDRESS 0xfed1c000
+#define HPET_BASE_ADDRESS 0xfed00000
/* IO Port base */
#define ACPI_BASE_ADDRESS 0x0400
diff --git a/src/soc/intel/baytrail/placeholders.c b/src/soc/intel/baytrail/placeholders.c
index 63f0fb3..5267927 100644
--- a/src/soc/intel/baytrail/placeholders.c
+++ b/src/soc/intel/baytrail/placeholders.c
@@ -7,10 +7,6 @@
void generate_cpu_entries(void) {}
-void acpi_create_intel_hpet(acpi_hpet_t * hpet) {}
-
-void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {}
-
unsigned long acpi_fill_mcfg(unsigned long current) { return current; }
void smm_init(void) {}
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4898
-gerrit
commit 416a3a7f6305f7c88f4a4e731c90e63da581b374
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Oct 24 10:21:43 2013 -0500
baytrail: add support to run reference code blob
The reference code blog is needed to bootstrap
certain pieces of hardware in bay trail. Provide
the ability to run reference code by loading
the reference code as an rmodule.
Note that support for vboot verification and S3
resume is omitted from this commit.
BUG=chrome-os-partner:22866
BRANCH=None
TEST=Built and booted with refcode loading.
Change-Id: I30334db441a57f4d87b4de6fca0a9a48e1c05c05
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174426
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/baytrail/Makefile.inc | 1 +
src/soc/intel/baytrail/baytrail/efi_wrapper.h | 50 ++++++++++++++++++++++
src/soc/intel/baytrail/baytrail/ramstage.h | 5 +++
src/soc/intel/baytrail/ramstage.c | 3 ++
src/soc/intel/baytrail/refcode.c | 60 +++++++++++++++++++++++++++
5 files changed, 119 insertions(+)
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index f913f0c..455f015 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -31,6 +31,7 @@ smm-y += pmutil.c
smm-y += smihandler.c
ramstage-y += smm.c
ramstage-y += southcluster.c
+ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c
# Remove as ramstage gets fleshed out
ramstage-y += placeholders.c
diff --git a/src/soc/intel/baytrail/baytrail/efi_wrapper.h b/src/soc/intel/baytrail/baytrail/efi_wrapper.h
new file mode 100644
index 0000000..6682f95
--- /dev/null
+++ b/src/soc/intel/baytrail/baytrail/efi_wrapper.h
@@ -0,0 +1,50 @@
+/*
+ * PEI EFI entry point
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Google Inc. nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __EFI_WRAPPER_H__
+#define __EFI_WRAPPER_H__
+
+#define EFI_WRAPPER_VER 1
+
+/* Provide generic x86 calling conventions. */
+#define ABI_X86 __attribute((regparm(0)))
+
+/* Errors returned by the EFI wrapper. */
+enum efi_wrapper_error {
+ INVALID_VER = -1,
+};
+
+struct efi_wrapper_params {
+ /* Mainboard Inputs */
+ int version;
+
+ void ABI_X86 (*console_out)(unsigned char byte);
+} __attribute__((packed));
+
+typedef int ABI_X86 (*efi_wrapper_entry_t)(struct efi_wrapper_params *);
+#endif
diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h
index 790b8c6..eaa8f6b 100644
--- a/src/soc/intel/baytrail/baytrail/ramstage.h
+++ b/src/soc/intel/baytrail/baytrail/ramstage.h
@@ -27,6 +27,11 @@
void baytrail_init_pre_device(void);
void baytrail_init_cpus(device_t dev);
void set_max_freq(void);
+#if CONFIG_HAVE_REFCODE_BLOB
+void baytrail_run_reference_code(void);
+#else
+static inline void baytrail_run_reference_code(void) {}
+#endif
extern struct pci_operations soc_pci_ops;
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index 229e367..896ecfe 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -113,6 +113,9 @@ void baytrail_init_pre_device(void)
/* Allow for SSE instructions to be executed. */
write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT);
+ /* Run reference code. */
+ baytrail_run_reference_code();
+
/* Get GPIO initial states from mainboard */
config = mainboard_get_gpios();
setup_soc_gpios(config);
diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c
new file mode 100644
index 0000000..59e3c4c
--- /dev/null
+++ b/src/soc/intel/baytrail/refcode.c
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <rmodule.h>
+
+#include <baytrail/ramstage.h>
+#include <baytrail/efi_wrapper.h>
+
+static void ABI_X86 send_to_console(unsigned char b)
+{
+ console_tx_byte(b);
+}
+
+void baytrail_run_reference_code(void)
+{
+ int ret;
+ efi_wrapper_entry_t entry;
+ struct efi_wrapper_params wrp = {
+ .version = EFI_WRAPPER_VER,
+ .console_out = send_to_console,
+ };
+ struct rmod_stage_load refcode = {
+ .cbmem_id = CBMEM_ID_REFCODE,
+ .name = "fallback/refcode",
+ };
+
+ if (rmodule_stage_load_from_cbfs(&refcode) || refcode.entry == NULL) {
+ printk(BIOS_DEBUG, "Error loading reference code.\n");
+ return;
+ }
+
+ entry = refcode.entry;
+
+ /* Call into reference code. */
+ ret = entry(&wrp);
+
+ if (ret != 0) {
+ printk(BIOS_DEBUG, "Reference code returned %d\n", ret);
+ return;
+ }
+}
+