Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4895
-gerrit
commit 0db2c7c965b57b712a50eaad5661b48a31f5ae5e
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Oct 24 08:55:51 2013 -0500
x86: add HAVE_REFCODE_BLOB option
In order to incorporate external blobs into
CBFS besides MRC have a notion of a reference code
blob. By selecting HAVE_REFCODE_BLOB and providing
the file name the refcode blob will be added to
cbfs as a stage file.
BUG=chrome-os-partner:22866
BRANCH=None
TEST=Using this option and other patches able to build,
boot, and run blob code.
Change-Id: I472604d77f4cb48f286b5a76b25d8b5bfb0c7780
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174423
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/Kconfig | 17 +++++++++++++++++
src/arch/x86/Makefile.inc | 3 +++
2 files changed, 20 insertions(+)
diff --git a/src/Kconfig b/src/Kconfig
index 7492e22..31a41ab 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -439,6 +439,23 @@ config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
The relocated ramstage is saved in an area specified by the
by the board and/or chipset.
+config HAVE_REFCODE_BLOB
+ depends on ARCH_X86
+ bool "An external reference code blob should be put into cbfs."
+ default n
+ help
+ The reference code blob will be placed into cbfs.
+
+if HAVE_REFCODE_BLOB
+
+config REFCODE_BLOB_FILE
+ string "Path and filename to reference code blob."
+ default "refcode.elf"
+ help
+ The path and filename to the file to be added to cbfs.
+
+endif # HAVE_REFCODE_BLOB
+
config HAVE_ACPI_TABLES
bool
help
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 2ade820..80e731f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -136,6 +136,9 @@ endif
ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y)
$(CBFSTOOL) $@.tmp add-stage -f $(VBOOT_STUB_ELF) -n $(CONFIG_CBFS_PREFIX)/vboot -c $(CBFS_COMPRESS_FLAG)
endif
+ifeq ($(CONFIG_HAVE_REFCODE_BLOB),y)
+ $(CBFSTOOL) $@.tmp add-stage -f $(CONFIG_REFCODE_BLOB_FILE) -n $(CONFIG_CBFS_PREFIX)/refcode -c $(CBFS_COMPRESS_FLAG)
+endif
ifeq ($(CONFIG_PXE_ROM),y)
$(CBFSTOOL) $@.tmp add -f $(CONFIG_PXE_ROM_FILE) -n pci$(CONFIG_PXE_ROM_ID).rom -t raw
endif
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4885
-gerrit
commit c893168384dbfc525791405ed873c1f5535a7fed
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Oct 16 09:21:55 2013 -0700
rambi: disable internal pullups on ram_id[2:0]
The ram_id[2:0] signals have stuffing options for pull up/down
with values of 10K. However, the default pulldown values for these
pads are 20K. Therefore, one can't read a high value because of
the high voltage threshold is 0.65 * Vref. Therefore the high
signals are marginal at best.
Fix this issue by disabling the internal pull for the pads connected
to ram_id[2:0].
BUG=chrome-os-partner:23350
BRANCH=None
TEST=Built and checked that ram_id[2:0] is properly read now.
Change-Id: Ib414d5798b472574337d1b71b87a4cf92f40c762
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173211
Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Reviewed-by: Bernie Thompson <bhthompson(a)chromium.org>
---
src/mainboard/google/rambi/romstage.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c
index d15a21d..369ebad 100644
--- a/src/mainboard/google/rambi/romstage.c
+++ b/src/mainboard/google/rambi/romstage.c
@@ -37,14 +37,29 @@
#define GPIO_SSUS_38_PAD 50
#define GPIO_SSUS_39_PAD 58
+static inline void disable_internal_pull(int pad)
+{
+ const int pull_mask = ~(0xf << 7);
+ write32(ssus_pconf0(pad), read32(ssus_pconf0(pad)) & pull_mask);
+}
+
static void *get_spd_pointer(char *spd_file_content, int total_spds)
{
int ram_id = 0;
+ /* The ram_id[2:0] pullups on rambi are too large for the default 20K
+ * pulldown on the pad. Therefore, disable the internal pull resistor to
+ * read high values correctly. */
+ disable_internal_pull(GPIO_SSUS_37_PAD);
+ disable_internal_pull(GPIO_SSUS_38_PAD);
+ disable_internal_pull(GPIO_SSUS_39_PAD);
+
ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0);
ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1);
ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2);
+ printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds);
+
if (ram_id >= total_spds)
return NULL;
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4887
-gerrit
commit b5f3190f9db2d46545e72cce4b3946aba0238863
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Oct 21 12:11:17 2013 -0500
rambi: add BSP lapic device
There's some baked in assumptions internal to coreboot
that the BSP's cpu device exists in the device tree. Therefore
provide one in the device tree.
BUG=chrome-os-partner:22862
BRANCH=None
TEST=Compiled and booted with other changes.
Change-Id: I22ba10964760ee8efbc5bbd5d4ce65daf31b3839
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173702
---
src/mainboard/google/rambi/devicetree.cb | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index 376aab6..c6ea97c 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -1,5 +1,7 @@
chip soc/intel/baytrail
- device cpu_cluster 0 on end
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
device domain 0 on
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX