Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4931
-gerrit
commit 16ee1010bb7eaa3d6549cbd42c4bf306576134b1
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Nov 1 13:35:32 2013 -0700
rambi: Enable USB boot with EHCI controller
This adds the EHCI driver back to libpayload and configures
the devicetree to route ports to EHCI.
This is hopefully just temporary until the issues with XHCI
can be worked out.
BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot from USB on rambi
Change-Id: I0549661f5e5fd83477f4839a05e7e21175b24b64
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175513
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/rambi/devicetree.cb | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index 66d98ed..af115a6 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -5,6 +5,24 @@ chip soc/intel/baytrail
register "sata_ahci" = "0x1"
register "ide_legacy_combined" = "0x0"
+ # Route USB ports to XHCI -- DISABLED UNTIL XHCI WORKS
+ register "usb_route_to_xhci" = "0"
+
+ # USB Port Disable Mask
+ register "usb2_port_disable_mask" = "0x0"
+ register "usb3_port_disable_mask" = "0x0"
+
+ # USB PHY settings
+ # TODO: These values are from Baytrail and need tuned for Rambi board
+ register "usb2_per_port_lane0" = "0x00049a09"
+ register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+ register "usb2_per_port_lane1" = "0x00049a09"
+ register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+ register "usb2_per_port_lane2" = "0x00049209"
+ register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+ register "usb2_per_port_lane3" = "0x00049a09"
+ register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
device cpu_cluster 0 on
device lapic 0 on end
end
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4926
-gerrit
commit 97ea96eb2ca314f4bfb5e2dd5cc89c124e794da1
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Oct 30 17:07:46 2013 -0500
baytrail: HDA function disable workaround
Parts of the audio path are common between the HDA and LPE.
However, those parts are power-controlled by the D-state of
the HDA device. Therefore, one cannot put the HDA into D3Hot
because those audio paths will be shutdown.
BUG=chrome-os-partner:22871
BRANCH=None
TEST=Built and booted through depthcharge. Disabling HDA still
causes a shutdown when performing warm reset, however I
was able to verify the magic sequence was being performed.
Change-Id: I3b01356d85a4b7b902bd896b8eb9e7bc509fcc42
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175491
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/baytrail/baytrail/iomap.h | 1 +
src/soc/intel/baytrail/southcluster.c | 27 +++++++++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/src/soc/intel/baytrail/baytrail/iomap.h b/src/soc/intel/baytrail/baytrail/iomap.h
index fa34105..d46a0fe 100644
--- a/src/soc/intel/baytrail/baytrail/iomap.h
+++ b/src/soc/intel/baytrail/baytrail/iomap.h
@@ -31,6 +31,7 @@
#define PUNIT_BASE_ADDRESS 0xfed05000
#define RCBA_BASE_ADDRESS 0xfed1c000
#define HPET_BASE_ADDRESS 0xfed00000
+#define TEMP_BASE_ADDRESS 0xfd000000
/* IO Port base */
#define ACPI_BASE_ADDRESS 0x0400
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index 40d135b..ece99bf 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -217,10 +217,37 @@ static inline void set_d3hot_bits(device_t dev, int offset)
pci_write_config8(dev, offset + 4, reg8);
}
+/* Parts of the audio subsystem are powered by the HDA device. Therefore, one
+ * cannot put HDA into D3Hot. Instead perform this workaround to make some of
+ * the audio paths work for LPE audio. */
+static void hda_work_around(device_t dev)
+{
+ unsigned long gctl = TEMP_BASE_ADDRESS + 0x8;
+
+ /* Need to set magic register 0x43 to 0xd7 in config space. */
+ pci_write_config8(dev, 0x43, 0xd7);
+
+ /* Need to set bit 0 of GCTL to take the device out of reset. However,
+ * that requires setting up the 64-bit BAR. */
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS);
+ pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
+ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+ write32(gctl, read32(gctl) | 0x1);
+ pci_write_config8(dev, PCI_COMMAND, 0);
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
+}
+
static int place_device_in_d3hot(device_t dev)
{
unsigned offset;
+ /* Parts of the HDA block are used for LPE audio as well.
+ * Therefore assume the HDA will never be put into D3Hot. */
+ if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) {
+ hda_work_around(dev);
+ return 0;
+ }
+
offset = pci_find_capability(dev, PCI_CAP_ID_PM);
if (offset != 0) {
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4925
-gerrit
commit 312a729810bdb7d3fa18d3f04760d29944f28c8e
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Oct 30 17:08:59 2013 -0500
baytrail: allow function disable on TXE
Previously it was not known how to put the TXE pci device
into D3Hot. It's been disseminated that this is not a requirement
for disabling the TXE pci device in the function disable register.
Therefore, allow this by returning 0 from place_device_in_d3hot().
BUG=chrome-os-partner:22871
BRANCH=None
TEST=Temporarily set TXE to be disabled. Noted FUNC_DIS was being
set accordingly.
Change-Id: Ibf537bf8ba718859591dc89bdf41e57c1ea9d836
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175490
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/baytrail/southcluster.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index a3a1a22..40d135b 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -264,6 +264,8 @@ static int place_device_in_d3hot(device_t dev)
offset = 0x50;
break;
DEV_CASE(TXE):
+ /* TXE cannot be placed in D3Hot. */
+ return 0;
break;
DEV_CASE(PCIE_PORT1):
DEV_CASE(PCIE_PORT2):
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4904
-gerrit
commit 38eff61779d83240ec8837f367a31e2230f8bdd9
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Oct 28 11:20:35 2013 -0500
baytrail: initialize chromeos EC if present in romstage
The EC needs to be initialized early in romstage. Therefore
perform the call after console has been initialized in order to
view any messages that the code may spit out.
BUG=chrome-os-partner:23387
BRANCH=None
TEST=Built and booted with recovery mode and EC in RW. Noted that
system reboots the EC.
Change-Id: I35aa3ea4aa3dbd9bd806b6498e227f45ceebd7a1
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174713
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/baytrail/romstage/romstage.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 10028ca..e833dbd 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -25,6 +25,9 @@
#include <console/console.h>
#include <cbmem.h>
#include <cpu/x86/mtrr.h>
+#if CONFIG_EC_GOOGLE_CHROMEEC
+#include <ec/google/chromeec/ec.h>
+#endif
#include <ramstage_cache.h>
#include <ramstage_cache.h>
#include <romstage_handoff.h>
@@ -126,6 +129,11 @@ void * asmlinkage romstage_main(unsigned long bist,
gfx_init();
+#if CONFIG_EC_GOOGLE_CHROMEEC
+ /* Ensure the EC is in the right mode for recovery */
+ google_chromeec_early_init();
+#endif
+
/* Call into mainboard. */
mainboard_romstage_entry(&rp);