Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4961
-gerrit
commit 46bcb377f8bb9289b9efc9f66f98c0f23ccdf043
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Nov 11 15:01:39 2013 -0600
rambi: disable HDA device
For some reason HDA can now be disabled. It's unclear what changes
in the baytrail code allowed this to happen, sadly.
BUG=chrome-os-partner:22871
BRANCH=None
TEST=Noted hda is not in lspci.
Change-Id: I64e2560533be6f701fa66cd53c906b62b09012ed
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176394
---
src/mainboard/google/rambi/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index a5fe37e..88785c0 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -44,7 +44,7 @@ chip soc/intel/baytrail
device pci 18.6 on end # I2C6
device pci 18.7 off end # I2C7
device pci 1a.0 on end # TXE
- device pci 1b.0 on end # HDA
+ device pci 1b.0 off end # HDA
device pci 1c.0 on end # PCIE_PORT1
device pci 1c.1 on end # PCIE_PORT2
device pci 1c.2 off end # PCIE_PORT3
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4959
-gerrit
commit ca9a50d6267b2499a3202541f43fa71456d71cf3
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Nov 11 14:55:47 2013 -0600
rambi: mainboard EC - SCI and SMI fixes
As rambi is a baytrail board it doesn't have a dedicated wake pin.
Therefore, one needs to enable the proper GPIO to wake up the sytem
before going into S3.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Put system into S3. Keyboard press created wake event. Also, typed
'lidclose' on EC console while at recovery screen. Machine properly
shutdown.
Change-Id: Ic67b6bce93d57c620f498505d83197e4ae34a07d
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176392
---
src/mainboard/google/rambi/ec.c | 1 +
src/mainboard/google/rambi/mainboard_smi.c | 13 ++++++++++---
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/google/rambi/ec.c b/src/mainboard/google/rambi/ec.c
index 0919f0f..c055d61 100644
--- a/src/mainboard/google/rambi/ec.c
+++ b/src/mainboard/google/rambi/ec.c
@@ -43,6 +43,7 @@ void mainboard_ec_init(void)
} else {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S5_WAKE_EVENTS);
+ google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
}
/* Clear wake events, these are enabled on entry to sleep */
diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c
index ac5c841..09a8580 100644
--- a/src/mainboard/google/rambi/mainboard_smi.c
+++ b/src/mainboard/google/rambi/mainboard_smi.c
@@ -28,6 +28,9 @@
#include <baytrail/nvs.h>
#include <baytrail/pmc.h>
+/* The wake gpio is SUS_GPIO[0]. */
+#define WAKE_GPIO_EN SUS_GPIO_EN0
+
int mainboard_io_trap_handler(int smif)
{
switch (smif) {
@@ -67,7 +70,7 @@ static uint8_t mainboard_smi_ec(void)
/* Go to S5 */
pm1_cnt = inl(pmbase + PM1_CNT);
- pm1_cnt |= SLP_TYP | (SLP_TYP_S5 << SLP_TYP_SHIFT);
+ pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT);
outl(pm1_cnt, pmbase + PM1_CNT);
break;
}
@@ -75,9 +78,11 @@ static uint8_t mainboard_smi_ec(void)
return cmd;
}
-void mainboard_smi_gpi(uint32_t gpi_sts)
+/* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that
+ * this includes the enable bits in the lower 16 bits. */
+void mainboard_smi_gpi(uint32_t alt_gpio_smi)
{
- if (gpi_sts & (1 << EC_SMI_GPI)) {
+ if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
/* Process all pending events */
while (mainboard_smi_ec() != 0);
}
@@ -97,6 +102,8 @@ void mainboard_smi_sleep(uint8_t slp_typ)
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
+ /* Enable wake pin in GPE block. */
+ enable_gpe(WAKE_GPIO_EN);
break;
case 5:
if (smm_get_gnvs()->s5u0 == 0)
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4949
-gerrit
commit 7b2f15730cc9b094c9c22ee0cfc21e824068478a
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Nov 7 14:33:21 2013 -0600
baytrail: include mainboard's superio.asl
The mainboard needs an opportunity to hang devices off of
the LPC device. Therefore, provide this opportunity for the
mainboard.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Buit and booted with keyboard. Keys work.
Change-Id: Ie2b660ad43e86d9237b0b0bb0720b069670bc537
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176133
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/baytrail/acpi/lpc.asl | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl
index 24fa9c7..408d2b4 100644
--- a/src/soc/intel/baytrail/acpi/lpc.asl
+++ b/src/soc/intel/baytrail/acpi/lpc.asl
@@ -138,6 +138,9 @@ Device (LPCB)
})
}
+ // Include mainboard's superio.asl file.
+ #include "acpi/superio.asl"
+
#ifdef ENABLE_TPM
Device (TPM) // Trusted Platform Module
{